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FPGA: fix occasional erroneous write inhibit

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This commit is contained in:
ikari 2011-11-10 23:41:33 +01:00
parent bd1f5215db
commit 93a12f3ca1
2 changed files with 4 additions and 4 deletions
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4
verilog/sd2snes/main.v
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@ -460,7 +460,7 @@ end
reg snes_wr_cycle;
always @(posedge CLK2) begin
if(SNES_cycle_start) begin
if(SNES_cycle_start & ~SNES_WR_start) begin
STATE <= ST_SNES_RD_ADDR;
end else if(SNES_WR_start) begin
STATE <= ST_SNES_WR_ADDR;
@ -605,6 +605,6 @@ assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
assign IRQ_DIR = 1'b0;
assign SNES_IRQ = 1'bZ;
assign p113_out = ROM_WE;
assign p113_out = 1'b0;
endmodule

4
verilog/sd2snes/sd2snes.xise
View File

@ -377,8 +377,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="8" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="8" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>