sd acceleration (FPGA side)
This commit is contained in:
ikari
parent
4bc455f12b
commit
97316353c3
@ -41,10 +41,11 @@ module mcu_cmd(
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output [23:0] rom_mask_out,
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// SPI "DMA" extension
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input spi_dma_ovr,
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input spi_dma_nextaddr,
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input [7:0] spi_dma_sram_data,
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input spi_dma_sram_we
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output SD_DMA_EN,
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input SD_DMA_STATUS,
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input SD_DMA_NEXTADDR,
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input [7:0] SD_DMA_SRAM_DATA,
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input SD_DMA_SRAM_WE
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);
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reg [3:0] MAPPER_BUF;
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@ -56,7 +57,10 @@ reg [7:0] MCU_DATA_OUT_BUF;
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reg [7:0] MCU_DATA_IN_BUF;
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reg [1:0] mcu_nextaddr_buf;
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wire mcu_nextaddr;
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wire spi_dma_nextaddr_trig;
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reg SD_DMA_ENr;
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assign SD_DMA_EN = SD_DMA_ENr;
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reg [2:0] spi_dma_nextaddr_r;
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reg [1:0] SRAM_MASK_IDX;
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@ -68,18 +72,23 @@ assign spi_data_out = MCU_DATA_IN_BUF;
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initial begin
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ADDR_OUT_BUF = 0;
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spi_dma_nextaddr_r = 0;
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SD_DMA_ENr = 0;
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end
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// command interpretation
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always @(posedge clk) begin
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if (cmd_ready) begin
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case (cmd_data[7:4])
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4'h3:
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4'h3: // select mapper
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MAPPER_BUF <= cmd_data[3:0];
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4'h4: // SD DMA
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SD_DMA_ENr <= 1;
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// 4'hE:
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// select memory unit
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endcase
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end else if (param_ready) begin
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case (cmd_data[7:4])
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4'h0:
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case (cmd_data[7:0])
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8'h00:
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case (spi_byte_cnt)
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32'h2: begin
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ADDR_OUT_BUF[23:16] <= param_data;
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@ -90,7 +99,7 @@ always @(posedge clk) begin
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32'h4:
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ADDR_OUT_BUF[7:0] <= param_data;
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endcase
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4'h1:
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8'h01:
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case (spi_byte_cnt)
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32'h2:
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ROM_MASK[23:16] <= param_data;
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@ -99,7 +108,7 @@ always @(posedge clk) begin
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32'h4:
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ROM_MASK[7:0] <= param_data;
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endcase
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4'h2:
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8'h02:
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case (spi_byte_cnt)
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32'h2:
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SAVERAM_MASK[23:16] <= param_data;
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@ -108,11 +117,15 @@ always @(posedge clk) begin
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32'h4:
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SAVERAM_MASK[7:0] <= param_data;
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endcase
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4'h9:
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8'h40:
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SD_DMA_ENr <= 1'b0;
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8'h90:
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MCU_DATA_OUT_BUF <= param_data;
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8'h91:
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MCU_DATA_OUT_BUF <= param_data;
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endcase
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end
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if (spi_dma_nextaddr_trig | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[0]) && (spi_byte_cnt > (32'h1+cmd_data[4]))))
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if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[0]) && (spi_byte_cnt > (32'h1+cmd_data[4]))))
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ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
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end
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@ -121,6 +134,8 @@ always @(posedge clk) begin
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if (spi_bit_cnt == 3'h7)
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if (cmd_data[7:0] == 8'hF0)
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MCU_DATA_IN_BUF <= 8'hA5;
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else if (cmd_data[7:0] == 8'hF1)
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MCU_DATA_IN_BUF <= {SD_DMA_STATUS, 7'b0};
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else if (cmd_data[7:0] == 8'hFF)
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MCU_DATA_IN_BUF <= param_data;
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else
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@ -135,10 +150,6 @@ always @(posedge clk) begin
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mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b0};
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end
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assign spi_dma_nextaddr_trig = (spi_dma_nextaddr_r[2:1] == 2'b01);
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always @(posedge clk) begin
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spi_dma_nextaddr_r <= {spi_dma_nextaddr_r[1:0], spi_dma_nextaddr};
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end
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// r/w pulse
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always @(posedge clk) begin
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@ -159,9 +170,9 @@ end
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assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
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assign mcu_read = MCU_READ_BUF;
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assign mcu_write = spi_dma_ovr ? spi_dma_sram_we : MCU_WRITE_BUF;
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assign mcu_write = SD_DMA_STATUS ? SD_DMA_SRAM_WE : MCU_WRITE_BUF;
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assign addr_out = ADDR_OUT_BUF;
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assign mcu_data_out = spi_dma_ovr ? spi_dma_sram_data : MCU_DATA_OUT_BUF;
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assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
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assign mcu_mapper = MAPPER_BUF;
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assign mcu_sram_size = SRAM_SIZE_BUF;
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assign rom_mask_out = ROM_MASK;
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@ -1,4 +1,4 @@
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NET "CLKIN" TNM_NET = CLKIN;
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NET "CLKIN" TNM_NET = "CLKIN";
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TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.579 MHz HIGH 50 %;
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NET "SNES_CS" IOSTANDARD = LVCMOS33;
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NET "SNES_READ" IOSTANDARD = LVCMOS33;
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@ -11,13 +11,13 @@ NET "CLKIN" IOSTANDARD = LVCMOS33;
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NET "SPI_SS" PULLUP;
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//NET "DCM_RST" LOC = P46;
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//NET "DCM_RST" IOSTANDARD = LVCMOS33;
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NET "IRQ_DIR" IOSTANDARD = LVCMOS33;
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NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33;
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NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33;
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NET "SNES_IRQ" IOSTANDARD = LVCMOS33;
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NET "SPI_DMA_CTRL" PULLUP;
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# PlanAhead generated physical constraints
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NET "ROM_CE" LOC = P172;
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NET "ROM_CE" IOSTANDARD = LVCMOS33;
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NET "ROM_CE" DRIVE = 8;
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NET "SNES_ADDR[0]" LOC = P119;
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NET "SNES_ADDR[10]" LOC = P146;
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@ -52,409 +52,316 @@ NET "SNES_DATA[5]" LOC = P106;
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NET "SNES_DATA[6]" LOC = P101;
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NET "SNES_DATA[7]" LOC = P97;
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# PlanAhead generated physical constraints
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NET "CLKIN" LOC = P80;
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NET "IRQ_DIR" LOC = P113;
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// NET "RST" LOC = P113;
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NET "MCU_OVR" LOC = P92;
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# PlanAhead generated IO constraints
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NET "MCU_OVR" IOSTANDARD = LVCMOS33;
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NET "MCU_OVR" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[0]" LOC = P166;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[0]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[0]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[10]" LOC = P197;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[10]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[10]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[11]" LOC = P196;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[11]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[11]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[12]" LOC = P2;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[12]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[12]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[13]" LOC = P194;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[13]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[13]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[14]" LOC = P200;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[14]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[14]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[15]" LOC = P184;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[15]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[15]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[16]" LOC = P199;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[16]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[16]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[17]" LOC = P11;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[17]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[17]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[18]" LOC = P3;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[18]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[18]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[19]" LOC = P4;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[19]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[19]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[1]" LOC = P168;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[1]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[1]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[20]" LOC = P191;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[20]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[20]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[21]" LOC = P203;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[21]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[21]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[22]" LOC = P198;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[22]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[22]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[2]" LOC = P171;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[2]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[2]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[3]" LOC = P165;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[3]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[3]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[4]" LOC = P169;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[4]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[4]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[5]" LOC = P18;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[5]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[5]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[6]" LOC = P175;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[6]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[6]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[7]" LOC = P167;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[7]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[7]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[8]" LOC = P205;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[8]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[8]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_ADDR[9]" LOC = P204;
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# PlanAhead generated IO constraints
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NET "ROM_ADDR[9]" IOSTANDARD = LVCMOS33;
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NET "ROM_ADDR[9]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_BHE" LOC = P161;
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# PlanAhead generated IO constraints
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NET "ROM_BHE" IOSTANDARD = LVCMOS33;
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NET "ROM_BHE" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_BLE" LOC = P156;
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# PlanAhead generated IO constraints
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NET "ROM_BLE" IOSTANDARD = LVCMOS33;
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NET "ROM_BLE" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "IRQ_DIR" LOC = P113;
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NET "IRQ_DIR" IOSTANDARD = LVCMOS33;
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NET "IRQ_DIR" DRIVE = 8;
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NET "ROM_CE" LOC = P172;
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# PlanAhead generated IO constraints
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NET "ROM_CE" IOSTANDARD = LVCMOS33;
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NET "ROM_CE" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[0]" LOC = P176;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[0]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[0]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[10]" LOC = P15;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[10]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[10]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[11]" LOC = P12;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[11]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[11]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[12]" LOC = P10;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[12]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[12]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[13]" LOC = P7;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[13]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[13]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[14]" LOC = P9;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[14]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[14]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[15]" LOC = P5;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[15]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[15]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[1]" LOC = P178;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[1]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[1]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[2]" LOC = P181;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[2]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[2]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[3]" LOC = P182;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[3]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[3]" DRIVE = 8;
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# PlanAhead generated physical constraints
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NET "ROM_DATA[4]" LOC = P183;
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# PlanAhead generated IO constraints
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NET "ROM_DATA[4]" IOSTANDARD = LVCMOS33;
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NET "ROM_DATA[4]" DRIVE = 8;
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||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_DATA[5]" LOC = P187;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_DATA[5]" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_DATA[5]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_DATA[6]" LOC = P185;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_DATA[6]" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_DATA[6]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_DATA[7]" LOC = P189;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_DATA[7]" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_DATA[7]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_DATA[8]" LOC = P16;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_DATA[8]" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_DATA[8]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_DATA[9]" LOC = P13;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_DATA[9]" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_DATA[9]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_OE" LOC = P162;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_OE" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_OE" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "ROM_WE" LOC = P190;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "ROM_WE" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_WE" DRIVE = 8;
|
||||
@ -507,14 +414,12 @@ NET "SNES_ADDR[8]" DRIVE = 8;
|
||||
NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[9]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "SNES_CPU_CLK" LOC = P94;
|
||||
NET "SNES_CS" LOC = P116;
|
||||
NET "SNES_DATABUS_DIR" LOC = P111;
|
||||
NET "SNES_DATABUS_OE" LOC = P109;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[0]" DRIVE = 8;
|
||||
@ -533,79 +438,75 @@ NET "SNES_DATA[6]" DRIVE = 8;
|
||||
NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[7]" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "SNES_IRQ" LOC = P114;
|
||||
NET "SNES_READ" LOC = P115;
|
||||
NET "SNES_REFRESH" LOC = P155;
|
||||
NET "SNES_WRITE" LOC = P95;
|
||||
NET "SPI_DMA_CTRL" LOC = P83;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "SPI_DMA_CTRL" IOSTANDARD = LVCMOS33;
|
||||
NET "SPI_DMA_CTRL" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "SPI_MISO" LOC = P72;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "SPI_MISO" IOSTANDARD = LVCMOS33;
|
||||
NET "SPI_MISO" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "SPI_MOSI" LOC = P74;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "SPI_MOSI" IOSTANDARD = LVCMOS33;
|
||||
NET "SPI_MOSI" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "SPI_SCK" LOC = P71;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "SPI_SCK" IOSTANDARD = LVCMOS33;
|
||||
NET "SPI_SCK" DRIVE = 8;
|
||||
NET "SPI_SCK" PULLUP;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "SPI_SS" LOC = P68;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "SPI_SS" IOSTANDARD = LVCMOS33;
|
||||
NET "SPI_SS" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "DAC_LRCK" LOC = P77;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "DAC_LRCK" IOSTANDARD = LVCMOS33;
|
||||
NET "DAC_LRCK" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "DAC_MCLK" LOC = P76;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "DAC_MCLK" IOSTANDARD = LVCMOS33;
|
||||
NET "DAC_MCLK" DRIVE = 8;
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
|
||||
NET "DAC_SDOUT" LOC = P78;
|
||||
|
||||
# PlanAhead generated IO constraints
|
||||
|
||||
NET "DAC_SDOUT" IOSTANDARD = LVCMOS33;
|
||||
NET "DAC_SDOUT" DRIVE = 8;
|
||||
|
||||
# PlanAhead Generated physical constraints
|
||||
|
||||
NET "SD_CLK" LOC = P64;
|
||||
NET "SD_CMD" LOC = P67;
|
||||
NET "SD_DAT[0]" LOC = P65;
|
||||
NET "SD_DAT[1]" LOC = P79;
|
||||
NET "SD_DAT[2]" LOC = P62;
|
||||
NET "SD_DAT[3]" LOC = P63;
|
||||
|
||||
# PlanAhead Generated IO constraints
|
||||
|
||||
NET "SD_CLK" IOSTANDARD = LVCMOS33;
|
||||
NET "SD_CMD" IOSTANDARD = LVCMOS33;
|
||||
NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
|
||||
NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;
|
||||
NET "SD_DAT[2]" IOSTANDARD = LVCMOS33;
|
||||
NET "SD_DAT[3]" IOSTANDARD = LVCMOS33;
|
||||
|
||||
@ -50,18 +50,16 @@ module main(
|
||||
input SPI_SS,
|
||||
inout SPI_SCK,
|
||||
input MCU_OVR,
|
||||
inout SPI_DMA_CTRL,
|
||||
|
||||
output DAC_MCLK,
|
||||
output DAC_LRCK,
|
||||
output DAC_SDOUT,
|
||||
|
||||
/* SD signals */
|
||||
inout SD_MOSI,
|
||||
input SD_MISO,
|
||||
inout SD_SS,
|
||||
inout SD_SCK
|
||||
|
||||
input [3:0] SD_DAT,
|
||||
inout SD_CMD,
|
||||
inout SD_CLK
|
||||
|
||||
/* debug */
|
||||
//output DCM_IN_STOPPED,
|
||||
//output DCM_FX_STOPPED
|
||||
@ -80,10 +78,19 @@ wire [7:0] MCU_OUT_DATA;
|
||||
wire [3:0] MAPPER;
|
||||
wire [23:0] SAVERAM_MASK;
|
||||
wire [23:0] ROM_MASK;
|
||||
wire [23:0] spi_dma_addr;
|
||||
wire [7:0] spi_dma_sram_data;
|
||||
wire spi_dma_trig = 1'b1; //SPI_DMA_CTRL;
|
||||
wire [7:0] SD_DMA_SRAM_DATA;
|
||||
//wire SD_DMA_EN; //SPI_DMA_CTRL;
|
||||
|
||||
sd_dma snes_sd_dma(.CLK(CLK2),
|
||||
.SD_DAT(SD_DAT),
|
||||
.SD_CLK(SD_CLK),
|
||||
.SD_DMA_EN(SD_DMA_EN),
|
||||
.SD_DMA_STATUS(SD_DMA_STATUS),
|
||||
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
|
||||
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
|
||||
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR)
|
||||
);
|
||||
|
||||
dac_test snes_dac_test(.clkin(CLK2),
|
||||
.mclk(DAC_MCLK),
|
||||
.lrck(DAC_LRCK),
|
||||
@ -103,10 +110,7 @@ spi snes_spi(.clk(CLK2),
|
||||
.startmessage(spi_startmessage),
|
||||
.input_data(spi_input_data),
|
||||
.byte_cnt(spi_byte_cnt),
|
||||
.bit_cnt(spi_bit_cnt),
|
||||
|
||||
.spi_dma_sck(spi_dma_sck),
|
||||
.spi_dma_ovr(spi_dma_ovr)
|
||||
.bit_cnt(spi_bit_cnt)
|
||||
);
|
||||
|
||||
mcu_cmd snes_mcu_cmd(
|
||||
@ -129,27 +133,13 @@ mcu_cmd snes_mcu_cmd(
|
||||
.startmessage(spi_startmessage),
|
||||
.saveram_mask_out(SAVERAM_MASK),
|
||||
.rom_mask_out(ROM_MASK),
|
||||
|
||||
.spi_dma_ovr(spi_dma_ovr),
|
||||
.spi_dma_nextaddr(spi_dma_nextaddr),
|
||||
.spi_dma_sram_data(spi_dma_sram_data),
|
||||
.spi_dma_sram_we(spi_dma_sram_we)
|
||||
.SD_DMA_EN(SD_DMA_EN),
|
||||
.SD_DMA_STATUS(SD_DMA_STATUS),
|
||||
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
|
||||
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
|
||||
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE)
|
||||
);
|
||||
|
||||
spi_dma snes_spi_dma(
|
||||
.clk(CLK2),
|
||||
.spi_dma_ovr(spi_dma_ovr), // to spi, mcu_cmd
|
||||
.spi_dma_miso(SPI_MISO), // to spi
|
||||
.spi_dma_sck(spi_dma_sck), // to spi
|
||||
.spi_dma_trig(spi_dma_trig), // from mcu
|
||||
.spi_dma_nextaddr(spi_dma_nextaddr), // to mcu_cmd?
|
||||
.spi_dma_sram_data(spi_dma_sram_data), // to mcu_cmd?
|
||||
.spi_dma_sram_we(spi_dma_sram_we), // to mcu_cmd?
|
||||
.spi_dma_done(spi_dma_done) // to mcu
|
||||
);
|
||||
|
||||
assign SPI_DMA_CTRL = spi_dma_ovr ? 1'b0 : 1'bZ;
|
||||
|
||||
// dcm1: dfs 4x
|
||||
my_dcm snes_dcm(.CLKIN(CLKIN),
|
||||
.CLKFX(CLK2),
|
||||
|
||||
@ -1,642 +0,0 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 00:20:33 07/14/2009
|
||||
// Design Name: main
|
||||
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/main_tf2.v
|
||||
// Project Name: sd2snes
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Verilog Test Fixture created by ISE for module: main
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module main_tf2;
|
||||
|
||||
// Inputs
|
||||
reg CLKIN;
|
||||
reg [23:0] SNES_ADDR;
|
||||
reg SNES_READ;
|
||||
reg SNES_WRITE;
|
||||
reg SNES_CS;
|
||||
reg SNES_CPU_CLK;
|
||||
reg SNES_REFRESH;
|
||||
reg SPI_MOSI;
|
||||
reg SPI_SS;
|
||||
reg SPI_SCK;
|
||||
reg AVR_ENA;
|
||||
|
||||
// Outputs
|
||||
wire SNES_DATABUS_OE;
|
||||
wire SNES_DATABUS_DIR;
|
||||
wire [19:0] SRAM_ADDR;
|
||||
wire [3:0] ROM_SEL;
|
||||
wire SRAM_OE;
|
||||
wire SRAM_WE;
|
||||
wire SPI_MISO;
|
||||
wire MODE;
|
||||
wire SRAM_BHE;
|
||||
wire SRAM_BLE;
|
||||
|
||||
// Bidirs
|
||||
wire [7:0] SNES_DATA;
|
||||
wire SNES_IRQ;
|
||||
wire [15:0] SRAM_DATA;
|
||||
|
||||
reg [15:0] SRAM_DATA_BUF;
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
main uut (
|
||||
.CLKIN(CLKIN),
|
||||
.SNES_ADDR(SNES_ADDR),
|
||||
.SNES_READ(SNES_READ),
|
||||
.SNES_WRITE(SNES_WRITE),
|
||||
.SNES_CS(SNES_CS),
|
||||
.SNES_DATA(SNES_DATA),
|
||||
.SNES_CPU_CLK(SNES_CPU_CLK),
|
||||
.SNES_REFRESH(SNES_REFRESH),
|
||||
.SNES_IRQ(SNES_IRQ),
|
||||
.IRQ_DIR(IRQ_DIR),
|
||||
.SNES_DATABUS_OE(SNES_DATABUS_OE),
|
||||
.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
|
||||
.SRAM_DATA(SRAM_DATA),
|
||||
.SRAM_ADDR(SRAM_ADDR),
|
||||
.SRAM_CE2(ROM_SEL),
|
||||
.SRAM_OE(SRAM_OE),
|
||||
.SRAM_WE(SRAM_WE),
|
||||
.SPI_MOSI(SPI_MOSI),
|
||||
.SPI_MISO(SPI_MISO),
|
||||
.SPI_SS(SPI_SS),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.AVR_ENA(AVR_ENA),
|
||||
.SRAM_BHE(SRAM_BHE),
|
||||
.SRAM_BLE(SRAM_BLE)
|
||||
);
|
||||
|
||||
initial begin
|
||||
// Initialize Inputs
|
||||
CLKIN = 0;
|
||||
SNES_ADDR = 0;
|
||||
SNES_READ = 1;
|
||||
SNES_WRITE = 1;
|
||||
SNES_CS = 0;
|
||||
SNES_CPU_CLK = 0;
|
||||
SNES_REFRESH = 0;
|
||||
SPI_MOSI = 0;
|
||||
SPI_SS = 1;
|
||||
SPI_SCK = 0;
|
||||
AVR_ENA = 0;
|
||||
|
||||
// Wait 100 ns for global reset to finish
|
||||
#100;
|
||||
// Wait for DCM to stabilize
|
||||
#5000;
|
||||
// Add stimulus here
|
||||
// Add stimulus here
|
||||
SPI_SS = 0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#100 SPI_SS=1;
|
||||
#200;
|
||||
SPI_SS=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_SS=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
#100 SPI_SS=1;
|
||||
#200;
|
||||
SPI_SS=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_SS=1;
|
||||
#200;
|
||||
|
||||
/*
|
||||
* READ TEST
|
||||
*/
|
||||
AVR_ENA=1;
|
||||
SPI_SS=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#100;
|
||||
#100;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_SS=1;
|
||||
#300;
|
||||
SPI_SS=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
SPI_SS=1;
|
||||
AVR_ENA=1;
|
||||
#280;
|
||||
// Initialize Inputs
|
||||
SNES_ADDR = 24'h223456;
|
||||
SNES_READ = 1;
|
||||
SNES_WRITE = 1;
|
||||
SNES_CS = 0;
|
||||
AVR_ENA = 1;
|
||||
SRAM_DATA_BUF = 8'hff;
|
||||
// Wait for global reset to finish
|
||||
#276;
|
||||
SNES_ADDR <= 24'h123456;
|
||||
SNES_READ <= 0;
|
||||
#176;
|
||||
SNES_READ <= 1;
|
||||
#100;
|
||||
SNES_WRITE <= 0;
|
||||
#176;
|
||||
SNES_WRITE <= 1;
|
||||
#100;
|
||||
SNES_READ <= 0;
|
||||
#276;
|
||||
// AVR_READ <= 1;
|
||||
// Add stimulus here
|
||||
SPI_SS = 0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#200;
|
||||
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=0;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
SPI_MOSI=1;
|
||||
#100 SPI_SCK=1;
|
||||
#100 SPI_SCK=0;
|
||||
#100 SPI_SS=1;
|
||||
#200;
|
||||
|
||||
|
||||
end
|
||||
always begin
|
||||
#23 CLKIN = ~CLKIN;
|
||||
end
|
||||
always begin
|
||||
#150 SNES_READ = ~SNES_READ;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -38,56 +38,18 @@
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="tf_spi.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="main_tf2.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="avr_cmd.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="dcm2.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="dcm_srl16.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="spi_dma.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="tf_spi_dma.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="tf_main_3.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="dac_test.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="sd_dma.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
@ -95,7 +57,7 @@
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Pads" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Advanced FSM Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -163,10 +125,11 @@
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="EDIF" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@ -289,7 +252,7 @@
|
||||
<property xil_pn:name="Number of Summary Paths" xil_pn:value="10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Balanced" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@ -319,7 +282,7 @@
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs Only" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
@ -20,7 +20,7 @@
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module spi(input clk,
|
||||
inout SCK,
|
||||
input SCK,
|
||||
input MOSI,
|
||||
inout MISO,
|
||||
input SSEL,
|
||||
@ -32,44 +32,21 @@ module spi(input clk,
|
||||
output startmessage,
|
||||
input [7:0] input_data,
|
||||
output [31:0] byte_cnt,
|
||||
output [2:0] bit_cnt,
|
||||
output [2:0] bit_cnt
|
||||
|
||||
// spi "DMA" extension
|
||||
input spi_dma_sck,
|
||||
input spi_dma_ovr);
|
||||
// SD "DMA" extension
|
||||
/*input sd_dma_sck,
|
||||
input sd_dma_ovr*/);
|
||||
|
||||
reg [7:0] cmd_data_r;
|
||||
reg [7:0] param_data_r;
|
||||
|
||||
// sync SCK to the FPGA clock using a 3-bits shift register
|
||||
// SCK is an OUTPUT in "DMA" mode
|
||||
reg [2:0] spi_dma_ovr_r;
|
||||
reg [9:0] spi_dma_leadout_cnt;
|
||||
reg spi_dma_leadout;
|
||||
initial begin
|
||||
spi_dma_ovr_r = 3'b000;
|
||||
spi_dma_leadout_cnt <= 10'b0000000000;
|
||||
end
|
||||
always @(posedge clk) spi_dma_ovr_r <= {spi_dma_ovr_r[1:0], spi_dma_ovr};
|
||||
wire spi_dma_ovr_falling = (spi_dma_ovr_r[1:0] == 2'b10);
|
||||
always @(posedge clk) begin
|
||||
if (spi_dma_ovr_falling) begin
|
||||
spi_dma_leadout <= 1;
|
||||
spi_dma_leadout_cnt <= 0;
|
||||
end else begin
|
||||
if(spi_dma_leadout_cnt == 100)
|
||||
spi_dma_leadout <= 0;
|
||||
if(spi_dma_leadout)
|
||||
spi_dma_leadout_cnt <= spi_dma_leadout_cnt + 1;
|
||||
end
|
||||
end
|
||||
assign SCK = spi_dma_ovr ? spi_dma_sck : spi_dma_leadout ? 1'b0 : 1'bZ;
|
||||
reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
|
||||
wire SCK_risingedge = spi_dma_ovr ? 0 : (SCKr[1:0]==2'b01); // now we can detect SCK rising edges
|
||||
wire SCK_fallingedge = spi_dma_ovr ? 0 : (SCKr[1:0]==2'b10); // and falling edges
|
||||
reg [2:0] SCKr;
|
||||
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
|
||||
|
||||
// wire SCK_risingedge = spi_dma_ovr ? 0 : ({SCKr[0], SCK}==2'b01); // now we can detect SCK rising edges
|
||||
// wire SCK_fallingedge = spi_dma_ovr ? 0 : ({SCKr[0], SCK}==2'b10); // and falling edges
|
||||
wire SCK_risingedge = (SCKr[1:0]==2'b01); // now we can detect SCK rising edges
|
||||
wire SCK_fallingedge = (SCKr[1:0]==2'b10); // and falling edges
|
||||
|
||||
// same thing for SSEL
|
||||
reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
|
||||
@ -130,8 +107,7 @@ always @(posedge clk) begin
|
||||
end
|
||||
end
|
||||
|
||||
// Slave out is an INPUT in "DMA" mode
|
||||
assign MISO = spi_dma_ovr ? 1'bZ : SSEL_active ? byte_data_sent[7] : 1'bZ; // send MSB first
|
||||
assign MISO = SSEL_active ? byte_data_sent[7] : 1'bZ; // send MSB first
|
||||
|
||||
reg cmd_ready_r;
|
||||
reg param_ready_r;
|
||||
|
||||
@ -1,147 +0,0 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 22:18:56 12/20/2009
|
||||
// Design Name:
|
||||
// Module Name: spi_dma
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module spi_dma(
|
||||
input clk,
|
||||
output spi_dma_ovr,
|
||||
input spi_dma_miso,
|
||||
output spi_dma_sck,
|
||||
input spi_dma_trig,
|
||||
output spi_dma_nextaddr,
|
||||
output [7:0] spi_dma_sram_data,
|
||||
output spi_dma_sram_we,
|
||||
output spi_dma_done
|
||||
);
|
||||
|
||||
reg spi_dma_sram_we_r;
|
||||
reg spi_dma_done_r;
|
||||
reg spi_dma_ovr_r;
|
||||
reg spi_dma_nextaddr_r;
|
||||
reg [7:0] spi_dma_sram_data_r;
|
||||
|
||||
reg [3:0] spi_dma_bitcnt; // extra bits
|
||||
reg [9:0] spi_dma_bytecnt;
|
||||
reg [3:0] spi_dma_clkcnt;
|
||||
reg [3:0] spi_dma_sck_int_r;
|
||||
reg [5:0] spi_dma_trig_r;
|
||||
reg [4:0] spi_dma_miso_r;
|
||||
reg spi_dma_sck_out_r;
|
||||
reg spi_dma_sck_out_r2;
|
||||
|
||||
initial begin
|
||||
spi_dma_clkcnt <= 4'b0000;
|
||||
spi_dma_bitcnt <= 4'b1110;
|
||||
spi_dma_bytecnt <= 10'b0000000000;
|
||||
spi_dma_nextaddr_r <= 1'b0;
|
||||
spi_dma_sram_we_r <= 1'b1;
|
||||
spi_dma_done_r <= 1'b1;
|
||||
spi_dma_sck_int_r <= 4'b0000;
|
||||
spi_dma_trig_r <= 6'b000000;
|
||||
spi_dma_ovr_r <= 1'b0;
|
||||
spi_dma_sck_out_r <= 1'b0;
|
||||
spi_dma_sck_out_r2 <= 1'b0;
|
||||
end
|
||||
|
||||
// synthesize clock
|
||||
wire spi_dma_sck_int = spi_dma_clkcnt[1];
|
||||
assign spi_dma_sck = spi_dma_sck_out_r & spi_dma_sck_out_r2;
|
||||
|
||||
always @(posedge clk) begin
|
||||
spi_dma_clkcnt <= spi_dma_clkcnt + 1;
|
||||
spi_dma_sck_int_r <= {spi_dma_sck_int_r[2:0], spi_dma_sck_int};
|
||||
spi_dma_trig_r <= {spi_dma_trig_r[4:0], spi_dma_trig};
|
||||
spi_dma_miso_r <= {spi_dma_miso_r[3:0], spi_dma_miso};
|
||||
end
|
||||
|
||||
wire spi_dma_trig_rising = (spi_dma_trig_r[5:1] == 5'b00011);
|
||||
wire spi_dma_trig_falling = (spi_dma_trig_r[5:1] == 5'b11100);
|
||||
wire spi_dma_sck_rising = (spi_dma_sck_int_r[2:1] == 2'b01);
|
||||
wire spi_dma_sck_falling = (spi_dma_sck_int_r[2:1] == 2'b10);
|
||||
wire spi_dma_sck_rising2 = (spi_dma_sck_int_r[2:1] == 2'b01);
|
||||
wire spi_dma_sck_falling2 = (spi_dma_sck_int_r[2:1] == 2'b10);
|
||||
|
||||
assign spi_dma_nextaddr = spi_dma_nextaddr_r & (spi_dma_bytecnt < 512);
|
||||
assign spi_dma_sram_data = spi_dma_sram_data_r;
|
||||
assign spi_dma_sram_we = spi_dma_sram_we_r | (spi_dma_bytecnt > 511);
|
||||
assign spi_dma_done = spi_dma_done_r;
|
||||
assign spi_dma_ovr = spi_dma_ovr_r;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (spi_dma_trig_falling & !spi_dma_ovr_r) begin
|
||||
spi_dma_done_r <= 0;
|
||||
spi_dma_ovr_r <= 1;
|
||||
end else if (spi_dma_bitcnt == 0 && spi_dma_bytecnt == 514) begin
|
||||
spi_dma_done_r <= 1;
|
||||
spi_dma_ovr_r <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(spi_dma_sck_falling)
|
||||
spi_dma_sck_out_r2 <= 0;
|
||||
else if(spi_dma_sck_rising)
|
||||
spi_dma_sck_out_r2 <= 1;
|
||||
end
|
||||
|
||||
// fetch a little later
|
||||
//always @(posedge spi_dma_sck) begin
|
||||
// if (/*spi_dma_sck_rising & */spi_dma_ovr_r & spi_dma_bitcnt <= 8)
|
||||
// spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
|
||||
//end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(spi_dma_sck_rising & spi_dma_ovr_r) begin
|
||||
if (spi_dma_bitcnt < 8) begin
|
||||
spi_dma_sck_out_r <= 1;
|
||||
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
|
||||
spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
|
||||
end else if (spi_dma_bitcnt == 8) begin
|
||||
spi_dma_sck_out_r <= 0;
|
||||
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
|
||||
spi_dma_sram_data_r <= {spi_dma_sram_data_r[6:0], spi_dma_miso_r[0]};
|
||||
end else if (spi_dma_bitcnt == 9) begin
|
||||
spi_dma_sck_out_r <= 0;
|
||||
spi_dma_sram_we_r <= 0;
|
||||
spi_dma_bitcnt <= 10;
|
||||
end else if (spi_dma_bitcnt == 10) begin
|
||||
spi_dma_sram_we_r <= 1;
|
||||
spi_dma_nextaddr_r <= 1;
|
||||
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
|
||||
end else if (spi_dma_bitcnt == 11) begin
|
||||
spi_dma_nextaddr_r <= 0;
|
||||
spi_dma_bytecnt <= spi_dma_bytecnt + 1;
|
||||
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
|
||||
end else if (spi_dma_bitcnt == 12) begin
|
||||
spi_dma_bitcnt <= 0;
|
||||
end else if (spi_dma_bitcnt == 4'b1101) begin
|
||||
spi_dma_sck_out_r <= 0;
|
||||
spi_dma_bitcnt <= 4'b1110;
|
||||
end else if (spi_dma_bitcnt == 4'b1110) begin
|
||||
spi_dma_bitcnt <= spi_dma_bitcnt + 1;
|
||||
end else if (spi_dma_bitcnt == 4'b1111) begin
|
||||
spi_dma_bitcnt <= 0;
|
||||
end
|
||||
end else if (spi_dma_trig_falling & !spi_dma_ovr_r) begin
|
||||
spi_dma_bitcnt <= 4'b1101;
|
||||
spi_dma_bytecnt <= 10'b0000000000;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,180 +0,0 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 23:11:58 05/13/2009
|
||||
// Design Name: main
|
||||
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/tf_main.v
|
||||
// Project Name: sd2snes
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Verilog Test Fixture created by ISE for module: main
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module tf_main;
|
||||
|
||||
// Inputs
|
||||
reg CLK;
|
||||
reg [2:0] MAPPER;
|
||||
reg [23:0] SNES_ADDR;
|
||||
reg SNES_READ;
|
||||
reg SNES_WRITE;
|
||||
reg SNES_CS;
|
||||
reg AVR_ENA;
|
||||
|
||||
// Outputs
|
||||
wire [20:0] SRAM_ADDR;
|
||||
wire [3:0] ROM_SEL;
|
||||
wire SRAM_OE;
|
||||
wire SRAM_WE;
|
||||
wire SNES_DATABUS_OE;
|
||||
wire SNES_DATABUS_DIR;
|
||||
wire MODE;
|
||||
|
||||
// Bidirs
|
||||
wire [7:0] SNES_DATA;
|
||||
wire [7:0] SRAM_DATA;
|
||||
wire [7:0] AVR_DATA;
|
||||
|
||||
reg [7:0] SRAM_DATA_BUF;
|
||||
reg [7:0] SNES_DATA_BUF;
|
||||
|
||||
SCK = 0;
|
||||
MOSI = 0;
|
||||
SSEL = 1;
|
||||
input_data = 0;
|
||||
|
||||
// Wait 100 ns for global reset to finish
|
||||
#100;
|
||||
|
||||
// Add stimulus here
|
||||
SSEL = 0;
|
||||
MOSI=1;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
MOSI=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
MOSI=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
MOSI=1;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
MOSI=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#200;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#200;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SCK=1;
|
||||
#100 SCK=0;
|
||||
#100 SSEL=1;
|
||||
|
||||
|
||||
end
|
||||
always begin
|
||||
#19 clk = ~clk;
|
||||
end
|
||||
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
main uut (
|
||||
.CLKIN(CLK),
|
||||
.MAPPER(MAPPER),
|
||||
.SNES_ADDR(SNES_ADDR),
|
||||
.SNES_READ(SNES_READ),
|
||||
.SNES_WRITE(SNES_WRITE),
|
||||
.SNES_CS(SNES_CS),
|
||||
.SNES_DATA(SNES_DATA),
|
||||
.SRAM_DATA(SRAM_DATA),
|
||||
.SRAM_ADDR(SRAM_ADDR),
|
||||
.ROM_SEL(ROM_SEL),
|
||||
.SRAM_OE(SRAM_OE),
|
||||
.SRAM_WE(SRAM_WE),
|
||||
.AVR_ENA(AVR_ENA),
|
||||
.SNES_DATABUS_OE(SNES_DATABUS_OE),
|
||||
.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
|
||||
.MODE(MODE)
|
||||
);
|
||||
|
||||
assign SRAM_DATA = SRAM_DATA_BUF;
|
||||
initial begin
|
||||
// Initialize Inputs
|
||||
CLK = 1;
|
||||
MAPPER = 0;
|
||||
SNES_ADDR = 24'h223456;
|
||||
SNES_READ = 1;
|
||||
SNES_WRITE = 1;
|
||||
SNES_CS = 0;
|
||||
AVR_ENA = 1;
|
||||
SRAM_DATA_BUF = 8'hff;
|
||||
// Wait for global reset to finish
|
||||
#276;
|
||||
SNES_ADDR <= 24'h123456;
|
||||
SNES_READ <= 0;
|
||||
#176;
|
||||
SNES_READ <= 1;
|
||||
#100;
|
||||
SNES_WRITE <= 0;
|
||||
#176;
|
||||
SNES_WRITE <= 1;
|
||||
#100;
|
||||
SNES_READ <= 0;
|
||||
#276;
|
||||
// AVR_READ <= 1;
|
||||
// Add stimulus here
|
||||
end
|
||||
|
||||
always
|
||||
#23 CLK <= ~CLK;
|
||||
// always begin
|
||||
// end
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,132 +0,0 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 04:03:25 12/21/2009
|
||||
// Design Name: main
|
||||
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/tf_main_3.v
|
||||
// Project Name: sd2snes
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Verilog Test Fixture created by ISE for module: main
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module tf_main_3;
|
||||
|
||||
// Inputs
|
||||
reg CLKIN;
|
||||
reg [23:0] SNES_ADDR;
|
||||
reg SNES_READ;
|
||||
reg SNES_WRITE;
|
||||
reg SNES_CS;
|
||||
reg SNES_CPU_CLK;
|
||||
reg SNES_REFRESH;
|
||||
reg SPI_MOSI;
|
||||
reg SPI_SS;
|
||||
reg AVR_ENA;
|
||||
|
||||
// Outputs
|
||||
wire SNES_DATABUS_OE;
|
||||
wire SNES_DATABUS_DIR;
|
||||
wire IRQ_DIR;
|
||||
wire [19:0] SRAM_ADDR;
|
||||
wire [3:0] SRAM_CE2;
|
||||
wire SRAM_OE;
|
||||
wire SRAM_WE;
|
||||
wire SRAM_BHE;
|
||||
wire SRAM_BLE;
|
||||
|
||||
// Bidirs
|
||||
wire [7:0] SNES_DATA;
|
||||
wire SNES_IRQ;
|
||||
wire [15:0] SRAM_DATA;
|
||||
wire SPI_MISO;
|
||||
wire SPI_SCK;
|
||||
wire SPI_DMA_CTRL;
|
||||
|
||||
reg SPI_DMA_CTRLdir;
|
||||
reg SPI_DMA_CTRLr;
|
||||
|
||||
reg SPI_MISOdir;
|
||||
reg SPI_MISOr;
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
main uut (
|
||||
.CLKIN(CLKIN),
|
||||
.SNES_ADDR(SNES_ADDR),
|
||||
.SNES_READ(SNES_READ),
|
||||
.SNES_WRITE(SNES_WRITE),
|
||||
.SNES_CS(SNES_CS),
|
||||
.SNES_DATA(SNES_DATA),
|
||||
.SNES_CPU_CLK(SNES_CPU_CLK),
|
||||
.SNES_REFRESH(SNES_REFRESH),
|
||||
.SNES_IRQ(SNES_IRQ),
|
||||
.SNES_DATABUS_OE(SNES_DATABUS_OE),
|
||||
.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
|
||||
.IRQ_DIR(IRQ_DIR),
|
||||
.SRAM_DATA(SRAM_DATA),
|
||||
.SRAM_ADDR(SRAM_ADDR),
|
||||
.SRAM_CE2(SRAM_CE2),
|
||||
.SRAM_OE(SRAM_OE),
|
||||
.SRAM_WE(SRAM_WE),
|
||||
.SRAM_BHE(SRAM_BHE),
|
||||
.SRAM_BLE(SRAM_BLE),
|
||||
.SPI_MOSI(SPI_MOSI),
|
||||
.SPI_MISO(SPI_MISO),
|
||||
.SPI_SS(SPI_SS),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.AVR_ENA(AVR_ENA),
|
||||
.SPI_DMA_CTRL(SPI_DMA_CTRL)
|
||||
);
|
||||
|
||||
initial begin
|
||||
// Initialize Inputs
|
||||
CLKIN = 0;
|
||||
SNES_ADDR = 0;
|
||||
SNES_READ = 0;
|
||||
SNES_WRITE = 0;
|
||||
SNES_CS = 0;
|
||||
SNES_CPU_CLK = 0;
|
||||
SNES_REFRESH = 0;
|
||||
SPI_MOSI = 0;
|
||||
SPI_SS = 0;
|
||||
AVR_ENA = 0;
|
||||
SPI_DMA_CTRLr = 1;
|
||||
SPI_DMA_CTRLdir = 0;
|
||||
SPI_MISOr = 0;
|
||||
SPI_MISOdir = 0;
|
||||
// Wait 100 ns for global reset to finish
|
||||
#100;
|
||||
#600; // dcm?
|
||||
// Add stimulus here
|
||||
SPI_DMA_CTRLr = 1;
|
||||
SPI_DMA_CTRLdir = 1;
|
||||
#100 SPI_DMA_CTRLr = 0;
|
||||
#100 SPI_DMA_CTRLr = 1'bZ;
|
||||
SPI_DMA_CTRLdir = 0;
|
||||
SPI_MISOdir = 1;
|
||||
#260 SPI_MISOr = 1;
|
||||
#80 SPI_MISOr = 0;
|
||||
#80 SPI_MISOr = 0;
|
||||
#80 SPI_MISOr = 1;
|
||||
#80 SPI_MISOr = 0;
|
||||
#80 SPI_MISOr = 1;
|
||||
#80 SPI_MISOr = 0;
|
||||
#80 SPI_MISOr = 1;
|
||||
end
|
||||
|
||||
assign SPI_DMA_CTRL = SPI_DMA_CTRLdir ? SPI_DMA_CTRLr : 1'bZ;
|
||||
assign SPI_MISO = SPI_MISOdir ? SPI_MISOr : 1'bZ;
|
||||
always #35 CLKIN = ~CLKIN;
|
||||
endmodule
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user