From 9a58016f264bf79169b1154abb5b74841a9acd3c Mon Sep 17 00:00:00 2001
From: Maximilian Rehkopf <ikari@elektra.(none)>
Date: Sat, 8 Oct 2011 02:29:38 +0200
Subject: [PATCH] FPGA: replace unneeded MCU_OVR signal

---
 verilog/sd2snes/address.v    |  1 -
 verilog/sd2snes/main.v       | 17 +++++++++--------
 verilog/sd2snes/sd2snes.xise |  4 ----
 3 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v
index b53624d..7ddb76e 100644
--- a/verilog/sd2snes/address.v
+++ b/verilog/sd2snes/address.v
@@ -25,7 +25,6 @@ module address(
   input SNES_CS,            // "CART" pin from SNES (active low)
   output [23:0] ROM_ADDR,   // Address to request from SRAM0
   output ROM_SEL,           // enable SRAM0 (active low)
-  input MCU_OVR,            // enable MCU master mode (active low)
   output IS_SAVERAM,        // address/CS mapped as SRAM?
   output IS_ROM,            // address mapped as ROM?
   output IS_WRITABLE,       // address somehow mapped as writable area?
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 66bdb41..8ed8514 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -151,6 +151,8 @@ sd_dma snes_sd_dma(
   .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
 );
 
+wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
+
 dac snes_dac(
   .clkin(CLK2),
   .sysclk(SNES_SYSCLK),
@@ -377,7 +379,6 @@ address snes_addr(
   .SNES_CS(SNES_CS),     // "CART" pin from SNES (active low)
   .ROM_ADDR(MAPPED_SNES_ADDR),   // Address to request from SRAM (active low)
   .ROM_SEL(ROM_SEL),     // which SRAM unit to access
-  .MCU_OVR(MCU_OVR),     // enable MCU mode (active low)
   .IS_SAVERAM(IS_SAVERAM),
   .IS_ROM(IS_ROM),
   .IS_WRITABLE(IS_WRITABLE),
@@ -497,8 +498,8 @@ end
 
 wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
 
-assign ROM_ADDR  = (!MCU_OVR) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
-assign ROM_ADDR0 = (!MCU_OVR) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
+assign ROM_ADDR  = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
+assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
 
 reg ROM_WEr;
 initial ROM_WEr = 1'b1;
@@ -643,19 +644,19 @@ end
 // wire MCU_WRQ;
 // reg ROM_OEr;
 assign ROM_DATA[7:0] = ROM_ADDR0
-                       ?(!MCU_OVR ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                  : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                       ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
+                                        : (!ROM_WE ? ROM_DOUTr : 8'bZ)
                         )
                        :8'bZ;
 
 assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
-                        :(!MCU_OVR ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
-                                  : (!ROM_WE ? ROM_DOUTr : 8'bZ)
+                        :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
+                                         : (!ROM_WE ? ROM_DOUTr : 8'bZ)
                          );
                          
 // When in MCU mode, enable SRAM_WE according to MCU programming
 // else enable SRAM_WE according to state&cycle
-assign ROM_WE = !MCU_OVR
+assign ROM_WE = SD_DMA_TO_ROM
                 ?MCU_WRITE
                 :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle); /* & !MODE)
                   | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX])*/
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index 838b154..170cb39 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -31,10 +31,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
-    <file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>