diff --git a/verilog/sd2snes/clk_test.v b/verilog/sd2snes/clk_test.v
index 7783125..aabe3dd 100644
--- a/verilog/sd2snes/clk_test.v
+++ b/verilog/sd2snes/clk_test.v
@@ -39,7 +39,7 @@ always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
 wire sysclk_rising = (sysclk_sreg == 2'b01);
 
 always @(posedge clk) begin
-  if(sysclk_counter < 96000000) begin
+  if(sysclk_counter < 88000000) begin
     sysclk_counter <= sysclk_counter + 1;
     if(sysclk_rising) sysclk_value <= sysclk_value + 1;
   end else begin
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index 9b3ac7c..828e255 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -1,6 +1,5 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
-//TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.05 MHz HIGH 50 %;
 
 NET "p113_out" IOSTANDARD = LVCMOS33;
 NET "p113_out" LOC = P113;
@@ -8,7 +7,7 @@ NET "p113_out" LOC = P113;
 NET "SPI_SCK" LOC = P71;
 NET "SPI_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
 NET "SPI_SCK" TNM_NET = "SPI_SCK";
-TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 48.1MHz HIGH 50 %;
+TIMESPEC TS_SPI_SCK = PERIOD "SPI_SCK" 88.2MHz HIGH 50 %;
 
 NET "SPI_SCK" IOSTANDARD = LVCMOS33;
 NET "SPI_SCK" DRIVE = 8;
diff --git a/verilog/sd2snes/rtc.v b/verilog/sd2snes/rtc.v
index e643d65..300c11c 100644
--- a/verilog/sd2snes/rtc.v
+++ b/verilog/sd2snes/rtc.v
@@ -42,7 +42,7 @@ reg [31:0] tick_cnt;
 
 always @(posedge clkin) begin
   tick_cnt <= tick_cnt + 1;
-  if((tick_cnt == 24000000) || pgm_we_rising) tick_cnt <= 0;
+  if((tick_cnt == 22000000) || pgm_we_rising) tick_cnt <= 0;
 end
 
 assign rtc_data = rtc_data_out_r;
diff --git a/verilog/sd2sneslite/main.ucf b/verilog/sd2sneslite/main.ucf
index 3ccab02..4478d58 100644
--- a/verilog/sd2sneslite/main.ucf
+++ b/verilog/sd2sneslite/main.ucf
@@ -1,5 +1,5 @@
 NET "CLKIN" TNM_NET = "CLKIN";
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 24.05 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.1 MHz HIGH 50 %;
 //TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.5 MHz HIGH 50 %;
 
 NET "p113_out" IOSTANDARD = LVCMOS33;