diff --git a/src/filetypes.c b/src/filetypes.c
index d1499b0..5a6a883 100644
--- a/src/filetypes.c
+++ b/src/filetypes.c
@@ -163,13 +163,13 @@ uint16_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) {
 								uint16_t pathlen = strlen(path);
 								switch(type) {
 									case TYPE_SMC:
-										file_open_by_filinfo(&fno);
-										if(file_res){
-											dprintf("ZOMG NOOOO %d\n", file_res);
-											_delay_ms(30);
-										}
-										smc_id(&romprops);
-										file_close();
+// XXX										file_open_by_filinfo(&fno);
+// XXX										if(file_res){
+// XXX											dprintf("ZOMG NOOOO %d\n", file_res);
+// XXX											_delay_ms(30);
+// XXX										}
+// XXX										smc_id(&romprops);
+// XXX										file_close();
 		//								_delay_ms(30);
 										// write element pointer to current dir structure
 //										dprintf("d=%d Saving %lX to Address %lX  [file]\n", depth, db_tgt, dir_tgt);
diff --git a/src/main.c b/src/main.c
index dc34cee..954ea2d 100644
--- a/src/main.c
+++ b/src/main.c
@@ -278,6 +278,8 @@ restart:
 	uart_puts_P(PSTR("SNES GO!\r\n"));
 	snes_reset(0);
 
+
+
 	uint8_t cmd = 0;
 
 	while(!sram_reliable());
@@ -316,6 +318,7 @@ restart:
 	cmd=0;
 	uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
 	uint16_t reset_count=0;
+// /* XXX */	writetest();
 	while(fpga_test() == FPGA_TEST_TOKEN) {
 		snes_reset_now=get_snes_reset();
 		if(snes_reset_now) {
diff --git a/verilog/sd2snes/avr_cmd.v b/verilog/sd2snes/avr_cmd.v
index f5c087c..58aad60 100644
--- a/verilog/sd2snes/avr_cmd.v
+++ b/verilog/sd2snes/avr_cmd.v
@@ -140,7 +140,7 @@ end
 
 // r/w pulse
 always @(posedge clk) begin
-   if ((spi_bit_cnt == 3'h1) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1))
+   if ((spi_bit_cnt == 3'h1 || spi_bit_cnt == 3'h2 || spi_bit_cnt == 3'h3) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1))
       AVR_WRITE_BUF <= 1'b0;
    else
       AVR_WRITE_BUF <= 1'b1;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 56f317d..3815264 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -319,31 +319,35 @@ initial begin
    SNES_WRITE_CYCLE = 1'b1;
    AVR_READ_CYCLE = 1'b1;
    AVR_WRITE_CYCLE = 1'b1;
-   MODE_ARRAY = 13'b0000000111111;
+   MODE_ARRAY = 13'b0_000000_111111;
    
-   SRAM_WE_ARRAY[2'b00] = 13'b1000000000000;
-   SRAM_WE_ARRAY[2'b01] = 13'b1000000111111;
-   SRAM_WE_ARRAY[2'b10] = 13'b1111111000000;
-   SRAM_WE_ARRAY[2'b11] = 13'b1111111111111;
+   SRAM_WE_ARRAY[2'b00] = 13'b1_000000_000000;
+   SRAM_WE_ARRAY[2'b01] = 13'b1_000000_111111;
+   SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000;
+   SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111;
 
-   SRAM_OE_ARRAY[2'b00] = 13'b1111111111111;
-   SRAM_OE_ARRAY[2'b01] = 13'b1111111000000;
-   SRAM_OE_ARRAY[2'b10] = 13'b0000000111111;
-   SRAM_OE_ARRAY[2'b11] = 13'b0000000000000;
+   SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111;
+   SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000;
+   SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111;
+   SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000;
    
-   SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0001000000000;  // SNES write
+   SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000;  // SNES write
    /* 13'b0001000000000 */
-   SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000;  // SNES read
+   SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;  // SNES read
    
-   AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000;  // AVR write
-   AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000;  // AVR read
+   AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111;  // AVR write
+//   AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000;  // AVR write
+
+   AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;  // AVR read
    
-   SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0000000000000;  // SNES write
-   SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0000100000000;  // SNES read
+   SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000;  // SNES write
+   SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000010_000000;  // SNES read
    /* 13'b0000100000000; */
    
-   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0000000000000;  // AVR write
-   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001;  // AVR read
+   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0_000000_000000;  // AVR write
+   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0_000000_000001;  // AVR read
+//   SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001;  // AVR read
+
 end 
 
 // falling edge of SNES /RD or /WR marks the beginning of a new cycle
@@ -357,11 +361,11 @@ always @(posedge CLK2) begin
 end
 
 always @(posedge CLK2) begin
+       AVR_READ_CYCLE <= AVR_READ;
+       AVR_WRITE_CYCLE <= AVR_WRITE;
        if (SNES_RW_start) begin
            SNES_READ_CYCLE <= SNES_READ;
            SNES_WRITE_CYCLE <= SNES_WRITE;
-           AVR_READ_CYCLE <= AVR_READ;
-           AVR_WRITE_CYCLE <= AVR_WRITE;
            STATE <= STATE_0;
            STATEIDX <= 11;
        end else begin
@@ -472,6 +476,9 @@ assign SRAM_OE = !AVR_ENA ? AVR_READ
 assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
 assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
 
+//assign SRAM_BHE = SRAM_ADDR0;
+//assign SRAM_BLE = ~SRAM_ADDR0;
+
 // dumb version
 //assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
 //assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;