memory access bugfix (broke resetting after MSU1 usage)
This commit is contained in:
ikari
parent
d803252866
commit
a701dfbe2e
@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes
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# List C source files here. (C dependencies are automatically generated.)
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SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c
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SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c msu1.c
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# List Assembler source files here.
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17
src/cli.c
17
src/cli.c
@ -57,8 +57,8 @@ static char *curchar;
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/* Word lists */
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static char command_words[] =
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"cd\0reset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0put\0d4\0vmode\0mapper\0";
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enum { CMD_CD = 0, CMD_RESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_PUT, CMD_D4, CMD_VMODE, CMD_MAPPER };
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"cd\0reset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0d4\0vmode\0mapper\0";
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enum { CMD_CD = 0, CMD_RESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_D4, CMD_VMODE, CMD_MAPPER };
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/* ------------------------------------------------------------------------- */
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/* Parse functions */
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@ -151,7 +151,7 @@ static int8_t parse_wordlist(char *wordlist) {
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cur++;
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c = *ptr;
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} while (c != 0);
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if (matched) {
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char *tmp = curchar;
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@ -296,6 +296,13 @@ static void cmd_loadrom(void) {
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snes_reset(0);
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}
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static void cmd_saveraw(void) {
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uint32_t address = parse_unsigned(0,16777216);
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uint32_t length = parse_unsigned(0,16777216);
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set_mcu_ovr(0);
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save_sram((uint8_t*)curchar, length, address);
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}
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static void cmd_d4(void) {
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int32_t hz;
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@ -451,6 +458,10 @@ void cli_loop(void) {
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cmd_loadrom();
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break;
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case CMD_SAVERAW:
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cmd_saveraw();
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break;
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case CMD_D4:
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cmd_d4();
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break;
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@ -3,6 +3,7 @@
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// #define DEBUG_SD
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// #define DEBUG_IRQ
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#define DEBUG_MSU1
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#define VER "0.0.1(NSFW)"
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#define IN_AHBRAM __attribute__ ((section(".ahbram")))
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@ -28,7 +29,7 @@
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#define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */
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#define CONFIG_SD_BLOCKTRANSFER 1
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#define CONFIG_SD_AUTO_RETRIES 10
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// #define SD_CHANGE_VECT
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// #define SD_CHANGE_VECT
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// #define CONFIG_SD_DATACRC 1
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@ -27,7 +27,7 @@
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SPI commands
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cmd param function
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cmd param function
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=============================================
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0t bbhhll set address to 0xbbhhll
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t = target
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@ -50,12 +50,15 @@
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60 sssseeee set SD DMA partial transfer start+end
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ssss = start offset (msb first)
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eeee = end offset (msb first)
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80 - read with increment (RAM only)
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81 - read w/o increment (RAM only)
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90 {xx}* write xx with increment (RAM only)
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91 {xx}* write xx w/o increment (RAM only)
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8p - read (RAM only)
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p: 0 = no increment after read
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1 = increment after read
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9p {xx}* write xx
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p: tt-i
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tt = target (see above)
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i = increment (see above)
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E0 ssrr set MSU-1 status register (=FPGA status byte 2)
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ss = bits to set in status register (1=set)
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@ -64,17 +67,17 @@
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E1 - pause DAC
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E2 - resume/play DAC
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E3 - reset DAC playback pointer (0)
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E4 - reset MSU read pointer (0)
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E4 hhll set MSU read pointer
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F0 - receive test token (to see if FPGA is alive)
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F1 - receive status
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F1 - receive status (2 bytes)
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F2 - get MSU data address (32bit, MSB first)
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F3 - get MSU audio track no. (16bit, MSB first)
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F4 - get MSU volume (8bit)
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FE - get SNES master clock frequency (32bit, MSB first)
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FF {xx]* echo (returns the sent data in the next byte)
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FF {xx}* echo (returns the sent data in the next byte)
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*/
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#include <arm/NXP/LPC17xx/LPC17xx.h>
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610
src/main.c
610
src/main.c
@ -24,6 +24,7 @@
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#include "sdnative.h"
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#include "crc.h"
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#include "smc.h"
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#include "msu1.h"
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#define EMC0TOGGLE (3<<4)
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#define MR0R (1<<1)
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@ -68,7 +69,6 @@ int main(void) {
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LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */
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led_pwm();
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sdn_init();
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fpga_spi_init();
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printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
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file_init();
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cic_init(0);
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@ -81,415 +81,219 @@ led_pwm();
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LPC_TIM3->TCR=1;
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fpga_init();
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fpga_rompgm();
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restart:
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if(disk_state == DISK_CHANGED) {
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sdn_init();
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newcard = 1;
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}
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load_bootrle(SRAM_MENU_ADDR);
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set_saveram_mask(0x1fff);
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set_rom_mask(0x3fffff);
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set_mapper(0x7);
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set_mcu_ovr(0);
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snes_reset(0);
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delay_ms(15); /* allow CIC to settle */
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while(get_cic_state() == CIC_FAIL) {
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rdyled(0);
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readled(0);
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writeled(0);
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delay_ms(500);
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rdyled(1);
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readled(1);
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writeled(1);
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delay_ms(500);
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}
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/* some sanity checks */
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uint8_t card_go = 0;
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while(!card_go) {
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if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
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snes_bootprint(" No Card! \0");
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while(disk_status(0) & (STA_NOINIT|STA_NODISK));
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delay_ms(200);
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while(1) {
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set_mcu_ovr(1);
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if(disk_state == DISK_CHANGED) {
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sdn_init();
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newcard = 1;
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}
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file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
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if(file_status != FILE_OK) {
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snes_bootprint(" /sd2snes/menu.bin not found! \0");
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while(disk_status(0) == RES_OK);
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} else {
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card_go = 1;
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}
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file_close();
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}
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snes_bootprint(" Loading ... \0");
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if(get_cic_state() == CIC_PAIR) {
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printf("PAIR MODE ENGAGED!\n");
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cic_pair(CIC_PAL, CIC_NTSC);
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}
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rdyled(1);
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readled(0);
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writeled(0);
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/* exclusive mode */
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set_mcu_ovr(1);
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*fs_path=0;
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uint32_t saved_dir_id;
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get_db_id(&saved_dir_id);
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load_bootrle(SRAM_MENU_ADDR);
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set_saveram_mask(0x1fff);
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set_rom_mask(0x3fffff);
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set_mapper(0x7);
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set_mcu_ovr(0);
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snes_reset(0);
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delay_ms(15); /* allow CIC to settle */
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uint32_t mem_dir_id = sram_readlong(SRAM_DIRID);
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uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
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printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id);
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if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard)) {
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newcard = 0;
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/* generate fs footprint (interesting files only) */
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uint32_t curr_dir_id = scan_dir(fs_path, 0, 0);
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printf("curr dir id = %lx\n", curr_dir_id);
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/* files changed or no database found? */
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if((get_db_id(&saved_dir_id) != FR_OK)
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|| saved_dir_id != curr_dir_id) {
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/* rebuild database */
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printf("saved dir id = %lx\n", saved_dir_id);
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printf("rebuilding database...");
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snes_bootprint(" rebuilding database ... \0");
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curr_dir_id = scan_dir(fs_path, 1, 0);
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sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
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uint32_t endaddr, direndaddr;
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sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
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sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
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printf("%lx %lx\n", endaddr, direndaddr);
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printf("sorting database...");
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snes_bootprint(" sorting database ... \0");
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sort_all_dir(direndaddr);
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printf("done\n");
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snes_bootprint(" saving database ... \0");
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save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
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save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
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printf("done\n");
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} else {
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printf("saved dir id = %lx\n", saved_dir_id);
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printf("different card, consistent db, loading db...\n");
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load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
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load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
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}
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sram_writelong(curr_dir_id, SRAM_DIRID);
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sram_writelong(0x12345678, SRAM_SCRATCHPAD);
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} else {
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printf("same card, loading db...\n");
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load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
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load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
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}
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/* load menu */
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fpga_pgm((uint8_t*)"/main.bit.rle");
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uart_putc('(');
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load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR);
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/* force memory size + mapper */
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set_rom_mask(0x3fffff);
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set_mapper(0x7);
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uart_putc(')');
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uart_putcrlf();
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sram_writebyte(0, SRAM_CMD_ADDR);
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/* shared mode */
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set_mcu_ovr(0);
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printf("SNES GO!\n");
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snes_reset(1);
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delay_ms(1);
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snes_reset(0);
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uint8_t cmd = 0;
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uint32_t filesize=0;
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sram_writebyte(32, SRAM_CMD_ADDR);
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printf("test sram\n");
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while(!sram_reliable());
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printf("ok\n");
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//while(1) {
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// delay_ms(1000);
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// printf("Estimated SNES master clock: %ld Hz\n", get_snes_sysclk());
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//}
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//sram_hexdump(SRAM_DB_ADDR, 0x200);
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//sram_hexdump(SRAM_MENU_ADDR, 0x400);
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while(!cmd) {
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cmd=menu_main_loop();
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// cmd = 1;
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printf("cmd: %d\n", cmd);
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sleep_ms(50);
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uart_putc('-');
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switch(cmd) {
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case SNES_CMD_LOADROM:
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get_selected_name(file_lfn);
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set_mcu_ovr(1);
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// strcpy((char*)file_lfn, "/mon.smc");
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printf("Selected name: %s\n", file_lfn);
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filesize = load_rom(file_lfn, SRAM_ROM_ADDR);
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if(romprops.ramsize_bytes) {
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strcpy(strrchr((char*)file_lfn, (int)'.'), ".srm");
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printf("SRM file: %s\n", file_lfn);
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load_sram(file_lfn, SRAM_SAVE_ADDR);
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} else {
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printf("No SRAM\n");
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}
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set_mcu_ovr(0);
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snes_reset(1);
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delay_ms(10);
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snes_reset(0);
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break;
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case SNES_CMD_SETRTC:
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cmd=0; /* stay in loop */
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break;
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default:
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printf("unknown cmd: %d\n", cmd);
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cmd=0; /* unknown cmd: stay in loop */
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break;
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}
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}
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printf("cmd was %x, going to snes main loop\n", cmd);
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/* MSU1 STUFF, GET ME OUTTA HERE */
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FIL durr;
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// open MSU file
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strcpy((char*)file_buf, (char*)file_lfn);
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strcpy(strrchr((char*)file_buf, (int)'.'), ".msu");
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printf("MSU datafile: %s\n", file_buf);
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printf("f_open result: %d\n", f_open(&durr, (const TCHAR*)file_buf, FA_READ));
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UINT bytes_read = 1024;
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UINT bytes_read2 = 1;
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set_dac_vol(0x00);
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spi_set_speed(SSP_CLK_DIVISOR_FAST);
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while(fpga_status() & 0x4000);
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uint16_t fpga_status_prev = fpga_status();
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uint16_t fpga_status_now = fpga_status();
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uint16_t dac_addr = 0;
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uint16_t msu_addr = 0;
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uint8_t msu_repeat = 0;
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uint16_t msu_track = 0;
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uint32_t msu_offset = 0;
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uint32_t msu_page1_start = 0x0000;
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uint32_t msu_page2_start = 0x2000;
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uint32_t msu_page_size = 0x2000;
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set_msu_addr(0x0);
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msu_reset(0x0);
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ff_sd_offload=1;
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sd_offload_tgt=2;
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f_lseek(&durr, 0L);
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ff_sd_offload=1;
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sd_offload_tgt=2;
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f_read(&durr, file_buf, 16384, &bytes_read2);
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set_dac_addr(dac_addr);
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dac_pause();
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dac_reset();
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/* audio_start, data_start, volume_start, audio_ctrl[1:0], ctrl_start */
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while(1){
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fpga_status_now = fpga_status();
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if(fpga_status_now & 0x0020) {
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char suffix[11];
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/* get trackno */
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msu_track = get_msu_track();
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printf("Audio requested! Track=%d\n", msu_track);
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/* open file */
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f_close(&file_handle);
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snprintf(suffix, sizeof(suffix), "-%d.wav", msu_track);
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strcpy((char*)file_buf, (char*)file_lfn);
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strcpy(strrchr((char*)file_buf, (int)'.'), suffix);
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printf("filename: %s\n", file_buf);
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f_open(&file_handle, (const TCHAR*)file_buf, FA_READ);
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ff_sd_offload=1;
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sd_offload_tgt=1;
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f_lseek(&file_handle, 44L);
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set_dac_addr(0);
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dac_pause();
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dac_reset();
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ff_sd_offload=1;
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sd_offload_tgt=1;
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f_read(&file_handle, file_buf, 2048, &bytes_read);
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/* clear busy bit */
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set_msu_status(0x00, 0x20); /* set no bits, reset bit 5 */
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}
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if(fpga_status_now & 0x0010) {
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/* get address */
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msu_offset=get_msu_offset();
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printf("Data requested! Offset=%08lx page1=%08lx page2=%08lx\n", msu_offset, msu_page1_start, msu_page2_start);
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if( ((msu_offset < msu_page1_start)
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|| (msu_offset >= msu_page1_start + msu_page_size))
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&& ((msu_offset < msu_page2_start)
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|| (msu_offset >= msu_page2_start + msu_page_size))) {
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printf("offset %08lx out of range (%08lx-%08lx, %08lx-%08lx), reload\n", msu_offset, msu_page1_start,
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msu_page1_start+msu_page_size-1, msu_page2_start, msu_page2_start+msu_page_size-1);
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/* cache miss */
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/* fill buffer */
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set_msu_addr(0x0);
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sd_offload_tgt=2;
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ff_sd_offload=1;
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printf("seek to %08lx, res = %d\n", msu_offset, f_lseek(&durr, msu_offset));
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sd_offload_tgt=2;
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ff_sd_offload=1;
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printf("read res = %d\n", f_read(&durr, file_buf, 16384, &bytes_read2));
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printf("read %d bytes\n", bytes_read2);
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msu_reset(0x0);
|
||||
msu_page1_start = msu_offset;
|
||||
msu_page2_start = msu_offset + msu_page_size;
|
||||
} else {
|
||||
if (msu_offset >= msu_page1_start && msu_offset <= msu_page1_start + msu_page_size) {
|
||||
msu_reset(0x0000 + msu_offset - msu_page1_start);
|
||||
printf("inside page1, new offset: %08lx\n", 0x0000 + msu_offset-msu_page1_start);
|
||||
if(!(msu_page2_start == msu_page1_start + msu_page_size)) {
|
||||
set_msu_addr(0x2000);
|
||||
sd_offload_tgt=2;
|
||||
ff_sd_offload=1;
|
||||
f_read(&durr, file_buf, 8192, &bytes_read2);
|
||||
printf("next page dirty (was: %08lx), loaded page2 (start now: ", msu_page2_start);
|
||||
msu_page2_start = msu_page1_start + msu_page_size;
|
||||
printf("%08lx)\n", msu_page2_start);
|
||||
}
|
||||
} else if (msu_offset >= msu_page2_start && msu_offset <= msu_page2_start + msu_page_size) {
|
||||
printf("inside page2, new offset: %08lx\n", 0x2000 + msu_offset-msu_page2_start);
|
||||
msu_reset(0x2000 + msu_offset - msu_page2_start);
|
||||
if(!(msu_page1_start == msu_page2_start + msu_page_size)) {
|
||||
set_msu_addr(0x0);
|
||||
sd_offload_tgt=2;
|
||||
ff_sd_offload=1;
|
||||
f_read(&durr, file_buf, 8192, &bytes_read2);
|
||||
printf("next page dirty (was: %08lx), loaded page1 (start now: ", msu_page1_start);
|
||||
msu_page1_start = msu_page2_start + msu_page_size;
|
||||
printf("%08lx)\n", msu_page1_start);
|
||||
}
|
||||
} else printf("!!!WATWATWAT!!!\n");
|
||||
}
|
||||
/* clear busy bit */
|
||||
set_msu_status(0x00, 0x10);
|
||||
}
|
||||
|
||||
if(fpga_status_now & 0x0001) {
|
||||
if(fpga_status_now & 0x0004) {
|
||||
msu_repeat = 1;
|
||||
set_msu_status(0x04, 0x01); /* set bit 2, reset bit 0 */
|
||||
printf("Repeat set!\n");
|
||||
} else {
|
||||
msu_repeat = 0;
|
||||
set_msu_status(0x00, 0x05); /* set no bits, reset bit 0+2 */
|
||||
printf("Repeat clear!\n");
|
||||
}
|
||||
|
||||
if(fpga_status_now & 0x0002) {
|
||||
printf("PLAY!\n");
|
||||
set_msu_status(0x02, 0x01); /* set bit 0, reset bit 1 */
|
||||
dac_play();
|
||||
} else {
|
||||
printf("PAUSE!\n");
|
||||
set_msu_status(0x00, 0x03); /* set no bits, reset bit 1+0 */
|
||||
dac_pause();
|
||||
}
|
||||
}
|
||||
|
||||
/* Audio buffer refill */
|
||||
if((fpga_status_now & 0x4000) != (fpga_status_prev & 0x4000)) {
|
||||
if(fpga_status_now & 0x4000) {
|
||||
dac_addr = 0x0;
|
||||
} else {
|
||||
dac_addr = 0x400;
|
||||
}
|
||||
set_dac_addr(dac_addr);
|
||||
sd_offload_tgt=1;
|
||||
ff_sd_offload=1;
|
||||
f_read(&file_handle, file_buf, 1024, &bytes_read);
|
||||
}
|
||||
|
||||
/* Data buffer refill */
|
||||
if((fpga_status_now & 0x2000) != (fpga_status_prev & 0x2000)) {
|
||||
printf("data\n");
|
||||
if(fpga_status_now & 0x2000) {
|
||||
msu_addr = 0x0;
|
||||
msu_page1_start = msu_page2_start + msu_page_size;
|
||||
} else {
|
||||
msu_addr = 0x2000;
|
||||
msu_page2_start = msu_page1_start + msu_page_size;
|
||||
}
|
||||
set_msu_addr(msu_addr);
|
||||
sd_offload_tgt=2;
|
||||
ff_sd_offload=1;
|
||||
printf("data buffer refilled. res=%d page1=%08lx page2=%08lx\n", f_read(&durr, file_buf, 8192, &bytes_read2), msu_page1_start, msu_page2_start);
|
||||
}
|
||||
fpga_status_prev = fpga_status_now;
|
||||
|
||||
/* handle loop / end */
|
||||
if(bytes_read<1024) {
|
||||
ff_sd_offload=0;
|
||||
sd_offload=0;
|
||||
if(msu_repeat) {
|
||||
printf("loop\n");
|
||||
ff_sd_offload=1;
|
||||
sd_offload_tgt=1;
|
||||
f_lseek(&file_handle, 44L);
|
||||
ff_sd_offload=1;
|
||||
sd_offload_tgt=1;
|
||||
f_read(&file_handle, file_buf, 1024 - bytes_read, &bytes_read);
|
||||
} else {
|
||||
set_msu_status(0x00, 0x02); /* clear play bit */
|
||||
}
|
||||
bytes_read=1024;
|
||||
}
|
||||
}
|
||||
|
||||
/* END OF MSU1 STUFF */
|
||||
|
||||
cmd=0;
|
||||
uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
|
||||
uint16_t reset_count=0;
|
||||
while(fpga_test() == FPGA_TEST_TOKEN) {
|
||||
cli_entrycheck();
|
||||
sleep_ms(250);
|
||||
sram_reliable();
|
||||
printf("%s ", get_cic_statename(get_cic_state()));
|
||||
snes_reset_now=get_snes_reset();
|
||||
if(snes_reset_now) {
|
||||
if(!snes_reset_prev) {
|
||||
printf("RESET BUTTON DOWN\n");
|
||||
snes_reset_state=1;
|
||||
reset_count=0;
|
||||
}
|
||||
} else {
|
||||
if(snes_reset_prev) {
|
||||
printf("RESET BUTTON UP\n");
|
||||
snes_reset_state=0;
|
||||
}
|
||||
}
|
||||
if(snes_reset_state) {
|
||||
reset_count++;
|
||||
} else {
|
||||
sram_reliable();
|
||||
snes_main_loop();
|
||||
}
|
||||
if(reset_count>4) {
|
||||
reset_count=0;
|
||||
set_mcu_ovr(1);
|
||||
snes_reset(1);
|
||||
delay_ms(1);
|
||||
if(romprops.ramsize_bytes && fpga_test() == FPGA_TEST_TOKEN) {
|
||||
writeled(1);
|
||||
save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
|
||||
writeled(0);
|
||||
}
|
||||
while(get_cic_state() == CIC_FAIL) {
|
||||
rdyled(0);
|
||||
readled(0);
|
||||
writeled(0);
|
||||
delay_ms(500);
|
||||
rdyled(1);
|
||||
readled(1);
|
||||
writeled(1);
|
||||
snes_reset(0);
|
||||
while(get_snes_reset());
|
||||
snes_reset(1);
|
||||
delay_ms(200);
|
||||
goto restart;
|
||||
delay_ms(500);
|
||||
}
|
||||
snes_reset_prev = snes_reset_now;
|
||||
/* some sanity checks */
|
||||
uint8_t card_go = 0;
|
||||
while(!card_go) {
|
||||
if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
|
||||
snes_bootprint(" No Card! \0");
|
||||
while(disk_status(0) & (STA_NOINIT|STA_NODISK));
|
||||
delay_ms(200);
|
||||
}
|
||||
file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
|
||||
if(file_status != FILE_OK) {
|
||||
snes_bootprint(" /sd2snes/menu.bin not found! \0");
|
||||
while(disk_status(0) == RES_OK);
|
||||
} else {
|
||||
card_go = 1;
|
||||
}
|
||||
file_close();
|
||||
}
|
||||
snes_bootprint(" Loading ... \0");
|
||||
if(get_cic_state() == CIC_PAIR) {
|
||||
printf("PAIR MODE ENGAGED!\n");
|
||||
cic_pair(CIC_PAL, CIC_NTSC);
|
||||
}
|
||||
rdyled(1);
|
||||
readled(0);
|
||||
writeled(0);
|
||||
/* exclusive mode */
|
||||
set_mcu_ovr(1);
|
||||
|
||||
*fs_path=0;
|
||||
uint32_t saved_dir_id;
|
||||
get_db_id(&saved_dir_id);
|
||||
|
||||
uint32_t mem_dir_id = sram_readlong(SRAM_DIRID);
|
||||
uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
|
||||
printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id);
|
||||
if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard)) {
|
||||
newcard = 0;
|
||||
/* generate fs footprint (interesting files only) */
|
||||
uint32_t curr_dir_id = scan_dir(fs_path, 0, 0);
|
||||
printf("curr dir id = %lx\n", curr_dir_id);
|
||||
/* files changed or no database found? */
|
||||
if((get_db_id(&saved_dir_id) != FR_OK)
|
||||
|| saved_dir_id != curr_dir_id) {
|
||||
/* rebuild database */
|
||||
printf("saved dir id = %lx\n", saved_dir_id);
|
||||
printf("rebuilding database...");
|
||||
snes_bootprint(" rebuilding database ... \0");
|
||||
curr_dir_id = scan_dir(fs_path, 1, 0);
|
||||
sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
|
||||
uint32_t endaddr, direndaddr;
|
||||
sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
|
||||
sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
|
||||
printf("%lx %lx\n", endaddr, direndaddr);
|
||||
printf("sorting database...");
|
||||
snes_bootprint(" sorting database ... \0");
|
||||
sort_all_dir(direndaddr);
|
||||
printf("done\n");
|
||||
snes_bootprint(" saving database ... \0");
|
||||
save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
|
||||
save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
|
||||
printf("done\n");
|
||||
} else {
|
||||
printf("saved dir id = %lx\n", saved_dir_id);
|
||||
printf("different card, consistent db, loading db...\n");
|
||||
load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
|
||||
load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
|
||||
}
|
||||
sram_writelong(curr_dir_id, SRAM_DIRID);
|
||||
sram_writelong(0x12345678, SRAM_SCRATCHPAD);
|
||||
} else {
|
||||
printf("same card, loading db...\n");
|
||||
load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
|
||||
load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
|
||||
}
|
||||
/* load menu */
|
||||
fpga_pgm((uint8_t*)"/main.bit.rle");
|
||||
|
||||
uart_putc('(');
|
||||
load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR);
|
||||
/* force memory size + mapper */
|
||||
set_rom_mask(0x3fffff);
|
||||
set_mapper(0x7);
|
||||
uart_putc(')');
|
||||
uart_putcrlf();
|
||||
|
||||
sram_writebyte(0, SRAM_CMD_ADDR);
|
||||
|
||||
/* shared mode */
|
||||
set_mcu_ovr(0);
|
||||
|
||||
printf("SNES GO!\n");
|
||||
snes_reset(1);
|
||||
delay_ms(1);
|
||||
snes_reset(0);
|
||||
|
||||
uint8_t cmd = 0;
|
||||
uint32_t filesize=0;
|
||||
sram_writebyte(32, SRAM_CMD_ADDR);
|
||||
printf("test sram\n");
|
||||
while(!sram_reliable());
|
||||
printf("ok\n");
|
||||
//while(1) {
|
||||
// delay_ms(1000);
|
||||
// printf("Estimated SNES master clock: %ld Hz\n", get_snes_sysclk());
|
||||
//}
|
||||
//sram_hexdump(SRAM_DB_ADDR, 0x200);
|
||||
//sram_hexdump(SRAM_MENU_ADDR, 0x400);
|
||||
while(!cmd) {
|
||||
cmd=menu_main_loop();
|
||||
// cmd = 1;
|
||||
printf("cmd: %d\n", cmd);
|
||||
sleep_ms(50);
|
||||
uart_putc('-');
|
||||
switch(cmd) {
|
||||
case SNES_CMD_LOADROM:
|
||||
get_selected_name(file_lfn);
|
||||
set_mcu_ovr(1);
|
||||
// strcpy((char*)file_lfn, "/msu1/msu1vid_ikari_01/msu1vid.sfc");
|
||||
printf("Selected name: %s\n", file_lfn);
|
||||
filesize = load_rom(file_lfn, SRAM_ROM_ADDR);
|
||||
if(romprops.ramsize_bytes) {
|
||||
strcpy(strrchr((char*)file_lfn, (int)'.'), ".srm");
|
||||
printf("SRM file: %s\n", file_lfn);
|
||||
load_sram(file_lfn, SRAM_SAVE_ADDR);
|
||||
} else {
|
||||
printf("No SRAM\n");
|
||||
}
|
||||
set_mcu_ovr(0);
|
||||
snes_reset(1);
|
||||
delay_ms(10);
|
||||
snes_reset(0);
|
||||
break;
|
||||
case SNES_CMD_SETRTC:
|
||||
cmd=0; /* stay in loop */
|
||||
break;
|
||||
default:
|
||||
printf("unknown cmd: %d\n", cmd);
|
||||
cmd=0; /* unknown cmd: stay in loop */
|
||||
break;
|
||||
}
|
||||
}
|
||||
printf("cmd was %x, going to snes main loop\n", cmd);
|
||||
|
||||
/* always try MSU1 for now */
|
||||
if(msu1_entrycheck_and_loop()) {
|
||||
prepare_reset();
|
||||
continue;
|
||||
}
|
||||
|
||||
cmd=0;
|
||||
uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
|
||||
uint16_t reset_count=0;
|
||||
while(fpga_test() == FPGA_TEST_TOKEN) {
|
||||
cli_entrycheck();
|
||||
sleep_ms(250);
|
||||
sram_reliable();
|
||||
printf("%s ", get_cic_statename(get_cic_state()));
|
||||
snes_reset_now=get_snes_reset();
|
||||
if(snes_reset_now) {
|
||||
if(!snes_reset_prev) {
|
||||
printf("RESET BUTTON DOWN\n");
|
||||
snes_reset_state=1;
|
||||
reset_count=0;
|
||||
}
|
||||
} else {
|
||||
if(snes_reset_prev) {
|
||||
printf("RESET BUTTON UP\n");
|
||||
snes_reset_state=0;
|
||||
}
|
||||
}
|
||||
if(snes_reset_state) {
|
||||
reset_count++;
|
||||
} else {
|
||||
sram_reliable();
|
||||
snes_main_loop();
|
||||
}
|
||||
if(reset_count>4) {
|
||||
reset_count=0;
|
||||
prepare_reset();
|
||||
break;
|
||||
}
|
||||
snes_reset_prev = snes_reset_now;
|
||||
}
|
||||
/* fpga test fail: panic */
|
||||
if(fpga_test() != FPGA_TEST_TOKEN){
|
||||
led_panic();
|
||||
}
|
||||
/* else reset */
|
||||
}
|
||||
/* fpga test fail: panic */
|
||||
led_panic();
|
||||
}
|
||||
|
||||
|
||||
34
src/memory.c
34
src/memory.c
@ -59,7 +59,7 @@ void sram_hexdump(uint32_t addr, uint32_t len) {
|
||||
void sram_writebyte(uint8_t val, uint32_t addr) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91); /* WRITE */
|
||||
FPGA_TX_BYTE(0x98); /* WRITE */
|
||||
FPGA_TX_BYTE(val);
|
||||
FPGA_TX_BYTE(0x00); /* dummy */
|
||||
FPGA_DESELECT();
|
||||
@ -68,7 +68,7 @@ void sram_writebyte(uint8_t val, uint32_t addr) {
|
||||
uint8_t sram_readbyte(uint32_t addr) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81); /* READ */
|
||||
FPGA_TX_BYTE(0x88); /* READ */
|
||||
FPGA_TX_BYTE(0x00); /* dummy */
|
||||
uint8_t val = FPGA_TXRX_BYTE(0x00);
|
||||
FPGA_DESELECT();
|
||||
@ -78,7 +78,7 @@ uint8_t sram_readbyte(uint32_t addr) {
|
||||
void sram_writeshort(uint16_t val, uint32_t addr) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91); /* WRITE */
|
||||
FPGA_TX_BYTE(0x98); /* WRITE */
|
||||
FPGA_TX_BYTE(val&0xff);
|
||||
FPGA_TX_BYTE((val>>8)&0xff);
|
||||
FPGA_TX_BYTE(0x00); /* dummy */
|
||||
@ -88,7 +88,7 @@ void sram_writeshort(uint16_t val, uint32_t addr) {
|
||||
void sram_writelong(uint32_t val, uint32_t addr) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91); /* WRITE */
|
||||
FPGA_TX_BYTE(0x98); /* WRITE */
|
||||
FPGA_TX_BYTE(val&0xff);
|
||||
FPGA_TX_BYTE((val>>8)&0xff);
|
||||
FPGA_TX_BYTE((val>>16)&0xff);
|
||||
@ -100,7 +100,7 @@ void sram_writelong(uint32_t val, uint32_t addr) {
|
||||
uint16_t sram_readshort(uint32_t addr) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81);
|
||||
FPGA_TX_BYTE(0x88);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
uint32_t val = FPGA_TXRX_BYTE(0x00);
|
||||
val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8);
|
||||
@ -111,7 +111,7 @@ uint16_t sram_readshort(uint32_t addr) {
|
||||
uint32_t sram_readlong(uint32_t addr) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81);
|
||||
FPGA_TX_BYTE(0x88);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
uint32_t val = FPGA_TXRX_BYTE(0x00);
|
||||
val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8);
|
||||
@ -124,7 +124,7 @@ uint32_t sram_readlong(uint32_t addr) {
|
||||
void sram_readlongblock(uint32_t* buf, uint32_t addr, uint16_t count) {
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81);
|
||||
FPGA_TX_BYTE(0x88);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
uint16_t i=0;
|
||||
while(i<count) {
|
||||
@ -142,7 +142,7 @@ void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
|
||||
uint8_t* tgt = buf;
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81); /* READ */
|
||||
FPGA_TX_BYTE(0x88); /* READ */
|
||||
FPGA_TX_BYTE(0x00); /* dummy */
|
||||
while(count--) {
|
||||
*(tgt++) = FPGA_TXRX_BYTE(0x00);
|
||||
@ -155,7 +155,7 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
|
||||
uint8_t* src = buf;
|
||||
set_mcu_addr(addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91); /* WRITE */
|
||||
FPGA_TX_BYTE(0x98); /* WRITE */
|
||||
while(count--) {
|
||||
FPGA_TX_BYTE(*src++);
|
||||
}
|
||||
@ -212,7 +212,7 @@ ticks_total=getticks()-ticksstart;
|
||||
printf("%u ticks in read, %u ticks in tx, %u ticks total\n", ticks_read, ticks_tx, ticks_total);
|
||||
uint32_t rammask;
|
||||
uint32_t rommask;
|
||||
|
||||
|
||||
if(filesize > (romprops.romsize_bytes + romprops.offset)) {
|
||||
romprops.romsize_bytes <<= 1;
|
||||
}
|
||||
@ -241,7 +241,7 @@ uint32_t load_sram(uint8_t* filename, uint32_t base_addr) {
|
||||
bytes_read = file_read();
|
||||
if (file_res || !bytes_read) break;
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91);
|
||||
FPGA_TX_BYTE(0x98);
|
||||
for(int j=0; j<bytes_read; j++) {
|
||||
FPGA_TX_BYTE(file_buf[j]);
|
||||
}
|
||||
@ -260,7 +260,7 @@ uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr) {
|
||||
filesize = file_handle.fsize;
|
||||
if(file_res) return 0;
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91);
|
||||
FPGA_TX_BYTE(0x98);
|
||||
for(;;) {
|
||||
data = rle_file_getc();
|
||||
if (file_res || file_status) break;
|
||||
@ -277,9 +277,9 @@ uint32_t load_bootrle(uint32_t base_addr) {
|
||||
set_mcu_addr(base_addr);
|
||||
DWORD filesize = 0;
|
||||
rle_mem_init(bootrle, sizeof(bootrle));
|
||||
|
||||
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91);
|
||||
FPGA_TX_BYTE(0x98);
|
||||
for(;;) {
|
||||
data = rle_mem_getc();
|
||||
if(rle_state) break;
|
||||
@ -304,7 +304,7 @@ void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
|
||||
while(count<sram_size) {
|
||||
set_mcu_addr(base_addr+count);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81); /* read */
|
||||
FPGA_TX_BYTE(0x88); /* read */
|
||||
FPGA_TX_BYTE(0x00); /* dummy */
|
||||
for(int j=0; j<sizeof(file_buf); j++) {
|
||||
file_buf[j] = FPGA_TXRX_BYTE(0x00);
|
||||
@ -328,7 +328,7 @@ uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
|
||||
crc_valid=1;
|
||||
set_mcu_addr(base_addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x81);
|
||||
FPGA_TX_BYTE(0x88);
|
||||
FPGA_TX_BYTE(0x00);
|
||||
for(count=0; count<size; count++) {
|
||||
data = FPGA_TXRX_BYTE(0x00);
|
||||
@ -375,7 +375,7 @@ uint8_t sram_reliable() {
|
||||
void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val) {
|
||||
set_mcu_addr(base_addr);
|
||||
FPGA_SELECT();
|
||||
FPGA_TX_BYTE(0x91);
|
||||
FPGA_TX_BYTE(0x98);
|
||||
for(uint32_t i=0; i<len; i++) {
|
||||
FPGA_TX_BYTE(val);
|
||||
}
|
||||
|
||||
23
src/snes.c
23
src/snes.c
@ -37,16 +37,35 @@
|
||||
#include "timer.h"
|
||||
#include "cli.h"
|
||||
#include "fpga.h"
|
||||
#include "fpga_spi.h"
|
||||
|
||||
uint8_t initloop=1;
|
||||
uint32_t saveram_crc, saveram_crc_old;
|
||||
extern snes_romprops_t romprops;
|
||||
|
||||
void prepare_reset() {
|
||||
set_mcu_ovr(1);
|
||||
snes_reset(1);
|
||||
delay_ms(1);
|
||||
if(romprops.ramsize_bytes && fpga_test() == FPGA_TEST_TOKEN) {
|
||||
writeled(1);
|
||||
save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
|
||||
writeled(0);
|
||||
}
|
||||
rdyled(1);
|
||||
readled(1);
|
||||
writeled(1);
|
||||
snes_reset(0);
|
||||
while(get_snes_reset());
|
||||
snes_reset(1);
|
||||
delay_ms(200);
|
||||
}
|
||||
|
||||
void snes_init() {
|
||||
/* put reset level on reset pin */
|
||||
BITBAND(SNES_RESET_REG->FIOCLR, SNES_RESET_BIT) = 1;
|
||||
/* reset the SNES */
|
||||
snes_reset(1);
|
||||
snes_reset(1);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -106,7 +125,7 @@ void snes_main_loop() {
|
||||
diffcount=0;
|
||||
writeled(1);
|
||||
save_sram(file_lfn, romprops.ramsize_bytes, SRAM_SAVE_ADDR);
|
||||
didnotsave=0;
|
||||
didnotsave=0;
|
||||
writeled(0);
|
||||
}
|
||||
saveram_crc_old = saveram_crc;
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
|
||||
uint8_t crc_valid;
|
||||
|
||||
void prepare_reset(void);
|
||||
void snes_init(void);
|
||||
void snes_reset(int state);
|
||||
uint8_t get_snes_reset(void);
|
||||
|
||||
@ -164,6 +164,8 @@ always @(posedge clk) begin
|
||||
SD_DMA_TGTr <= cmd_data[1:0];
|
||||
SD_DMA_PARTIALr <= cmd_data[2];
|
||||
end
|
||||
4'h8: SD_DMA_TGTr <= 2'b00;
|
||||
4'h9: SD_DMA_TGTr <= cmd_data[1:0];
|
||||
// 4'hE:
|
||||
// select memory unit
|
||||
endcase
|
||||
@ -283,7 +285,7 @@ always @(posedge clk) begin
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[0]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
|
||||
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[3]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
|
||||
case (SD_DMA_TGTr)
|
||||
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
|
||||
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
|
||||
|
||||
@ -47,7 +47,7 @@ reg vol_valid;
|
||||
reg[2:0] sysclk_sreg;
|
||||
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
|
||||
|
||||
reg [16:0] interpol_count;
|
||||
reg [25:0] interpol_count;
|
||||
reg interpol_overflow;
|
||||
|
||||
always @(posedge clkin) begin
|
||||
@ -110,12 +110,12 @@ always @(posedge clkin) begin
|
||||
interpol_overflow <= 0;
|
||||
interpol_count <= 0;
|
||||
end else if(sysclk_rising) begin
|
||||
if(interpol_count > 65437) begin
|
||||
interpol_count <= interpol_count + 135 - 65573;
|
||||
if(interpol_count > 59378938) begin
|
||||
interpol_count <= interpol_count + 122500 - 59501439;
|
||||
dac_address_r <= dac_address_r + play_r;
|
||||
interpol_overflow <= 1;
|
||||
end else begin
|
||||
interpol_count <= interpol_count + 135;
|
||||
interpol_count <= interpol_count + 122500;
|
||||
interpol_overflow <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
@ -36,330 +36,27 @@
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s400" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dac_buf|dac_buf_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="dac_buf.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dac_buf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="8" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="dac_buf" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="dac_buf_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="dac_buf_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="dac_buf_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="dac_buf_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="dac_buf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2010-12-29T13:11:09" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BA4AB8EF979AA432F67FF279F092E18B" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user