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FPGA: code formatting, update synthesis configuration, timing

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This commit is contained in:
ikari 2011-06-18 02:27:56 +02:00
parent 630d75cacc
commit a8d64311c6
14 changed files with 1741 additions and 1673 deletions
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134
verilog/sd2snes/address.v
View File

@ -41,7 +41,7 @@ module address(
input [14:0] bsx_regs,
output dspx_enable,
output dspx_a0
);
);
wire [1:0] SRAM_BANK;
@ -80,34 +80,41 @@ assign IS_ROM = ( (MAPPER == 3'b000) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: 1'b0);
assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b100 || MAPPER == 3'b110 || MAPPER == 3'b111) ? (!SNES_ADDR[22]
assign IS_SAVERAM = ((MAPPER == 3'b000
|| MAPPER == 3'b010
|| MAPPER == 3'b100
|| MAPPER == 3'b110
|| MAPPER == 3'b111)
? (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
Offset 0000-7fff TODO: 0000-ffff for
small ROMs */
:(MAPPER == 3'b001 || MAPPER == 3'b101) ? (&SNES_ADDR[22:20]
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
TODO: 0000-ffff for small ROMs? */
:(MAPPER == 3'b001
|| MAPPER == 3'b101)
? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15])
/* BS-X: SRAM @ Bank 0x10-0x17
Offset 5000-5fff */
:(MAPPER == 3'b011) ? ((SNES_ADDR[23:19] == 5'b00010)
& !SNES_ADDR[15]
)
/* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
:(MAPPER == 3'b011)
? ((SNES_ADDR[23:19] == 5'b00010)
& (SNES_ADDR[15:12] == 4'b0101)
)
: 1'b0);
assign IS_WRITABLE = IS_SAVERAM | (
(MAPPER == 3'b011)
? (
(bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
assign IS_WRITABLE = IS_SAVERAM
|((MAPPER == 3'b011)
?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
|(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
|(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
|(SNES_ADDR[23:19] == 5'b01110)
|(SNES_ADDR[23:21] == 3'b001 && SNES_ADDR[15:13] == 3'b011))
|(SNES_ADDR[23:21] == 3'b001
&& SNES_ADDR[15:13] == 3'b011)
)
: 1'b0);
/* BSX regs:
@ -122,31 +129,68 @@ assign IS_WRITABLE = IS_SAVERAM | (
*/
assign SRAM_ADDR_FULL = (MODE) ? MCU_ADDR
: ((MAPPER[1:0] == 2'b00) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
:((MAPPER[1:0] == 2'b00)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER[1:0] == 2'b01) ?
(IS_SAVERAM ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
:(MAPPER == 3'b010) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
:(MAPPER == 3'b011) ?
(IS_SAVERAM ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: IS_WRITABLE ? (24'h400000 + (SNES_ADDR & 24'h0FFFFF /*7ffff*/))
:(MAPPER[1:0] == 2'b01)
?(IS_SAVERAM
? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
:(MAPPER == 3'b011)
?(IS_SAVERAM
? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: IS_WRITABLE
? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
: ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
|(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
? (24'h800000 + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & 24'h0FFFFF))
: ((bsx_regs[1] ? 24'h400000 : 24'h000000)
+ bsx_regs[2] ? ({2'b00, SNES_ADDR[21:0]} & (ROM_MASK /* >> bsx_regs[1] */))
: ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & (ROM_MASK /* >> bsx_regs[1] */))))
:(MAPPER == 3'b110) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: (SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
: ({2'b10, SNES_ADDR[23], SNES_ADDR[21:16], SNES_ADDR[14:0]})))
:(MAPPER == 3'b111) ?
(IS_SAVERAM ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) + 24'hE00000))
?(24'h800000
+ ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
& 24'h0FFFFF)
)
:((bsx_regs[1]
? 24'h400000
: 24'h000000
)
+ bsx_regs[2]
?({2'b00, SNES_ADDR[21:0]}
& (ROM_MASK /* >> bsx_regs[1] */)
)
:({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
& (ROM_MASK /* >> bsx_regs[1] */)
)
)
)
:(MAPPER == 3'b110)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
:(SNES_ADDR[15]
?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10,
SNES_ADDR[23],
SNES_ADDR[21:16],
SNES_ADDR[14:0]}
)
)
)
:(MAPPER == 3'b111)
?(IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hE00000)
)
: 24'b0);
assign ROM_ADDR = SRAM_ADDR_FULL[23:1];
@ -154,7 +198,7 @@ assign ROM_ADDR = SRAM_ADDR_FULL[23:1];
assign ROM_SEL = 1'b0; // (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
assign ROM_ADDR0 = SRAM_ADDR_FULL[0];
//488888
assign msu_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign use_bsx = (MAPPER == 3'b011);
@ -164,14 +208,16 @@ assign srtc_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h280
// or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
// DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
wire dspx_enable_w =
(MAPPER == 3'b101) ?
(ROM_MASK[20] ?
(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
(MAPPER == 3'b101)
?(ROM_MASK[20]
?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
:(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
)
:(MAPPER == 3'b100) ?
(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15] & &SNES_ADDR[14:13]/* & CS */)
:(MAPPER == 3'b100)
?(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15]
& &SNES_ADDR[14:13])
:1'b0;
assign dspx_a0 = (MAPPER == 3'b101) ? SNES_ADDR[14]
:(MAPPER == 3'b100) ? SNES_ADDR[12]
:1'b1;

17
verilog/sd2snes/bsx.v
View File

@ -34,7 +34,7 @@ module bsx(
output data_ovr,
output flash_writable,
input [59:0] rtc_data
);
);
wire [3:0] reg_addr = snes_addr[19:16]; // 00-0f:5000-5fff
wire [4:0] base_addr = snes_addr[4:0]; // 88-9f -> 08-1f
@ -46,19 +46,28 @@ reg [16:0] flash_cmd0;
reg [24:0] flash_cmd5555;
wire cart_enable = (use_bsx) && ((snes_addr[23:12] & 12'hf0f) == 12'h005);
wire base_enable = (use_bsx) && (!snes_addr[22] && (snes_addr[15:0] >= 16'h2188)
&& (snes_addr[15:0] <= 16'h219f));
wire flash_enable = (snes_addr[23:16] == 8'hc0);
wire is_flash_special_address = (flash_addr == 16'h0002
|| flash_addr == 16'h5555
|| flash_addr == 16'h2aaa
|| flash_addr == 16'h0000
|| (flash_addr >= 16'hff00 && flash_addr <= 16'hff13));
|| (flash_addr >= 16'hff00
&& flash_addr <= 16'hff13));
wire flash_ovr = (use_bsx) && (flash_enable & flash_ovr_r) && is_flash_special_address;
wire flash_ovr = (use_bsx)
&& (flash_enable & flash_ovr_r)
&& is_flash_special_address;
assign flash_writable = (use_bsx)
&& flash_enable
&& flash_we_r
&& !is_flash_special_address;
assign flash_writable = (use_bsx) && flash_enable && flash_we_r && !is_flash_special_address;
assign data_ovr = cart_enable | base_enable | flash_ovr;
reg [5:0] reg_oe_sreg;

2
verilog/sd2snes/clk_test.v
View File

@ -22,7 +22,7 @@ module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;

4
verilog/sd2snes/dac.v
View File

@ -32,7 +32,7 @@ module dac(
output lrck,
output mclk,
output DAC_STATUS
);
);
reg[8:0] dac_address_r;
wire[8:0] dac_address = dac_address_r;
@ -72,8 +72,6 @@ reg [15:0] smpshift;
reg [15:0] smpdata;
assign mclk = cnt[2]; // mclk = clk/8
//assign lrck = cnt[10]; // lrck = mclk/512
//wire sclk = cnt[5]; // sclk = lrck*32
assign lrck = cnt[8]; // lrck = mclk/128
wire sclk = cnt[3]; // sclk = lrck*32

33
verilog/sd2snes/data.v
View File

@ -47,7 +47,7 @@ module data(
input bsx_data_ovr,
input srtc_enable,
input dspx_enable
);
);
reg [7:0] SNES_IN_MEM;
reg [7:0] SNES_OUT_MEM;
@ -61,23 +61,34 @@ assign BSX_DATA_IN = SNES_DATA;
assign SRTC_DATA_IN = SNES_DATA;
assign DSPX_DATA_IN = SNES_DATA;
assign SNES_DATA = SNES_READ ? 8'bZ : (!MCU_OVR ? 8'h00 : (msu_enable ? MSU_DATA_OUT :
bsx_data_ovr ? BSX_DATA_OUT :
srtc_enable ? SRTC_DATA_OUT :
dspx_enable ? DSPX_DATA_OUT : SNES_OUT_MEM));
assign SNES_DATA = SNES_READ ? 8'bZ
:(!MCU_OVR ? 8'h00
:(msu_enable ? MSU_DATA_OUT
: bsx_data_ovr ? BSX_DATA_OUT
: srtc_enable ? SRTC_DATA_OUT
: dspx_enable ? DSPX_DATA_OUT
: SNES_OUT_MEM)
);
assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
assign MCU_OUT_DATA = !MCU_OVR ? (FROM_ROM_BYTE)
: (MCU_OUT_MEM);
:(MCU_OUT_MEM);
assign ROM_DATA[7:0] = ROM_ADDR0 ? (!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
assign ROM_DATA[7:0] = ROM_ADDR0
?(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)))
: 8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ : (!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)
)
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)));
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)
)
);
always @(posedge CLK) begin
if(SNES_DATA_TO_MEM)

105
verilog/sd2snes/main.v
View File

@ -72,10 +72,8 @@ module main(
/* debug */
,
output p113_out
//output DCM_IN_STOPPED,
//output DCM_FX_STOPPED
//input DCM_RST
);
);
assign p113_out = SNES_READ;
wire [7:0] spi_cmd_data;
@ -135,7 +133,8 @@ wire dspx_dat_we;
//wire SD_DMA_EN; //SPI_DMA_CTRL;
sd_dma snes_sd_dma(.CLK(CLK2),
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
@ -149,7 +148,8 @@ sd_dma snes_sd_dma(.CLK(CLK2),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
);
dac snes_dac(.clkin(CLK2),
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk(DAC_MCLK),
.lrck(DAC_LRCK),
@ -177,7 +177,7 @@ srtc snes_srtc (
.rtc_data_out(srtc_rtc_data_out),
.rtc_we(srtc_rtc_we),
.reset(srtc_reset)
);
);
rtc snes_rtc (
.clkin(CLKIN),
@ -186,7 +186,7 @@ rtc snes_rtc (
.pgm_we(rtc_pgm_we),
.rtc_data_in1(srtc_rtc_data_out),
.we1(srtc_rtc_we)
);
);
msu snes_msu (
.clkin(CLK2),
@ -209,9 +209,10 @@ msu snes_msu (
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
);
bsx snes_bsx(.clkin(CLK2),
bsx snes_bsx(
.clkin(CLK2),
.use_bsx(use_bsx),
.pgm_we(bsx_regs_reset_we),
.snes_addr(SNES_ADDR),
@ -225,9 +226,10 @@ bsx snes_bsx(.clkin(CLK2),
.data_ovr(bsx_data_ovr),
.flash_writable(IS_FLASHWR),
.rtc_data(rtc_data)
);
);
spi snes_spi(.clk(CLK2),
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
@ -258,7 +260,7 @@ upd77c25 snes_dspx (
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr)
);
);
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
@ -322,53 +324,16 @@ mcu_cmd snes_mcu_cmd(
);
// dcm1: dfs 4x
my_dcm snes_dcm(.CLKIN(CLKIN),
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
);
assign DCM_RST=0;
/*
dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
.Q(DCM_RST)
);
*/
//wire DCM_FX_STOPPED = DCM_STATUS[2];
//always @(posedge CLKIN) begin
// if(DCM_FX_STOPPED)
// DCM_RSTr <= 1'b1;
// else
// DCM_RSTr <= 1'b0;
//end
/*reg DO_DCM_RESET, DCM_RESETTING;
reg DCM_RSTr;
assign DCM_RST = DCM_RSTr;
reg [2:0] DCM_RESET_CNT;
initial DO_DCM_RESET = 1'b0;
initial DCM_RESETTING = 1'b0;
always @(posedge CLKIN) begin
if(!DCM_LOCKED && !DCM_RESETTING) begin
DCM_RSTr <= 1'b1;
DO_DCM_RESET <= 1'b1;
DCM_RESET_CNT <= 3'b0;
end else if (DO_DCM_RESET) begin
DCM_RSTr <= 1'b0;
DCM_RESET_CNT <= DCM_RESET_CNT + 1;
end
end
always @(posedge CLKIN) begin
if (DO_DCM_RESET)
DCM_RESETTING <= 1'b1;
else if (DCM_RESET_CNT == 3'b110)
DCM_RESETTING <= 1'b0;
end
*/
wire SNES_RW;
reg [1:0] SNES_READr;
reg [1:0] SNES_WRITEr;
@ -400,9 +365,6 @@ end
reg ADDR_WRITE;
//reg [23:0] SNES_ADDRr;
//wire [23:0] SNES_ADDRw = SNES_ADDR;
wire ROM_SEL;
address snes_addr(
@ -432,14 +394,15 @@ address snes_addr(
//uPD77C25
.dspx_enable(dspx_enable),
.dspx_a0(DSPX_A0)
);
);
wire SNES_READ_CYCLEw;
wire SNES_WRITE_CYCLEw;
wire MCU_READ_CYCLEw;
wire MCU_WRITE_CYCLEw;
data snes_data(.CLK(CLK2),
data snes_data(
.CLK(CLK2),
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.MCU_READ(MCU_READ),
@ -467,7 +430,7 @@ data snes_data(.CLK(CLK2),
.bsx_data_ovr(bsx_data_ovr),
.srtc_enable(srtc_enable),
.dspx_enable(dspx_enable)
);
);
parameter MODE_SNES = 1'b0;
parameter MODE_MCU = 1'b1;
@ -523,7 +486,6 @@ assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX];
initial begin
CYCLE_RESET = 2'b0;
STATE = STATE_IDLE;
STATEIDX = 13;
ROM_WE_MASK = 1'b1;
@ -545,21 +507,16 @@ initial begin
ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000;
SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
/* 13'b0001000000000 */
SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
// MCU_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // MCU write
MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read
ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write
ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read
/* 13'b0000100000000; */
ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write
ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read
// SRAM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 13'b0000000000001; // MCU read
end
@ -640,13 +597,16 @@ end
// When in MCU mode, enable SRAM_WE according to MCU programming
// else enable SRAM_WE according to state&cycle
assign ROM_WE = !MCU_OVR ? MCU_WRITE
: ((!IS_FLASHWR & !IS_WRITABLE & !MODE) | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
assign ROM_WE = !MCU_OVR
?MCU_WRITE
:((!IS_FLASHWR & !IS_WRITABLE & !MODE)
| ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
// When in MCU mode, enable SRAM_OE whenever not writing
// else enable SRAM_OE according to state&cycle
assign ROM_OE = !MCU_OVR ? MCU_READ
: ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
assign ROM_OE = !MCU_OVR
?MCU_READ
:ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
@ -664,7 +624,12 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
assign SNES_DATABUS_OE = dspx_enable ? 1'b0 :
msu_enable ? (SNES_READ & SNES_WRITE) :
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
srtc_enable ? (SNES_READ & SNES_WRITE) : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE));
srtc_enable ? (SNES_READ & SNES_WRITE) :
((IS_ROM & SNES_CS)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];

43
verilog/sd2snes/mcu_cmd.v
View File

@ -110,7 +110,7 @@ clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
);
reg [3:0] MAPPER_BUF;
@ -205,7 +205,7 @@ always @(posedge clk) begin
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= cmd_data[1:0];
// 4'hE:
// select memory unit
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
@ -397,9 +397,13 @@ always @(posedge clk) begin
8'hec: // release DSPx reset
dspx_reset_out <= 1'b0;
endcase
end
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[3]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt > (32'h1+cmd_data[4])))
)
begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
@ -410,7 +414,7 @@ end
// value fetch during last SPI bit
always @(posedge clk) begin
if (spi_bit_cnt == 3'h7)
if (spi_bit_cnt == 3'h7) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
@ -459,7 +463,7 @@ always @(posedge clk) begin
MCU_DATA_IN_BUF <= mcu_data_in;
else
MCU_DATA_IN_BUF <= cmd_data;
end
end
// nextaddr pulse generation
@ -473,14 +477,26 @@ end
// r/w pulse
always @(posedge clk) begin
if ((spi_bit_cnt == 3'h1 || spi_bit_cnt == 3'h2 || spi_bit_cnt == 3'h3) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1))
if ((spi_bit_cnt == 3'h1
|| spi_bit_cnt == 3'h2
|| spi_bit_cnt == 3'h3
)
& (cmd_data[7:4] == 4'h9)
& (spi_byte_cnt > 32'h1)
)
MCU_WRITE_BUF <= 1'b0;
else
MCU_WRITE_BUF <= 1'b1;
// Read pulse is two spi cycles to ensure that the value
// Read pulse is 3 spi cycles to ensure that the value
// is ready in the 2nd cycle in MCU master mode
if ((spi_bit_cnt == 3'h5 || spi_bit_cnt == 3'h6 || spi_bit_cnt == 3'h7) & (cmd_data[7:4] == 4'h8) & (spi_byte_cnt > 32'h0))
if ((spi_bit_cnt == 3'h5
|| spi_bit_cnt == 3'h6
|| spi_bit_cnt == 3'h7
)
& (cmd_data[7:4] == 4'h8)
& (spi_byte_cnt > 32'h0)
)
MCU_READ_BUF <= 1'b0;
else
MCU_READ_BUF <= 1'b1;
@ -490,7 +506,14 @@ end
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_read = MCU_READ_BUF;
assign mcu_write = SD_DMA_STATUS ? (SD_DMA_TGTr == 2'b00 ? SD_DMA_SRAM_WE : 1'b1) : MCU_WRITE_BUF;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
?SD_DMA_SRAM_WE
:1'b1
)
: MCU_WRITE_BUF;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;

17
verilog/sd2snes/msu.v
View File

@ -39,7 +39,7 @@ module msu(
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write
);
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
@ -52,7 +52,8 @@ wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [1:0] msu_address_ext_write_sreg;
always @(posedge clkin) msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01);
reg [5:0] reg_oe_sreg;
@ -89,8 +90,12 @@ initial begin
data_busy_r <= 1'b1;
end
assign status_out = {msu_address_r[13],
audio_start_r, data_start_r, volume_start_r, audio_ctrl_r, ctrl_start_r};
assign status_out = {msu_address_r[13], // 6
audio_start_r, // 5
data_start_r, // 4
volume_start_r, // 3
audio_ctrl_r, // 2:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
@ -101,9 +106,9 @@ msu_databuf snes_msu_databuf (
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)); // Bus [7 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
// reg [7:0] data_out_r;
reg [7:0] data_in_r;
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;

15
verilog/sd2snes/rtc.v
View File

@ -25,7 +25,7 @@ module rtc (
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
);
reg [59:0] rtc_data_r;
reg [59:0] rtc_data_out_r;
@ -110,7 +110,6 @@ end
wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
always @(posedge clkin) begin
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
@ -242,7 +241,8 @@ always @(posedge clkin) begin
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month] && rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
if(rtc_data_r[31:28] == dom10[month]
&& rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
@ -344,13 +344,18 @@ always @(posedge clkin) begin
+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24] + (rtc_data_r[31:28] << 1) + (rtc_data_r[31:28] << 3);
dow_day <= rtc_data_r[27:24]
+ (rtc_data_r[31:28] << 1)
+ (rtc_data_r[31:28] << 3);
end
STATE_DOW1: begin
year <= dow_year1[1:0];
if(dow_month <= 2) begin
dow_month <= dow_month + 10;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6) - 1;
dow_year <= dow_year1
+ (dow_year100 << 2)
+ (dow_year100 << 5)
+ (dow_year100 << 6) - 1;
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin

10
verilog/sd2snes/sd2snes.xise
View File

@ -297,8 +297,8 @@
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
@ -327,7 +327,7 @@
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@ -381,8 +381,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>

2
verilog/sd2snes/sd_dma.v
View File

@ -31,7 +31,7 @@ module sd_dma(
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
);
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;

11
verilog/sd2snes/spi.v
View File

@ -19,7 +19,8 @@
//
//////////////////////////////////////////////////////////////////////////////////
module spi(input clk,
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
@ -33,10 +34,7 @@ module spi(input clk,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
// SD "DMA" extension
/*input sd_dma_sck,
input sd_dma_ovr*/);
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
@ -81,7 +79,8 @@ begin
end
end
always @(posedge clk) byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
always @(posedge clk)
byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
always @(posedge clk) begin
if(~SSEL_active)

17
verilog/sd2snes/srtc.v
View File

@ -31,7 +31,7 @@ module srtc(
input enable,
output rtc_we,
input reset
);
);
reg rtc_dirty_r;
assign rtc_dirty = rtc_dirty_r;
@ -90,7 +90,6 @@ always @(posedge clkin) begin
end else if(reg_we_rising && enable) begin
case (addr_in)
// 1'b0: // data register is read only
1'b1: // control register
case (data_in[3:0])
4'hd: begin
@ -129,14 +128,16 @@ always @(posedge clkin) begin
6: rtc_data_out_r[27:24] <= data_in[3:0];
7: rtc_data_out_r[31:28] <= data_in[3:0];
8: begin
rtc_data_out_r[35:32] <= data_in[3:0] < 10 ? data_in[3:0]
rtc_data_out_r[35:32] <= (data_in[3:0] < 10)
? data_in[3:0]
: data_in[3:0] - 10;
rtc_data_out_r[39:36] <= data_in[3:0] < 10 ? 0 : 1;
end
9: rtc_data_out_r[43:40] <= data_in[3:0];
10: rtc_data_out_r[47:44] <= data_in[3:0];
11: begin
rtc_data_out_r[51:48] <= data_in[3:0] < 10 ? data_in[3:0]
rtc_data_out_r[51:48] <= (data_in[3:0] < 10)
? data_in[3:0]
: data_in[3:0] - 10;
rtc_data_out_r[55:52] <= data_in[3:0] < 10 ? 1 : 2;
end
@ -163,10 +164,14 @@ always @(posedge clkin) begin
5: data_out_r <= rtc_data_r[23:20];
6: data_out_r <= rtc_data_r[27:24];
7: data_out_r <= rtc_data_r[31:28];
8: data_out_r <= rtc_data_r[35:32] + (rtc_data_r[39:36] << 1) + (rtc_data_r[39:36] << 3);
8: data_out_r <= rtc_data_r[35:32]
+ (rtc_data_r[39:36] << 1)
+ (rtc_data_r[39:36] << 3);
9: data_out_r <= rtc_data_r[43:40];
10: data_out_r <= rtc_data_r[47:44];
11: data_out_r <= rtc_data_r[51:48] + (rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3) - 10;
11: data_out_r <= rtc_data_r[51:48]
+ (rtc_data_r[55:52] << 1)
+ (rtc_data_r[55:52] << 3) - 10;
12: data_out_r <= rtc_data_r[59:56];
15: begin
rtc_data_r <= rtc_data_in;

12
verilog/sd2snes/upd77c25.v
View File

@ -132,7 +132,11 @@ upd77c25_datram datram (
.douta(ram_douta)); // Bus [15 : 0]
assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == STATE_NEXT);
assign ram_addra = {regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100) ? 4'b0100 : 4'b0000), regs_dpl};
assign ram_addra = {regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100)
? 4'b0100
: 4'b0000),
regs_dpl};
reg signed [15:0] regs_k;
reg signed [15:0] regs_l;
reg [15:0] regs_trb;
@ -142,7 +146,6 @@ reg [15:0] regs_sr;
reg [15:0] regs_si;
reg [3:0] regs_sp;
reg cond_true;
reg [8:0] jp_brch;
@ -211,12 +214,12 @@ always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[6:0], nCS};
reg [5:0] reg_oe_sreg;
initial reg_oe_sreg = 6'b111111;
always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
wire reg_oe_rising = !reg_nCS_sreg[2] && (reg_oe_sreg[5:0] == 6'b000001);
wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
reg [5:0] reg_we_sreg;
initial reg_we_sreg = 6'b111111;
always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
wire reg_we_rising = !reg_nCS_sreg[2] && (reg_we_sreg[5:0] == 6'b000001);
wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
reg [7:0] A0r;
initial A0r = 8'b11111111;
@ -582,7 +585,6 @@ always @(posedge CLK) begin
end
STATE_IDLE1: insn_state <= STATE_IDLE2;
STATE_IDLE2: insn_state <= STATE_FETCH;
endcase
end else begin
insn_state <= STATE_IDLE1;