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FPGA: code formatting, update synthesis configuration, timing

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This commit is contained in:
ikari 2011-06-18 02:27:56 +02:00
parent 630d75cacc
commit a8d64311c6
14 changed files with 1741 additions and 1673 deletions
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240
verilog/sd2snes/address.v
View File

@ -18,37 +18,37 @@
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input SNES_CS, // "CART" pin from SNES (active low)
output [22:0] ROM_ADDR, // Address to request from SRAM0
output ROM_SEL, // enable SRAM0 (active low)
input MCU_OVR, // enable MCU master mode (active low)
input MODE, // MCU(1) or SNES(0) ("bus phase")
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] MCU_ADDR, // allow address to be set externally
input ADDR_WRITE,
output ROM_ADDR0,
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
input use_msu,
output msu_enable,
output srtc_enable,
output use_bsx,
input [14:0] bsx_regs,
output dspx_enable,
output dspx_a0
);
input CLK,
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input SNES_CS, // "CART" pin from SNES (active low)
output [22:0] ROM_ADDR, // Address to request from SRAM0
output ROM_SEL, // enable SRAM0 (active low)
input MCU_OVR, // enable MCU master mode (active low)
input MODE, // MCU(1) or SNES(0) ("bus phase")
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] MCU_ADDR, // allow address to be set externally
input ADDR_WRITE,
output ROM_ADDR0,
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
input use_msu,
output msu_enable,
output srtc_enable,
output use_bsx,
input [14:0] bsx_regs,
output dspx_enable,
output dspx_a0
);
wire [1:0] SRAM_BANK;
wire [23:0] SRAM_ADDR_FULL;
/* currently supported mappers:
Index Mapper
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
@ -59,13 +59,13 @@ wire [23:0] SRAM_ADDR_FULL;
111 menu (ROM in upper SRAM)
*/
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
/* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf
Offset 6000-7fff */
assign IS_ROM = ( (MAPPER == 3'b000) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b001) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
|(SNES_ADDR[22]))
: (MAPPER == 3'b010) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b011) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
@ -73,88 +73,132 @@ assign IS_ROM = ( (MAPPER == 3'b000) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
: (MAPPER == 3'b100) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b101) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
|(SNES_ADDR[22]))
: (MAPPER == 3'b110) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: (MAPPER == 3'b111) ? ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]))
: 1'b0);
assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b100 || MAPPER == 3'b110 || MAPPER == 3'b111) ? (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd
Offset 0000-7fff TODO: 0000-ffff for
small ROMs */
:(MAPPER == 3'b001 || MAPPER == 3'b101) ? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15])
/* BS-X: SRAM @ Bank 0x10-0x17
Offset 5000-5fff */
:(MAPPER == 3'b011) ? ((SNES_ADDR[23:19] == 5'b00010)
& (SNES_ADDR[15:12] == 4'b0101)
)
assign IS_SAVERAM = ((MAPPER == 3'b000
|| MAPPER == 3'b010
|| MAPPER == 3'b100
|| MAPPER == 3'b110
|| MAPPER == 3'b111)
? (!SNES_ADDR[22]
& &SNES_ADDR[21:20]
& &SNES_ADDR[14:13]
& !SNES_ADDR[15]
)
/* LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xfd Offset 0000-7fff
TODO: 0000-ffff for small ROMs? */
:(MAPPER == 3'b001
|| MAPPER == 3'b101)
? (&SNES_ADDR[22:20]
& (SNES_ADDR[19:16] < 4'b1110)
& !SNES_ADDR[15]
)
/* BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff */
:(MAPPER == 3'b011)
? ((SNES_ADDR[23:19] == 5'b00010)
& (SNES_ADDR[15:12] == 4'b0101)
)
: 1'b0);
assign IS_WRITABLE = IS_SAVERAM | (
(MAPPER == 3'b011)
? (
(bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
|(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
|(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
|(SNES_ADDR[23:19] == 5'b01110)
|(SNES_ADDR[23:21] == 3'b001 && SNES_ADDR[15:13] == 3'b011))
: 1'b0);
assign IS_WRITABLE = IS_SAVERAM
|((MAPPER == 3'b011)
?((bsx_regs[3] && SNES_ADDR[23:20]==4'b0110)
|(!bsx_regs[5] && SNES_ADDR[23:20]==4'b0100)
|(!bsx_regs[6] && SNES_ADDR[23:20]==4'b0101)
|(SNES_ADDR[23:19] == 5'b01110)
|(SNES_ADDR[23:21] == 3'b001
&& SNES_ADDR[15:13] == 3'b011)
)
: 1'b0);
/* BSX regs:
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
2 1=HiROM; 0=LoROM
3 1=Mirror PRAM @60-6f:0000-ffff
5 1=DO NOT mirror PRAM @40-4f:0000-ffff
6 1=DO NOT mirror PRAM @50-5f:0000-ffff
7 1=map BSX cartridge ROM @00-1f:8000-ffff
8 1=map BSX cartridge ROM @80-9f:8000-ffff
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
2 1=HiROM; 0=LoROM
3 1=Mirror PRAM @60-6f:0000-ffff
5 1=DO NOT mirror PRAM @40-4f:0000-ffff
6 1=DO NOT mirror PRAM @50-5f:0000-ffff
7 1=map BSX cartridge ROM @00-1f:8000-ffff
8 1=map BSX cartridge ROM @80-9f:8000-ffff
*/
assign SRAM_ADDR_FULL = (MODE) ? MCU_ADDR
: ((MAPPER[1:0] == 2'b00) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER[1:0] == 2'b01) ?
(IS_SAVERAM ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
:(MAPPER == 3'b010) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
:(MAPPER == 3'b011) ?
(IS_SAVERAM ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: IS_WRITABLE ? (24'h400000 + (SNES_ADDR & 24'h0FFFFF /*7ffff*/))
: ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
|(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
? (24'h800000 + ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & 24'h0FFFFF))
: ((bsx_regs[1] ? 24'h400000 : 24'h000000)
+ bsx_regs[2] ? ({2'b00, SNES_ADDR[21:0]} & (ROM_MASK /* >> bsx_regs[1] */))
: ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]} & (ROM_MASK /* >> bsx_regs[1] */))))
:(MAPPER == 3'b110) ?
(IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: (SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
: ({2'b10, SNES_ADDR[23], SNES_ADDR[21:16], SNES_ADDR[14:0]})))
:(MAPPER == 3'b111) ?
(IS_SAVERAM ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) + 24'hE00000))
: 24'b0);
:((MAPPER[1:0] == 2'b00)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
:(MAPPER[1:0] == 2'b01)
?(IS_SAVERAM
? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK)
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK))
:(MAPPER == 3'b010)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]}
& ROM_MASK))
:(MAPPER == 3'b011)
?(IS_SAVERAM
? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: IS_WRITABLE
? (24'h400000 + (SNES_ADDR & 24'h07FFFF))
: ((bsx_regs[7] && SNES_ADDR[23:21] == 3'b000)
|(bsx_regs[8] && SNES_ADDR[23:21] == 3'b100))
?(24'h800000
+ ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
& 24'h0FFFFF)
)
:((bsx_regs[1]
? 24'h400000
: 24'h000000
)
+ bsx_regs[2]
?({2'b00, SNES_ADDR[21:0]}
& (ROM_MASK /* >> bsx_regs[1] */)
)
:({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}
& (ROM_MASK /* >> bsx_regs[1] */)
)
)
)
:(MAPPER == 3'b110)
?(IS_SAVERAM
? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
:(SNES_ADDR[15]
?({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10,
SNES_ADDR[23],
SNES_ADDR[21:16],
SNES_ADDR[14:0]}
)
)
)
:(MAPPER == 3'b111)
?(IS_SAVERAM
? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000)
& SAVERAM_MASK)
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK)
+ 24'hE00000)
)
: 24'b0);
assign ROM_ADDR = SRAM_ADDR_FULL[23:1];
assign ROM_SEL = 1'b0; // (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK];
assign ROM_ADDR0 = SRAM_ADDR_FULL[0];
//488888
assign msu_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign use_bsx = (MAPPER == 3'b011);
@ -164,14 +208,16 @@ assign srtc_enable = (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h280
// or DR=60-6f:0000-3fff; SR=60-6f:4000-7fff
// DSP1 HiROM: DR=00-0f:6000-6fff; SR=00-0f:7000-7fff
wire dspx_enable_w =
(MAPPER == 3'b101) ?
(ROM_MASK[20] ?
(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
:(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
)
:(MAPPER == 3'b100) ?
(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15] & &SNES_ADDR[14:13]/* & CS */)
(MAPPER == 3'b101)
?(ROM_MASK[20]
?(SNES_ADDR[22] & SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15])
:(~SNES_ADDR[22] & SNES_ADDR[21] & SNES_ADDR[20] & SNES_ADDR[15])
)
:(MAPPER == 3'b100)
?(~SNES_ADDR[22] & ~SNES_ADDR[21] & ~SNES_ADDR[20] & ~SNES_ADDR[15]
& &SNES_ADDR[14:13])
:1'b0;
assign dspx_a0 = (MAPPER == 3'b101) ? SNES_ADDR[14]
:(MAPPER == 3'b100) ? SNES_ADDR[12]
:1'b1;

229
verilog/sd2snes/bsx.v
View File

@ -19,22 +19,22 @@
//
//////////////////////////////////////////////////////////////////////////////////
module bsx(
input clkin,
input reg_oe,
input reg_we,
input [23:0] snes_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input [7:0] reg_reset_bits,
input [7:0] reg_set_bits,
output [14:0] regs_out,
input pgm_we,
input [14:0] regs_in,
input use_bsx,
output data_ovr,
output flash_writable,
input [59:0] rtc_data
);
input clkin,
input reg_oe,
input reg_we,
input [23:0] snes_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input [7:0] reg_reset_bits,
input [7:0] reg_set_bits,
output [14:0] regs_out,
input pgm_we,
input [14:0] regs_in,
input use_bsx,
output data_ovr,
output flash_writable,
input [59:0] rtc_data
);
wire [3:0] reg_addr = snes_addr[19:16]; // 00-0f:5000-5fff
wire [4:0] base_addr = snes_addr[4:0]; // 88-9f -> 08-1f
@ -46,19 +46,28 @@ reg [16:0] flash_cmd0;
reg [24:0] flash_cmd5555;
wire cart_enable = (use_bsx) && ((snes_addr[23:12] & 12'hf0f) == 12'h005);
wire base_enable = (use_bsx) && (!snes_addr[22] && (snes_addr[15:0] >= 16'h2188)
&& (snes_addr[15:0] <= 16'h219f));
&& (snes_addr[15:0] <= 16'h219f));
wire flash_enable = (snes_addr[23:16] == 8'hc0);
wire is_flash_special_address = (flash_addr == 16'h0002
|| flash_addr == 16'h5555
|| flash_addr == 16'h2aaa
|| flash_addr == 16'h0000
|| (flash_addr >= 16'hff00 && flash_addr <= 16'hff13));
wire flash_ovr = (use_bsx) && (flash_enable & flash_ovr_r) && is_flash_special_address;
assign flash_writable = (use_bsx) && flash_enable && flash_we_r && !is_flash_special_address;
|| flash_addr == 16'h5555
|| flash_addr == 16'h2aaa
|| flash_addr == 16'h0000
|| (flash_addr >= 16'hff00
&& flash_addr <= 16'hff13));
wire flash_ovr = (use_bsx)
&& (flash_enable & flash_ovr_r)
&& is_flash_special_address;
assign flash_writable = (use_bsx)
&& flash_enable
&& flash_we_r
&& !is_flash_special_address;
assign data_ovr = cart_enable | base_enable | flash_ovr;
reg [5:0] reg_oe_sreg;
@ -114,7 +123,7 @@ initial begin
base_regs[22] <= 8'h02;
base_regs[23] <= 8'hff;
base_regs[24] <= 8'h80;
base_regs[25] <= 8'h01;
base_regs[25] <= 8'h01;
base_regs[26] <= 0;
base_regs[27] <= 0;
base_regs[28] <= 0;
@ -138,100 +147,100 @@ always @(posedge clkin) begin
if(reg_oe_falling) begin
if(cart_enable)
reg_data_outr <= {regs_outr[reg_addr], 7'b0};
else if(base_enable) begin
case(base_addr)
5'b10010: begin
if(bsx_counter < 18) begin
bsx_counter <= bsx_counter + 1;
case (bsx_counter)
5:
reg_data_outr <= 8'h1;
6:
reg_data_outr <= 8'h1;
10:
reg_data_outr <= rtc_sec;
11:
reg_data_outr <= rtc_min;
12:
reg_data_outr <= rtc_hour;
default:
reg_data_outr <= 8'h0;
endcase
end else begin
reg_data_outr <= 8'h0;
bsx_counter <= 0;
end
end
5'b10011:
reg_data_outr <= base_regs[base_addr] & 8'h3f;
else if(base_enable) begin
case(base_addr)
5'b10010: begin
if(bsx_counter < 18) begin
bsx_counter <= bsx_counter + 1;
case (bsx_counter)
5:
reg_data_outr <= 8'h1;
6:
reg_data_outr <= 8'h1;
10:
reg_data_outr <= rtc_sec;
11:
reg_data_outr <= rtc_min;
12:
reg_data_outr <= rtc_hour;
default:
reg_data_outr <= 8'h0;
endcase
end else begin
reg_data_outr <= 8'h0;
bsx_counter <= 0;
end
end
5'b10011:
reg_data_outr <= base_regs[base_addr] & 8'h3f;
default:
reg_data_outr <= base_regs[base_addr];
endcase
end else if (flash_enable) begin
casex (flash_addr)
16'h0002:
reg_data_outr <= 8'h80;
16'h5555:
reg_data_outr <= 8'h80;
16'b1111111100000xxx:
reg_data_outr <= flash_vendor_data[flash_addr&16'h0007];
default:
reg_data_outr <= 8'h00;
endcase
end
reg_data_outr <= base_regs[base_addr];
endcase
end else if (flash_enable) begin
casex (flash_addr)
16'h0002:
reg_data_outr <= 8'h80;
16'h5555:
reg_data_outr <= 8'h80;
16'b1111111100000xxx:
reg_data_outr <= flash_vendor_data[flash_addr&16'h0007];
default:
reg_data_outr <= 8'h00;
endcase
end
end else if(pgm_we_rising) begin
regs_tmpr[8:1] <= (regs_tmpr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
regs_outr[8:1] <= (regs_outr[8:1] | reg_set_bits[7:0]) & ~reg_reset_bits[7:0];
end else if(reg_we_rising && cart_enable) begin
if(reg_addr == 4'he && reg_data_in[7])
regs_outr <= regs_tmpr | 16'b0100000000000000;
else
regs_outr <= regs_tmpr | 16'b0100000000000000;
else
regs_tmpr[reg_addr] <= reg_data_in[7];
end else if(reg_we_rising && base_enable) begin
case(base_addr)
5'h0f: begin
base_regs[base_addr-1] <= base_regs[base_addr]-(base_regs[base_addr-1] >> 1);
base_regs[base_addr] <= base_regs[base_addr] >> 1;
end
5'h11: begin
bsx_counter <= 0;
base_regs[base_addr] <= reg_data_in;
end
5'h12: begin
base_regs[8'h10] <= 8'h80;
end
default:
case(base_addr)
5'h0f: begin
base_regs[base_addr-1] <= base_regs[base_addr]-(base_regs[base_addr-1] >> 1);
base_regs[base_addr] <= base_regs[base_addr] >> 1;
end
5'h11: begin
bsx_counter <= 0;
base_regs[base_addr] <= reg_data_in;
endcase
end
5'h12: begin
base_regs[8'h10] <= 8'h80;
end
default:
base_regs[base_addr] <= reg_data_in;
endcase
end else if(reg_we_rising && flash_enable) begin
case(flash_addr)
16'h0000: begin
flash_cmd0 <= {flash_cmd0[7:0], reg_data_in};
if(flash_cmd0[7:0] == 8'h38 && reg_data_in == 8'hd0)
flash_ovr_r <= 1;
end
16'h5555: begin
flash_cmd5555 <= {flash_cmd5555[15:0], reg_data_in};
if(flash_cmd5555[15:0] == 16'haa55) begin
case (reg_data_in)
8'hf0: begin
flash_ovr_r <= 0;
flash_we_r <= 0;
end
8'ha0: begin
flash_ovr_r <= 1;
flash_we_r <= 1;
end
8'h70: begin
flash_we_r <= 0;
end
endcase
end
end
16'h2aaa: begin
flash_cmd5555 <= {flash_cmd5555[15:0], reg_data_in};
end
endcase
16'h0000: begin
flash_cmd0 <= {flash_cmd0[7:0], reg_data_in};
if(flash_cmd0[7:0] == 8'h38 && reg_data_in == 8'hd0)
flash_ovr_r <= 1;
end
16'h5555: begin
flash_cmd5555 <= {flash_cmd5555[15:0], reg_data_in};
if(flash_cmd5555[15:0] == 16'haa55) begin
case (reg_data_in)
8'hf0: begin
flash_ovr_r <= 0;
flash_we_r <= 0;
end
8'ha0: begin
flash_ovr_r <= 1;
flash_we_r <= 1;
end
8'h70: begin
flash_we_r <= 0;
end
endcase
end
end
16'h2aaa: begin
flash_cmd5555 <= {flash_cmd5555[15:0], reg_data_in};
end
endcase
end
end

12
verilog/sd2snes/clk_test.v
View File

@ -19,10 +19,10 @@
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
@ -44,8 +44,8 @@ always @(posedge clk) begin
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end

174
verilog/sd2snes/dac.v
View File

@ -1,38 +1,38 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Company:
// Engineer:
//
// Dependencies:
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Revision:
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input play,
input reset,
output sdout,
output lrck,
output mclk,
output DAC_STATUS
);
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input play,
input reset,
output sdout,
output lrck,
output mclk,
output DAC_STATUS
);
reg[8:0] dac_address_r;
wire[8:0] dac_address = dac_address_r;
@ -55,13 +55,13 @@ always @(posedge clkin) begin
end
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
reg [15:0] cnt;
reg [15:0] smpcnt;
@ -71,11 +71,9 @@ wire [15:0] sample2 = {smpcnt[9] ? ~smpcnt[8:0] : smpcnt[8:0], 7'b0};
reg [15:0] smpshift;
reg [15:0] smpdata;
assign mclk = cnt[2]; // mclk = clk/8
//assign lrck = cnt[10]; // lrck = mclk/512
//wire sclk = cnt[5]; // sclk = lrck*32
assign lrck = cnt[8]; // lrck = mclk/128
wire sclk = cnt[3]; // sclk = lrck*32
assign mclk = cnt[2]; // mclk = clk/8
assign lrck = cnt[8]; // lrck = mclk/128
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] lrck_sreg;
reg [2:0] sclk_sreg;
@ -94,77 +92,77 @@ wire reset_rising = (reset_sreg[1:0] == 2'b01);
reg play_r;
initial begin
cnt = 16'hff00;
smpcnt = 16'b0;
lrck_sreg = 2'b11;
sclk_sreg = 1'b0;
dac_address_r = 10'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 8'h0;
vol_target_reg = 8'hff;
samples <= 16'h0;
cnt = 16'hff00;
smpcnt = 16'b0;
lrck_sreg = 2'b11;
sclk_sreg = 1'b0;
dac_address_r = 10'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 8'h0;
vol_target_reg = 8'hff;
samples <= 16'h0;
end
always @(posedge clkin) begin
if(reset_rising) begin
dac_address_r <= 0;
interpol_overflow <= 0;
interpol_count <= 0;
interpol_overflow <= 0;
interpol_count <= 0;
end else if(sysclk_rising) begin
if(interpol_count > 59378938) begin
interpol_count <= interpol_count + 122500 - 59501439;
interpol_count <= interpol_count + 122500 - 59501439;
dac_address_r <= dac_address_r + play_r;
interpol_overflow <= 1;
end else begin
interpol_count <= interpol_count + 122500;
interpol_overflow <= 0;
end
interpol_overflow <= 1;
end else begin
interpol_count <= interpol_count + 122500;
interpol_overflow <= 0;
end
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[1:0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
reset_sreg <= {reset_sreg[0], reset};
cnt <= cnt + 1;
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[1:0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
reset_sreg <= {reset_sreg[0], reset};
end
always @(posedge clkin) begin
if (vol_latch_rising) begin
vol_valid <= 1'b1;
end
else if(vol_valid) begin
vol_target_reg <= volume;
vol_valid <= 1'b0;
end
if (vol_latch_rising) begin
vol_valid <= 1'b1;
end
else if(vol_valid) begin
vol_target_reg <= volume;
vol_valid <= 1'b0;
end
end
// ramp volume only every 4 samples
always @(posedge clkin) begin
if (lrck_rising && &samples[1:0]) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
if (lrck_rising && &samples[1:0]) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
always @(posedge clkin) begin
if (lrck_rising) begin // right channel
smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
samples <= samples + 1;
end else if (lrck_falling) begin // left channel
smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
end else begin
if (sclk_rising) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
smpshift <= {smpshift[14:0], 1'b0};
end
end
if (lrck_rising) begin // right channel
smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
samples <= samples + 1;
end else if (lrck_falling) begin // left channel
smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
end else begin
if (sclk_rising) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule

111
verilog/sd2snes/data.v
View File

@ -19,35 +19,35 @@
//
//////////////////////////////////////////////////////////////////////////////////
module data(
input CLK,
input SNES_READ,
input SNES_WRITE,
input MCU_READ,
input MCU_WRITE,
inout [7:0] SNES_DATA,
inout [15:0] ROM_DATA,
input [7:0] MCU_IN_DATA,
output [7:0] MCU_OUT_DATA,
input MODE,
input SNES_DATA_TO_MEM,
input MCU_DATA_TO_MEM,
input ROM_DATA_TO_SNES_MEM,
input ROM_DATA_TO_MCU_MEM,
input MCU_OVR,
input ROM_ADDR0,
output [7:0] MSU_DATA_IN,
input [7:0] MSU_DATA_OUT,
output [7:0] BSX_DATA_IN,
input [7:0] BSX_DATA_OUT,
output [7:0] SRTC_DATA_IN,
input [7:0] SRTC_DATA_OUT,
output [7:0] DSPX_DATA_IN,
input [7:0] DSPX_DATA_OUT,
input msu_enable,
input bsx_data_ovr,
input srtc_enable,
input dspx_enable
);
input CLK,
input SNES_READ,
input SNES_WRITE,
input MCU_READ,
input MCU_WRITE,
inout [7:0] SNES_DATA,
inout [15:0] ROM_DATA,
input [7:0] MCU_IN_DATA,
output [7:0] MCU_OUT_DATA,
input MODE,
input SNES_DATA_TO_MEM,
input MCU_DATA_TO_MEM,
input ROM_DATA_TO_SNES_MEM,
input ROM_DATA_TO_MCU_MEM,
input MCU_OVR,
input ROM_ADDR0,
output [7:0] MSU_DATA_IN,
input [7:0] MSU_DATA_OUT,
output [7:0] BSX_DATA_IN,
input [7:0] BSX_DATA_OUT,
output [7:0] SRTC_DATA_IN,
input [7:0] SRTC_DATA_OUT,
output [7:0] DSPX_DATA_IN,
input [7:0] DSPX_DATA_OUT,
input msu_enable,
input bsx_data_ovr,
input srtc_enable,
input dspx_enable
);
reg [7:0] SNES_IN_MEM;
reg [7:0] SNES_OUT_MEM;
@ -61,33 +61,44 @@ assign BSX_DATA_IN = SNES_DATA;
assign SRTC_DATA_IN = SNES_DATA;
assign DSPX_DATA_IN = SNES_DATA;
assign SNES_DATA = SNES_READ ? 8'bZ : (!MCU_OVR ? 8'h00 : (msu_enable ? MSU_DATA_OUT :
bsx_data_ovr ? BSX_DATA_OUT :
srtc_enable ? SRTC_DATA_OUT :
dspx_enable ? DSPX_DATA_OUT : SNES_OUT_MEM));
assign SNES_DATA = SNES_READ ? 8'bZ
:(!MCU_OVR ? 8'h00
:(msu_enable ? MSU_DATA_OUT
: bsx_data_ovr ? BSX_DATA_OUT
: srtc_enable ? SRTC_DATA_OUT
: dspx_enable ? DSPX_DATA_OUT
: SNES_OUT_MEM)
);
assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
assign MCU_OUT_DATA = !MCU_OVR ? (FROM_ROM_BYTE)
: (MCU_OUT_MEM);
:(MCU_OUT_MEM);
assign ROM_DATA[7:0] = ROM_ADDR0
?(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)
)
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)
)
);
assign ROM_DATA[7:0] = ROM_ADDR0 ? (!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)))
: 8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ : (!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ)
: (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ)
: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ)));
always @(posedge CLK) begin
if(SNES_DATA_TO_MEM)
SNES_IN_MEM <= SNES_DATA;
if(MCU_DATA_TO_MEM)
MCU_IN_MEM <= MCU_IN_DATA;
if(ROM_DATA_TO_SNES_MEM)
SNES_OUT_MEM <= FROM_ROM_BYTE;
if(ROM_DATA_TO_MCU_MEM)
MCU_OUT_MEM <= FROM_ROM_BYTE;
if(SNES_DATA_TO_MEM)
SNES_IN_MEM <= SNES_DATA;
if(MCU_DATA_TO_MEM)
MCU_IN_MEM <= MCU_IN_DATA;
if(ROM_DATA_TO_SNES_MEM)
SNES_OUT_MEM <= FROM_ROM_BYTE;
if(ROM_DATA_TO_MCU_MEM)
MCU_OUT_MEM <= FROM_ROM_BYTE;
end
endmodule

803
verilog/sd2snes/main.v
View File

@ -19,63 +19,61 @@
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR,
input SNES_READ,
input SNES_WRITE,
input SNES_CS,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK,
input SNES_REFRESH,
inout SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
output IRQ_DIR,
input SNES_SYSCLK,
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR,
input SNES_READ,
input SNES_WRITE,
input SNES_CS,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK,
input SNES_REFRESH,
inout SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
output IRQ_DIR,
input SNES_SYSCLK,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
/* debug */
,
output p113_out
);
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
/* debug */
,
output p113_out
//output DCM_IN_STOPPED,
//output DCM_FX_STOPPED
//input DCM_RST
);
assign p113_out = SNES_READ;
wire [7:0] spi_cmd_data;
@ -128,247 +126,214 @@ wire [7:0] DSPX_SNES_DATA_OUT;
wire [23:0] dspx_pgm_data;
wire [10:0] dspx_pgm_addr;
wire dspx_pgm_we;
wire [15:0] dspx_dat_data;
wire [9:0] dspx_dat_addr;
wire dspx_dat_we;
//wire SD_DMA_EN; //SPI_DMA_CTRL;
sd_dma snes_sd_dma(.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
);
dac snes_dac(.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk(DAC_MCLK),
.lrck(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.play(dac_play),
.reset(dac_reset)
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk(DAC_MCLK),
.lrck(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.play(dac_play),
.reset(dac_reset)
);
srtc snes_srtc (
.clkin(CLK2),
/*XXX*/.reg_addr(srtc_reg_addr),
.addr_in(SNES_ADDR[0]),
.data_in(SRTC_SNES_DATA_IN),
.data_out(SRTC_SNES_DATA_OUT),
.rtc_data_in(rtc_data),
.reg_we(SNES_WRITE),
.reg_oe(SNES_READ),
.enable(srtc_enable),
.rtc_data_out(srtc_rtc_data_out),
.rtc_we(srtc_rtc_we),
.reset(srtc_reset)
);
.clkin(CLK2),
/*XXX*/.reg_addr(srtc_reg_addr),
.addr_in(SNES_ADDR[0]),
.data_in(SRTC_SNES_DATA_IN),
.data_out(SRTC_SNES_DATA_OUT),
.rtc_data_in(rtc_data),
.reg_we(SNES_WRITE),
.reg_oe(SNES_READ),
.enable(srtc_enable),
.rtc_data_out(srtc_rtc_data_out),
.rtc_we(srtc_rtc_we),
.reset(srtc_reset)
);
rtc snes_rtc (
.clkin(CLKIN),
.rtc_data(rtc_data),
.rtc_data_in(rtc_data_in),
.pgm_we(rtc_pgm_we),
.rtc_data_in1(srtc_rtc_data_out),
.we1(srtc_rtc_we)
);
.clkin(CLKIN),
.rtc_data(rtc_data),
.rtc_data_in(rtc_data_in),
.pgm_we(rtc_pgm_we),
.rtc_data_in1(srtc_rtc_data_out),
.we1(srtc_rtc_we)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe(SNES_READ),
.reg_we(SNES_WRITE),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe(SNES_READ),
.reg_we(SNES_WRITE),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
bsx snes_bsx(.clkin(CLK2),
.use_bsx(use_bsx),
.pgm_we(bsx_regs_reset_we),
.snes_addr(SNES_ADDR),
.reg_data_in(BSX_SNES_DATA_IN),
.reg_data_out(BSX_SNES_DATA_OUT),
.reg_oe(SNES_READ),
.reg_we(SNES_WRITE),
.regs_out(bsx_regs),
.reg_reset_bits(bsx_regs_reset_bits),
.reg_set_bits(bsx_regs_set_bits),
.data_ovr(bsx_data_ovr),
.flash_writable(IS_FLASHWR),
.rtc_data(rtc_data)
);
bsx snes_bsx(
.clkin(CLK2),
.use_bsx(use_bsx),
.pgm_we(bsx_regs_reset_we),
.snes_addr(SNES_ADDR),
.reg_data_in(BSX_SNES_DATA_IN),
.reg_data_out(BSX_SNES_DATA_OUT),
.reg_oe(SNES_READ),
.reg_we(SNES_WRITE),
.regs_out(bsx_regs),
.reg_reset_bits(bsx_regs_reset_bits),
.reg_set_bits(bsx_regs_set_bits),
.data_ovr(bsx_data_ovr),
.flash_writable(IS_FLASHWR),
.rtc_data(rtc_data)
);
spi snes_spi(.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
upd77c25 snes_dspx (
.DI(DSPX_SNES_DATA_IN),
.DO(DSPX_SNES_DATA_OUT),
.A0(DSPX_A0),
.nCS(~dspx_enable),
.nRD(SNES_READ),
.nWR(SNES_WRITE),
.RST(~dspx_reset),
.CLK(CLK2),
.PGM_WR(dspx_pgm_we),
.PGM_DI(dspx_pgm_data),
.PGM_WR_ADDR(dspx_pgm_addr),
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr)
);
.DI(DSPX_SNES_DATA_IN),
.DO(DSPX_SNES_DATA_OUT),
.A0(DSPX_A0),
.nCS(~dspx_enable),
.nRD(SNES_READ),
.nWR(SNES_WRITE),
.RST(~dspx_reset),
.CLK(CLK2),
.PGM_WR(dspx_pgm_we),
.PGM_DI(dspx_pgm_data),
.PGM_WR_ADDR(dspx_pgm_addr),
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr)
);
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_sram_size(SRAM_SIZE),
.mcu_read(MCU_READ),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_OUT_DATA),
.mcu_data_out(MCU_IN_DATA),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),
// .dac_volume_latch_out(dac_vol_latch),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.bsx_regs_set_out(bsx_regs_set_bits),
.bsx_regs_reset_out(bsx_regs_reset_bits),
.bsx_regs_reset_we(bsx_regs_reset_we),
.rtc_data_out(rtc_data_in),
.rtc_pgm_we(rtc_pgm_we),
.srtc_reset(srtc_reset),
.dspx_pgm_data_out(dspx_pgm_data),
.dspx_pgm_addr_out(dspx_pgm_addr),
.dspx_pgm_we_out(dspx_pgm_we),
.dspx_dat_data_out(dspx_dat_data),
.dspx_dat_addr_out(dspx_dat_addr),
.dspx_dat_we_out(dspx_dat_we),
.dspx_reset_out(dspx_reset)
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_sram_size(SRAM_SIZE),
.mcu_read(MCU_READ),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_OUT_DATA),
.mcu_data_out(MCU_IN_DATA),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),
// .dac_volume_latch_out(dac_vol_latch),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.bsx_regs_set_out(bsx_regs_set_bits),
.bsx_regs_reset_out(bsx_regs_reset_bits),
.bsx_regs_reset_we(bsx_regs_reset_we),
.rtc_data_out(rtc_data_in),
.rtc_pgm_we(rtc_pgm_we),
.srtc_reset(srtc_reset),
.dspx_pgm_data_out(dspx_pgm_data),
.dspx_pgm_addr_out(dspx_pgm_addr),
.dspx_pgm_we_out(dspx_pgm_we),
.dspx_dat_data_out(dspx_dat_data),
.dspx_dat_addr_out(dspx_dat_addr),
.dspx_dat_we_out(dspx_dat_we),
.dspx_reset_out(dspx_reset)
);
// dcm1: dfs 4x
my_dcm snes_dcm(.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
assign DCM_RST=0;
/*
dcm_srl16 snes_dcm_resetter(.CLK(CLKIN),
.Q(DCM_RST)
);
*/
//wire DCM_FX_STOPPED = DCM_STATUS[2];
//always @(posedge CLKIN) begin
// if(DCM_FX_STOPPED)
// DCM_RSTr <= 1'b1;
// else
// DCM_RSTr <= 1'b0;
//end
/*reg DO_DCM_RESET, DCM_RESETTING;
reg DCM_RSTr;
assign DCM_RST = DCM_RSTr;
reg [2:0] DCM_RESET_CNT;
initial DO_DCM_RESET = 1'b0;
initial DCM_RESETTING = 1'b0;
always @(posedge CLKIN) begin
if(!DCM_LOCKED && !DCM_RESETTING) begin
DCM_RSTr <= 1'b1;
DO_DCM_RESET <= 1'b1;
DCM_RESET_CNT <= 3'b0;
end else if (DO_DCM_RESET) begin
DCM_RSTr <= 1'b0;
DCM_RESET_CNT <= DCM_RESET_CNT + 1;
end
end
always @(posedge CLKIN) begin
if (DO_DCM_RESET)
DCM_RESETTING <= 1'b1;
else if (DCM_RESET_CNT == 3'b110)
DCM_RESETTING <= 1'b0;
end
*/
wire SNES_RW;
reg [1:0] SNES_READr;
reg [1:0] SNES_WRITEr;
@ -391,84 +356,82 @@ wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
assign SNES_RW = (SNES_READ & SNES_WRITE);
always @(posedge CLK2) begin
SNES_READr <= {SNES_READr[0], SNES_READ};
SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
SNES_CSr <= {SNES_CSr[0], SNES_CS};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
SNES_READr <= {SNES_READr[0], SNES_READ};
SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
SNES_CSr <= {SNES_CSr[0], SNES_CS};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
end
reg ADDR_WRITE;
//reg [23:0] SNES_ADDRr;
//wire [23:0] SNES_ADDRw = SNES_ADDR;
wire ROM_SEL;
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
.ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low)
.ROM_SEL(ROM_SEL), // which SRAM unit to access
.MCU_OVR(MCU_OVR), // enable MCU mode (active low)
.MODE(MODE), // MCU(1) or SNES(0) ("bus phase")
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.MCU_ADDR(MCU_ADDR),
.ROM_ADDR0(ROM_ADDR0),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.use_msu(use_msu),
.msu_enable(msu_enable),
//BS-X
.use_bsx(use_bsx),
.bsx_regs(bsx_regs),
//SRTC
.srtc_enable(srtc_enable),
//uPD77C25
.dspx_enable(dspx_enable),
.dspx_a0(DSPX_A0)
);
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
.ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low)
.ROM_SEL(ROM_SEL), // which SRAM unit to access
.MCU_OVR(MCU_OVR), // enable MCU mode (active low)
.MODE(MODE), // MCU(1) or SNES(0) ("bus phase")
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.MCU_ADDR(MCU_ADDR),
.ROM_ADDR0(ROM_ADDR0),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.use_msu(use_msu),
.msu_enable(msu_enable),
//BS-X
.use_bsx(use_bsx),
.bsx_regs(bsx_regs),
//SRTC
.srtc_enable(srtc_enable),
//uPD77C25
.dspx_enable(dspx_enable),
.dspx_a0(DSPX_A0)
);
wire SNES_READ_CYCLEw;
wire SNES_WRITE_CYCLEw;
wire MCU_READ_CYCLEw;
wire MCU_WRITE_CYCLEw;
data snes_data(.CLK(CLK2),
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.MCU_READ(MCU_READ),
.MCU_WRITE(MCU_WRITE),
.SNES_DATA(SNES_DATA),
.ROM_DATA(ROM_DATA),
.MODE(MODE),
.SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
.MCU_DATA_TO_MEM(MCU_DATA_TO_MEM),
.ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM),
.ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM),
.MCU_OVR(MCU_OVR),
.MCU_IN_DATA(MCU_IN_DATA),
.MCU_OUT_DATA(MCU_OUT_DATA),
.ROM_ADDR0(ROM_ADDR0),
.MSU_DATA_IN(MSU_SNES_DATA_IN),
.MSU_DATA_OUT(MSU_SNES_DATA_OUT),
.BSX_DATA_IN(BSX_SNES_DATA_IN),
.BSX_DATA_OUT(BSX_SNES_DATA_OUT),
.SRTC_DATA_IN(SRTC_SNES_DATA_IN),
.SRTC_DATA_OUT(SRTC_SNES_DATA_OUT),
.DSPX_DATA_IN(DSPX_SNES_DATA_IN),
.DSPX_DATA_OUT(DSPX_SNES_DATA_OUT),
.msu_enable(msu_enable),
.bsx_data_ovr(bsx_data_ovr),
.srtc_enable(srtc_enable),
.dspx_enable(dspx_enable)
);
data snes_data(
.CLK(CLK2),
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.MCU_READ(MCU_READ),
.MCU_WRITE(MCU_WRITE),
.SNES_DATA(SNES_DATA),
.ROM_DATA(ROM_DATA),
.MODE(MODE),
.SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
.MCU_DATA_TO_MEM(MCU_DATA_TO_MEM),
.ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM),
.ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM),
.MCU_OVR(MCU_OVR),
.MCU_IN_DATA(MCU_IN_DATA),
.MCU_OUT_DATA(MCU_OUT_DATA),
.ROM_ADDR0(ROM_ADDR0),
.MSU_DATA_IN(MSU_SNES_DATA_IN),
.MSU_DATA_OUT(MSU_SNES_DATA_OUT),
.BSX_DATA_IN(BSX_SNES_DATA_IN),
.BSX_DATA_OUT(BSX_SNES_DATA_OUT),
.SRTC_DATA_IN(SRTC_SNES_DATA_IN),
.SRTC_DATA_OUT(SRTC_SNES_DATA_OUT),
.DSPX_DATA_IN(DSPX_SNES_DATA_IN),
.DSPX_DATA_OUT(DSPX_SNES_DATA_OUT),
.msu_enable(msu_enable),
.bsx_data_ovr(bsx_data_ovr),
.srtc_enable(srtc_enable),
.dspx_enable(dspx_enable)
);
parameter MODE_SNES = 1'b0;
parameter MODE_MCU = 1'b1;
@ -484,7 +447,7 @@ parameter STATE_8 = 14'b00000100000000;
parameter STATE_9 = 14'b00001000000000;
parameter STATE_10 = 14'b00010000000000;
parameter STATE_11 = 14'b00100000000000;
parameter STATE_12 = 14'b01000000000000;
parameter STATE_12 = 14'b01000000000000;
parameter STATE_IDLE = 14'b10000000000000;
reg [13:0] STATE;
@ -523,7 +486,6 @@ assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX];
initial begin
CYCLE_RESET = 2'b0;
STATE = STATE_IDLE;
STATEIDX = 13;
ROM_WE_MASK = 1'b1;
@ -533,7 +495,7 @@ initial begin
MCU_READ_CYCLE = 1'b1;
MCU_WRITE_CYCLE = 1'b1;
MODE_ARRAY = 14'b0_000000_1111111;
ROM_WE_ARRAY[2'b00] = 14'b1_000000_0000000;
ROM_WE_ARRAY[2'b01] = 14'b1_000000_1111111;
ROM_WE_ARRAY[2'b10] = 14'b1_111111_0000000;
@ -543,25 +505,20 @@ initial begin
ROM_OE_ARRAY[2'b01] = 14'b1_111111_0000000;
ROM_OE_ARRAY[2'b10] = 14'b0_000000_1111111;
ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000;
SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
/* 13'b0001000000000 */
SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
// MCU_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // MCU write
SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read
ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write
ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read
/* 13'b0000100000000; */
ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write
ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read
// SRAM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 13'b0000000000001; // MCU read
end
end
// falling edge of SNES /RD or /WR marks the beginning of a new cycle
// SNES READ or WRITE always starts @posedge CLK !!
@ -570,83 +527,86 @@ end
// we have 24 internal cycles to work with. (CLKIN * 4)
always @(posedge CLK2) begin
CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
end
reg[7:0] STATECNT;
initial STATECNT = 0;
always @(posedge CLK2) begin
MCU_READ_CYCLE <= MCU_READ;
MCU_WRITE_CYCLE <= MCU_WRITE;
if (SNES_cycle_start) begin
SNES_READ_CYCLE <= SNES_READ;
SNES_WRITE_CYCLE <= SNES_WRITE;
STATE <= STATE_0;
STATEIDX <= 12;
STATECNT <= 0;
end else begin
STATECNT <= STATECNT + 1;
case (STATE)
STATE_0: begin
SNES_WRITE_CYCLE <= SNES_WRITE;
STATE <= STATE_1; STATEIDX <= 11;
end
STATE_1: begin
STATE <= STATE_2; STATEIDX <= 10;
end
STATE_2: begin
STATE <= STATE_3; STATEIDX <= 9;
end
STATE_3: begin
STATE <= STATE_4; STATEIDX <= 8;
end
STATE_4: begin
STATE <= STATE_5; STATEIDX <= 7;
end
STATE_5: begin
STATE <= STATE_6; STATEIDX <= 6;
end
STATE_6: begin
STATE <= STATE_7; STATEIDX <= 5;
end
STATE_7: begin
STATE <= STATE_8; STATEIDX <= 4;
end
STATE_8: begin
STATE <= STATE_9; STATEIDX <= 3;
end
STATE_9: begin
STATE <= STATE_10; STATEIDX <= 2;
end
STATE_10: begin
STATE <= STATE_11; STATEIDX <= 1;
end
STATE_11: begin
STATE <= STATE_12; STATEIDX <= 0;
end
STATE_12: begin
STATE <= STATE_IDLE; STATEIDX <= 13;
end
STATE_IDLE: begin
STATE <= STATE_IDLE; STATEIDX <= 13;
end
default: begin
STATE <= STATE_IDLE; STATEIDX <= 13;
end
endcase
end
MCU_READ_CYCLE <= MCU_READ;
MCU_WRITE_CYCLE <= MCU_WRITE;
if (SNES_cycle_start) begin
SNES_READ_CYCLE <= SNES_READ;
SNES_WRITE_CYCLE <= SNES_WRITE;
STATE <= STATE_0;
STATEIDX <= 12;
STATECNT <= 0;
end else begin
STATECNT <= STATECNT + 1;
case (STATE)
STATE_0: begin
SNES_WRITE_CYCLE <= SNES_WRITE;
STATE <= STATE_1; STATEIDX <= 11;
end
STATE_1: begin
STATE <= STATE_2; STATEIDX <= 10;
end
STATE_2: begin
STATE <= STATE_3; STATEIDX <= 9;
end
STATE_3: begin
STATE <= STATE_4; STATEIDX <= 8;
end
STATE_4: begin
STATE <= STATE_5; STATEIDX <= 7;
end
STATE_5: begin
STATE <= STATE_6; STATEIDX <= 6;
end
STATE_6: begin
STATE <= STATE_7; STATEIDX <= 5;
end
STATE_7: begin
STATE <= STATE_8; STATEIDX <= 4;
end
STATE_8: begin
STATE <= STATE_9; STATEIDX <= 3;
end
STATE_9: begin
STATE <= STATE_10; STATEIDX <= 2;
end
STATE_10: begin
STATE <= STATE_11; STATEIDX <= 1;
end
STATE_11: begin
STATE <= STATE_12; STATEIDX <= 0;
end
STATE_12: begin
STATE <= STATE_IDLE; STATEIDX <= 13;
end
STATE_IDLE: begin
STATE <= STATE_IDLE; STATEIDX <= 13;
end
default: begin
STATE <= STATE_IDLE; STATEIDX <= 13;
end
endcase
end
end
// When in MCU mode, enable SRAM_WE according to MCU programming
// else enable SRAM_WE according to state&cycle
assign ROM_WE = !MCU_OVR ? MCU_WRITE
: ((!IS_FLASHWR & !IS_WRITABLE & !MODE) | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
assign ROM_WE = !MCU_OVR
?MCU_WRITE
:((!IS_FLASHWR & !IS_WRITABLE & !MODE)
| ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
// When in MCU mode, enable SRAM_OE whenever not writing
// else enable SRAM_OE according to state&cycle
assign ROM_OE = !MCU_OVR ? MCU_READ
: ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
assign ROM_OE = !MCU_OVR
?MCU_READ
:ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
@ -663,8 +623,13 @@ assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
assign SNES_DATABUS_OE = dspx_enable ? 1'b0 :
msu_enable ? (SNES_READ & SNES_WRITE) :
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
srtc_enable ? (SNES_READ & SNES_WRITE) : ((IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR) | (SNES_READ & SNES_WRITE));
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
srtc_enable ? (SNES_READ & SNES_WRITE) :
((IS_ROM & SNES_CS)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];

687
verilog/sd2snes/mcu_cmd.v
View File

@ -19,86 +19,86 @@
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [3:0] mcu_mapper,
output [3:0] mcu_sram_size,
output mcu_read,
output mcu_write,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [3:0] mapper,
input endmessage,
input startmessage,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [11:0] SD_DMA_PARTIAL_START,
output [11:0] SD_DMA_PARTIAL_END,
// DAC
output [10:0] dac_addr_out,
// output [7:0] dac_volume_out,
// output dac_volume_latch_out,
input DAC_STATUS,
output dac_play_out,
output dac_reset_out,
// MSU data
output [13:0] msu_addr_out,
input [6:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// BS-X
output [7:0] bsx_regs_reset_out,
output [7:0] bsx_regs_set_out,
output bsx_regs_reset_we,
// generic RTC
output [55:0] rtc_data_out,
output rtc_pgm_we,
// S-RTC
output srtc_reset,
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [3:0] mcu_mapper,
output [3:0] mcu_sram_size,
output mcu_read,
output mcu_write,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [3:0] mapper,
input endmessage,
input startmessage,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [9:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// SNES sync/clk
input snes_sysclk
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [11:0] SD_DMA_PARTIAL_START,
output [11:0] SD_DMA_PARTIAL_END,
// DAC
output [10:0] dac_addr_out,
// output [7:0] dac_volume_out,
// output dac_volume_latch_out,
input DAC_STATUS,
output dac_play_out,
output dac_reset_out,
// MSU data
output [13:0] msu_addr_out,
input [6:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// BS-X
output [7:0] bsx_regs_reset_out,
output [7:0] bsx_regs_set_out,
output bsx_regs_reset_we,
// generic RTC
output [55:0] rtc_data_out,
output rtc_pgm_we,
// S-RTC
output srtc_reset,
// uPD77C25
output reg [23:0] dspx_pgm_data_out,
output reg [10:0] dspx_pgm_addr_out,
output reg dspx_pgm_we_out,
output reg [15:0] dspx_dat_data_out,
output reg [9:0] dspx_dat_addr_out,
output reg dspx_dat_we_out,
output reg dspx_reset_out,
// SNES sync/clk
input snes_sysclk
);
initial begin
initial begin
dspx_pgm_addr_out = 11'b00000000000;
dspx_dat_addr_out = 9'b000000000;
dspx_reset_out = 1'b1;
@ -107,10 +107,10 @@ end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
);
reg [3:0] MAPPER_BUF;
@ -153,9 +153,9 @@ reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [6:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
@ -181,188 +181,188 @@ reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
DAC_VOL_OUT_BUF = 0;
DAC_VOL_LATCH_BUF = 0;
spi_dma_nextaddr_r = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
DAC_VOL_OUT_BUF = 0;
DAC_VOL_LATCH_BUF = 0;
spi_dma_nextaddr_r = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
end
// command interpretation
always @(posedge clk) begin
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[3:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= cmd_data[1:0];
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h0x:
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
8'h1x:
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[3:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= cmd_data[1:0];
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h0x:
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
8'h2x:
end
2'b10: begin
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
// 8'h5x:
// case (spi_byte_cnt)
// 32'h2:
// DAC_VOL_OUT_BUF <= param_data;
// 32'h3:
// DAC_VOL_LATCH_BUF <= 1'b1;
// 32'h4:
// DAC_VOL_LATCH_BUF <= 1'b0;
// endcase
8'h6x:
case (spi_byte_cnt)
32'h2:
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4:
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
DAC_PLAY_OUT_BUF <= 1'b0;
8'he2: // resume DAC
DAC_PLAY_OUT_BUF <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
DAC_RESET_OUT_BUF <= 1'b1;
32'h3:
DAC_RESET_OUT_BUF <= 1'b0;
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'he5:
case (spi_byte_cnt)
32'h2:
rtc_data_out_buf[55:48] <= param_data;
32'h3:
rtc_data_out_buf[47:40] <= param_data;
32'h4:
rtc_data_out_buf[39:32] <= param_data;
32'h5:
rtc_data_out_buf[31:24] <= param_data;
32'h6:
rtc_data_out_buf[23:16] <= param_data;
32'h7:
rtc_data_out_buf[15:8] <= param_data;
32'h8: begin
rtc_data_out_buf[7:0] <= param_data;
rtc_pgm_we_buf <= 1'b1;
end
32'h9:
rtc_pgm_we_buf <= 1'b0;
endcase
8'he6:
case (spi_byte_cnt)
32'h2: begin
bsx_regs_set_out_buf <= param_data[7:0];
end
32'h3: begin
bsx_regs_reset_out_buf <= param_data[7:0];
bsx_regs_reset_we_buf <= 1'b1;
end
32'h4:
bsx_regs_reset_we_buf <= 1'b0;
endcase
8'he7:
case (spi_byte_cnt)
32'h2: begin
srtc_reset_buf <= 1'b1;
end
32'h3: begin
srtc_reset_buf <= 1'b0;
end
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
// 8'h5x:
// case (spi_byte_cnt)
// 32'h2:
// DAC_VOL_OUT_BUF <= param_data;
// 32'h3:
// DAC_VOL_LATCH_BUF <= 1'b1;
// 32'h4:
// DAC_VOL_LATCH_BUF <= 1'b0;
// endcase
8'h6x:
case (spi_byte_cnt)
32'h2:
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4:
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
DAC_PLAY_OUT_BUF <= 1'b0;
8'he2: // resume DAC
DAC_PLAY_OUT_BUF <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
DAC_RESET_OUT_BUF <= 1'b1;
32'h3:
DAC_RESET_OUT_BUF <= 1'b0;
endcase
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'he5:
case (spi_byte_cnt)
32'h2:
rtc_data_out_buf[55:48] <= param_data;
32'h3:
rtc_data_out_buf[47:40] <= param_data;
32'h4:
rtc_data_out_buf[39:32] <= param_data;
32'h5:
rtc_data_out_buf[31:24] <= param_data;
32'h6:
rtc_data_out_buf[23:16] <= param_data;
32'h7:
rtc_data_out_buf[15:8] <= param_data;
32'h8: begin
rtc_data_out_buf[7:0] <= param_data;
rtc_pgm_we_buf <= 1'b1;
end
32'h9:
rtc_pgm_we_buf <= 1'b0;
endcase
8'he6:
case (spi_byte_cnt)
32'h2: begin
bsx_regs_set_out_buf <= param_data[7:0];
end
32'h3: begin
bsx_regs_reset_out_buf <= param_data[7:0];
bsx_regs_reset_we_buf <= 1'b1;
end
32'h4:
bsx_regs_reset_we_buf <= 1'b0;
endcase
8'he7:
case (spi_byte_cnt)
32'h2: begin
srtc_reset_buf <= 1'b1;
end
32'h3: begin
srtc_reset_buf <= 1'b0;
end
endcase
8'he8: begin// reset DSPx PGM+DAT address
case (spi_byte_cnt)
32'h2: begin
@ -396,101 +396,124 @@ always @(posedge clk) begin
dspx_reset_out <= 1'b1;
8'hec: // release DSPx reset
dspx_reset_out <= 1'b0;
endcase
end
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[3]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
endcase
end
if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt > (32'h1+cmd_data[4])))
)
begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (spi_bit_cnt == 3'h7)
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:4] == 4'h8)
MCU_DATA_IN_BUF <= mcu_data_in;
else
MCU_DATA_IN_BUF <= cmd_data;
if (spi_bit_cnt == 3'h7) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[6], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {2'b0, MSU_STATUSr[5:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:4] == 4'h8)
MCU_DATA_IN_BUF <= mcu_data_in;
else
MCU_DATA_IN_BUF <= cmd_data;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
if (spi_bit_cnt == 3'h0)
mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b1};
else
mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b0};
if (spi_bit_cnt == 3'h0)
mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b1};
else
mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b0};
end
// r/w pulse
always @(posedge clk) begin
if ((spi_bit_cnt == 3'h1 || spi_bit_cnt == 3'h2 || spi_bit_cnt == 3'h3) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1))
MCU_WRITE_BUF <= 1'b0;
else
MCU_WRITE_BUF <= 1'b1;
if ((spi_bit_cnt == 3'h1
|| spi_bit_cnt == 3'h2
|| spi_bit_cnt == 3'h3
)
& (cmd_data[7:4] == 4'h9)
& (spi_byte_cnt > 32'h1)
)
MCU_WRITE_BUF <= 1'b0;
else
MCU_WRITE_BUF <= 1'b1;
// Read pulse is two spi cycles to ensure that the value
// Read pulse is 3 spi cycles to ensure that the value
// is ready in the 2nd cycle in MCU master mode
if ((spi_bit_cnt == 3'h5 || spi_bit_cnt == 3'h6 || spi_bit_cnt == 3'h7) & (cmd_data[7:4] == 4'h8) & (spi_byte_cnt > 32'h0))
MCU_READ_BUF <= 1'b0;
else
MCU_READ_BUF <= 1'b1;
if ((spi_bit_cnt == 3'h5
|| spi_bit_cnt == 3'h6
|| spi_bit_cnt == 3'h7
)
& (cmd_data[7:4] == 4'h8)
& (spi_byte_cnt > 32'h0)
)
MCU_READ_BUF <= 1'b0;
else
MCU_READ_BUF <= 1'b1;
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_read = MCU_READ_BUF;
assign mcu_write = SD_DMA_STATUS ? (SD_DMA_TGTr == 2'b00 ? SD_DMA_SRAM_WE : 1'b1) : MCU_WRITE_BUF;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
?SD_DMA_SRAM_WE
:1'b1
)
: MCU_WRITE_BUF;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
@ -518,5 +541,5 @@ assign mcu_mapper = MAPPER_BUF;
assign mcu_sram_size = SRAM_SIZE_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
endmodule

157
verilog/sd2snes/msu.v
View File

@ -19,27 +19,27 @@
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe,
input reg_we,
output [6:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write
);
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe,
input reg_we,
output [6:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
@ -52,7 +52,8 @@ wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [1:0] msu_address_ext_write_sreg;
always @(posedge clkin) msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01);
reg [5:0] reg_oe_sreg;
@ -85,25 +86,29 @@ reg [1:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r <= 1'b1;
data_busy_r <= 1'b1;
audio_busy_r <= 1'b1;
data_busy_r <= 1'b1;
end
assign status_out = {msu_address_r[13],
audio_start_r, data_start_r, volume_start_r, audio_ctrl_r, ctrl_start_r};
assign status_out = {msu_address_r[13], // 6
audio_start_r, // 5
data_start_r, // 4
volume_start_r, // 3
audio_ctrl_r, // 2:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)); // Bus [7 : 0]
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
// reg [7:0] data_out_r;
reg [7:0] data_in_r;
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
@ -111,14 +116,14 @@ always @(posedge clkin) data_in_r <= reg_data_in;
always @(posedge clkin) begin
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
3'h1: data_out_r <= msu_data_r;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001};
3'h1: data_out_r <= msu_data_r;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
@ -126,44 +131,44 @@ always @(posedge clkin) begin
if(reg_we_rising && enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[1:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[1:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
// volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
// volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
@ -174,7 +179,7 @@ always @(posedge clkin) begin
msu_address_r <= msu_address_ext;
else if(enable && reg_addr == 3'h1 && reg_oe_falling) begin
msu_address_r <= msu_address_r + 1;
msu_data_r <= msu_data;
msu_data_r <= msu_data;
end
end

597
verilog/sd2snes/rtc.v
View File

@ -19,13 +19,13 @@
//
//////////////////////////////////////////////////////////////////////////////////
module rtc (
input clkin,
input pgm_we,
input [59:0] rtc_data_in,
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
input clkin,
input pgm_we,
input [59:0] rtc_data_in,
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
reg [59:0] rtc_data_r;
reg [59:0] rtc_data_out_r;
@ -46,7 +46,7 @@ always @(posedge clkin) begin
end
assign rtc_data = rtc_data_out_r;
reg [21:0] rtc_state;
reg [21:0] next_state;
reg carry;
@ -64,29 +64,29 @@ reg [6:0] dow_year100;
reg [15:0] dow_tmp;
parameter [21:0]
STATE_SEC1 = 22'b0000000000000000000001,
STATE_SEC10 = 22'b0000000000000000000010,
STATE_MIN1 = 22'b0000000000000000000100,
STATE_MIN10 = 22'b0000000000000000001000,
STATE_HOUR1 = 22'b0000000000000000010000,
STATE_HOUR10 = 22'b0000000000000000100000,
STATE_DAY1 = 22'b0000000000000001000000,
STATE_DAY10 = 22'b0000000000000010000000,
STATE_MON1 = 22'b0000000000000100000000,
STATE_MON10 = 22'b0000000000001000000000,
STATE_YEAR1 = 22'b0000000000010000000000,
STATE_YEAR10 = 22'b0000000000100000000000,
STATE_YEAR100 = 22'b0000000001000000000000,
STATE_YEAR1000 = 22'b0000000010000000000000,
STATE_DOW0 = 22'b0000000100000000000000,
STATE_DOW1 = 22'b0000001000000000000000,
STATE_DOW2 = 22'b0000010000000000000000,
STATE_DOW3 = 22'b0000100000000000000000,
STATE_DOW4 = 22'b0001000000000000000000,
STATE_DOW5 = 22'b0010000000000000000000,
STATE_LATCH = 22'b0100000000000000000000,
STATE_IDLE = 22'b1000000000000000000000;
STATE_SEC1 = 22'b0000000000000000000001,
STATE_SEC10 = 22'b0000000000000000000010,
STATE_MIN1 = 22'b0000000000000000000100,
STATE_MIN10 = 22'b0000000000000000001000,
STATE_HOUR1 = 22'b0000000000000000010000,
STATE_HOUR10 = 22'b0000000000000000100000,
STATE_DAY1 = 22'b0000000000000001000000,
STATE_DAY10 = 22'b0000000000000010000000,
STATE_MON1 = 22'b0000000000000100000000,
STATE_MON10 = 22'b0000000000001000000000,
STATE_YEAR1 = 22'b0000000000010000000000,
STATE_YEAR10 = 22'b0000000000100000000000,
STATE_YEAR100 = 22'b0000000001000000000000,
STATE_YEAR1000 = 22'b0000000010000000000000,
STATE_DOW0 = 22'b0000000100000000000000,
STATE_DOW1 = 22'b0000001000000000000000,
STATE_DOW2 = 22'b0000010000000000000000,
STATE_DOW3 = 22'b0000100000000000000000,
STATE_DOW4 = 22'b0001000000000000000000,
STATE_DOW5 = 22'b0010000000000000000000,
STATE_LATCH = 22'b0100000000000000000000,
STATE_IDLE = 22'b1000000000000000000000;
initial begin
rtc_state = STATE_IDLE;
next_state = STATE_IDLE;
@ -101,7 +101,7 @@ initial begin
dom1[8] <= 0; dom10[8] <= 3;
dom1[9] <= 1; dom10[9] <= 3;
dom1[10] <= 0; dom10[10] <= 3;
dom1[11] <= 1; dom10[11] <= 3;
dom1[11] <= 1; dom10[11] <= 3;
month <= 0;
rtc_data_r <= 60'h220110301000000;
tick_cnt <= 0;
@ -110,60 +110,59 @@ end
wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
always @(posedge clkin) begin
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
case (rtc_state)
STATE_SEC1:
rtc_state <= STATE_SEC10;
STATE_SEC10:
rtc_state <= STATE_MIN1;
STATE_MIN1:
rtc_state <= STATE_MIN10;
STATE_MIN10:
rtc_state <= STATE_HOUR1;
STATE_HOUR1:
rtc_state <= STATE_HOUR10;
STATE_HOUR10:
rtc_state <= STATE_DAY1;
STATE_DAY1:
rtc_state <= STATE_DAY10;
STATE_DAY10:
rtc_state <= STATE_MON1;
STATE_MON1:
rtc_state <= STATE_MON10;
STATE_MON10:
rtc_state <= STATE_YEAR1;
STATE_YEAR1:
rtc_state <= STATE_YEAR10;
STATE_YEAR10:
rtc_state <= STATE_YEAR100;
STATE_YEAR100:
rtc_state <= STATE_YEAR1000;
STATE_YEAR1000:
rtc_state <= STATE_DOW0;
STATE_DOW0:
rtc_state <= STATE_DOW1;
STATE_DOW1:
rtc_state <= STATE_DOW2;
STATE_DOW2:
rtc_state <= STATE_DOW3;
STATE_DOW3:
rtc_state <= STATE_DOW4;
STATE_DOW4:
if(dow_tmp > 13)
rtc_state <= STATE_DOW4;
else
rtc_state <= STATE_DOW5;
STATE_DOW5:
rtc_state <= STATE_LATCH;
STATE_LATCH:
rtc_state <= STATE_IDLE;
default:
rtc_state <= STATE_IDLE;
endcase
end
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
case (rtc_state)
STATE_SEC1:
rtc_state <= STATE_SEC10;
STATE_SEC10:
rtc_state <= STATE_MIN1;
STATE_MIN1:
rtc_state <= STATE_MIN10;
STATE_MIN10:
rtc_state <= STATE_HOUR1;
STATE_HOUR1:
rtc_state <= STATE_HOUR10;
STATE_HOUR10:
rtc_state <= STATE_DAY1;
STATE_DAY1:
rtc_state <= STATE_DAY10;
STATE_DAY10:
rtc_state <= STATE_MON1;
STATE_MON1:
rtc_state <= STATE_MON10;
STATE_MON10:
rtc_state <= STATE_YEAR1;
STATE_YEAR1:
rtc_state <= STATE_YEAR10;
STATE_YEAR10:
rtc_state <= STATE_YEAR100;
STATE_YEAR100:
rtc_state <= STATE_YEAR1000;
STATE_YEAR1000:
rtc_state <= STATE_DOW0;
STATE_DOW0:
rtc_state <= STATE_DOW1;
STATE_DOW1:
rtc_state <= STATE_DOW2;
STATE_DOW2:
rtc_state <= STATE_DOW3;
STATE_DOW3:
rtc_state <= STATE_DOW4;
STATE_DOW4:
if(dow_tmp > 13)
rtc_state <= STATE_DOW4;
else
rtc_state <= STATE_DOW5;
STATE_DOW5:
rtc_state <= STATE_LATCH;
STATE_LATCH:
rtc_state <= STATE_IDLE;
default:
rtc_state <= STATE_IDLE;
endcase
end
end
always @(posedge clkin) begin
@ -173,216 +172,222 @@ always @(posedge clkin) begin
rtc_data_r <= rtc_data_in1;
end else begin
case(rtc_state)
STATE_SEC1: begin
if(rtc_data_r[3:0] == 9) begin
rtc_data_r[3:0] <= 0;
carry <= 1;
end else begin
rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
carry <= 0;
end
end
STATE_SEC10: begin
if(carry) begin
if(rtc_data_r[7:4] == 5) begin
rtc_data_r[7:4] <= 0;
carry <= 1;
end else begin
rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
carry <= 0;
end
end
end
STATE_MIN1: begin
if(carry) begin
if(rtc_data_r[11:8] == 9) begin
rtc_data_r[11:8] <= 0;
carry <= 1;
end else begin
rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
carry <= 0;
end
end
end
STATE_MIN10: begin
if(carry) begin
if(rtc_data_r[15:12] == 5) begin
rtc_data_r[15:12] <= 0;
carry <= 1;
end else begin
rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
carry <= 0;
end
end
end
STATE_HOUR1: begin
if(carry) begin
if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else if (rtc_data_r[19:16] == 9) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else begin
rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
carry <= 0;
end
end
end
STATE_HOUR10: begin
if(carry) begin
if(rtc_data_r[23:20] == 2) begin
rtc_data_r[23:20] <= 0;
carry <= 1;
end else begin
rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
carry <= 0;
end
end
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month] && rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else begin
rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
carry <= 0;
end
end
end
STATE_DAY10: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]) begin
rtc_data_r[31:28] <= 0;
rtc_data_r[27:24] <= 1;
carry <= 1;
end else begin
rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
carry <= 0;
end
end
end
STATE_MON1: begin
if(carry) begin
if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
rtc_data_r[35:32] <= 1;
carry <= 1;
end else if (rtc_data_r[35:32] == 9) begin
rtc_data_r[35:32] <= 0;
carry <= 1;
end else begin
rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
carry <= 0;
end
end
end
STATE_MON10: begin
if(carry) begin
if(rtc_data_r[39:36] == 1) begin
rtc_data_r[39:36] <= 0;
carry <= 1;
end else begin
rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
carry <= 0;
end
end
end
STATE_YEAR1: begin
month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
if(carry) begin
if(rtc_data_r[43:40] == 9) begin
rtc_data_r[43:40] <= 0;
carry <= 1;
end else begin
rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
carry <= 0;
end
end
end
STATE_YEAR10: begin
if(carry) begin
if(rtc_data_r[47:44] == 9) begin
rtc_data_r[47:44] <= 0;
carry <= 1;
end else begin
rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
carry <= 0;
end
end
end
STATE_YEAR100: begin
if(carry) begin
if(rtc_data_r[51:48] == 9) begin
rtc_data_r[51:48] <= 0;
carry <= 1;
end else begin
rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
carry <= 0;
end
end
end
STATE_YEAR1000: begin
if(carry) begin
if(rtc_data_r[55:52] == 9) begin
rtc_data_r[55:52] <= 0;
carry <= 1;
end else begin
rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
carry <= 0;
end
end
end
STATE_DOW0: begin
dow_year1 <= rtc_data_r[43:40]
+(rtc_data_r[47:44] << 1) + (rtc_data_r[47:44] << 3);
dow_year100 <= rtc_data_r[51:48]
+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24] + (rtc_data_r[31:28] << 1) + (rtc_data_r[31:28] << 3);
end
STATE_DOW1: begin
year <= dow_year1[1:0];
if(dow_month <= 2) begin
dow_month <= dow_month + 10;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6) - 1;
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin
dow_year1 <= 99;
dow_year100 <= dow_year100 - 1;
end
end else begin
dow_month <= dow_month - 2;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6);
end
end
STATE_DOW2: begin
dow_tmp <= (83 * dow_month);
end
STATE_DOW3: begin
dow_tmp <= (dow_tmp >> 5)
+ dow_day
+ dow_year
+ (dow_year >> 2)
- (dow_year100)
+ (dow_year100 >> 2);
end
STATE_DOW4: begin
dow_tmp <= dow_tmp - 7;
end
STATE_DOW5: begin
rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
end
STATE_LATCH: begin
rtc_data_out_r <= rtc_data_r;
end
endcase
STATE_SEC1: begin
if(rtc_data_r[3:0] == 9) begin
rtc_data_r[3:0] <= 0;
carry <= 1;
end else begin
rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
carry <= 0;
end
end
STATE_SEC10: begin
if(carry) begin
if(rtc_data_r[7:4] == 5) begin
rtc_data_r[7:4] <= 0;
carry <= 1;
end else begin
rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
carry <= 0;
end
end
end
STATE_MIN1: begin
if(carry) begin
if(rtc_data_r[11:8] == 9) begin
rtc_data_r[11:8] <= 0;
carry <= 1;
end else begin
rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
carry <= 0;
end
end
end
STATE_MIN10: begin
if(carry) begin
if(rtc_data_r[15:12] == 5) begin
rtc_data_r[15:12] <= 0;
carry <= 1;
end else begin
rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
carry <= 0;
end
end
end
STATE_HOUR1: begin
if(carry) begin
if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else if (rtc_data_r[19:16] == 9) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else begin
rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
carry <= 0;
end
end
end
STATE_HOUR10: begin
if(carry) begin
if(rtc_data_r[23:20] == 2) begin
rtc_data_r[23:20] <= 0;
carry <= 1;
end else begin
rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
carry <= 0;
end
end
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]
&& rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else begin
rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
carry <= 0;
end
end
end
STATE_DAY10: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]) begin
rtc_data_r[31:28] <= 0;
rtc_data_r[27:24] <= 1;
carry <= 1;
end else begin
rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
carry <= 0;
end
end
end
STATE_MON1: begin
if(carry) begin
if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
rtc_data_r[35:32] <= 1;
carry <= 1;
end else if (rtc_data_r[35:32] == 9) begin
rtc_data_r[35:32] <= 0;
carry <= 1;
end else begin
rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
carry <= 0;
end
end
end
STATE_MON10: begin
if(carry) begin
if(rtc_data_r[39:36] == 1) begin
rtc_data_r[39:36] <= 0;
carry <= 1;
end else begin
rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
carry <= 0;
end
end
end
STATE_YEAR1: begin
month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
if(carry) begin
if(rtc_data_r[43:40] == 9) begin
rtc_data_r[43:40] <= 0;
carry <= 1;
end else begin
rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
carry <= 0;
end
end
end
STATE_YEAR10: begin
if(carry) begin
if(rtc_data_r[47:44] == 9) begin
rtc_data_r[47:44] <= 0;
carry <= 1;
end else begin
rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
carry <= 0;
end
end
end
STATE_YEAR100: begin
if(carry) begin
if(rtc_data_r[51:48] == 9) begin
rtc_data_r[51:48] <= 0;
carry <= 1;
end else begin
rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
carry <= 0;
end
end
end
STATE_YEAR1000: begin
if(carry) begin
if(rtc_data_r[55:52] == 9) begin
rtc_data_r[55:52] <= 0;
carry <= 1;
end else begin
rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
carry <= 0;
end
end
end
STATE_DOW0: begin
dow_year1 <= rtc_data_r[43:40]
+(rtc_data_r[47:44] << 1) + (rtc_data_r[47:44] << 3);
dow_year100 <= rtc_data_r[51:48]
+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24]
+ (rtc_data_r[31:28] << 1)
+ (rtc_data_r[31:28] << 3);
end
STATE_DOW1: begin
year <= dow_year1[1:0];
if(dow_month <= 2) begin
dow_month <= dow_month + 10;
dow_year <= dow_year1
+ (dow_year100 << 2)
+ (dow_year100 << 5)
+ (dow_year100 << 6) - 1;
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin
dow_year1 <= 99;
dow_year100 <= dow_year100 - 1;
end
end else begin
dow_month <= dow_month - 2;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6);
end
end
STATE_DOW2: begin
dow_tmp <= (83 * dow_month);
end
STATE_DOW3: begin
dow_tmp <= (dow_tmp >> 5)
+ dow_day
+ dow_year
+ (dow_year >> 2)
- (dow_year100)
+ (dow_year100 >> 2);
end
STATE_DOW4: begin
dow_tmp <= dow_tmp - 7;
end
STATE_DOW5: begin
rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
end
STATE_LATCH: begin
rtc_data_out_r <= rtc_data_r;
end
endcase
end
end

10
verilog/sd2snes/sd2snes.xise
View File

@ -297,8 +297,8 @@
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
@ -327,7 +327,7 @@
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@ -381,8 +381,8 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>

56
verilog/sd2snes/sd_dma.v
View File

@ -19,19 +19,19 @@
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
input SD_DMA_TGT,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
);
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
input SD_DMA_TGT,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
@ -78,9 +78,9 @@ assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ;
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
@ -91,11 +91,11 @@ end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
@ -110,19 +110,19 @@ always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_WEr <= 1'b1;
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1:
SD_DMA_SRAM_WEr <= 1'b1;
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1:
SD_DMA_NEXTADDRr <= 1'b0;
// 3'h2:
// 3'h2:
3'h3:
if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
// 3'h5:
// 3'h6:
// 3'h7:
endcase
end

101
verilog/sd2snes/spi.v
View File

@ -19,25 +19,23 @@
//
//////////////////////////////////////////////////////////////////////////////////
module spi(input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
// SD "DMA" extension
/*input sd_dma_sck,
input sd_dma_ovr*/);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
@ -71,40 +69,41 @@ assign bit_cnt = bitcnt;
always @(posedge clk)
begin
if(~SSEL_active) begin
bitcnt <= 3'b000;
end
else if(SCK_risingedge) begin
bitcnt <= bitcnt + 3'b001;
// shift received data into the register
byte_data_received <= {byte_data_received[6:0], MOSI_data};
end
if(~SSEL_active) begin
bitcnt <= 3'b000;
end
else if(SCK_risingedge) begin
bitcnt <= bitcnt + 3'b001;
// shift received data into the register
byte_data_received <= {byte_data_received[6:0], MOSI_data};
end
end
always @(posedge clk) byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
always @(posedge clk)
byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);
always @(posedge clk) begin
if(~SSEL_active)
byte_cnt_r <= 16'h0000;
else if(byte_received) begin
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
if(~SSEL_active)
byte_cnt_r <= 16'h0000;
else if(byte_received) begin
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
end
reg [7:0] byte_data_sent;
always @(posedge clk) begin
if(SSEL_active) begin
if(SSEL_startmessage)
byte_data_sent <= 8'h5A; // dummy byte
else
if(SCK_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= input_data; // after that, we send whatever we get
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
end
if(SSEL_active) begin
if(SSEL_startmessage)
byte_data_sent <= 8'h5A; // dummy byte
else
if(SCK_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= input_data; // after that, we send whatever we get
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
end
end
assign MISO = SSEL_active ? byte_data_sent[7] : 1'bZ; // send MSB first
@ -124,18 +123,18 @@ always @(posedge clk) param_ready_r2 = byte_received && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock (why did I do this again...)
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule

199
verilog/sd2snes/srtc.v
View File

@ -19,19 +19,19 @@
//
//////////////////////////////////////////////////////////////////////////////////
module srtc(
input clkin,
input [4:0] reg_addr,
input addr_in,
input [7:0] data_in,
output [7:0] data_out,
input [59:0] rtc_data_in,
output [59:0] rtc_data_out,
input reg_we,
input reg_oe,
input enable,
output rtc_we,
input reset
);
input clkin,
input [4:0] reg_addr,
input addr_in,
input [7:0] data_in,
output [7:0] data_out,
input [59:0] rtc_data_in,
output [59:0] rtc_data_out,
input reg_we,
input reg_oe,
input enable,
output rtc_we,
input reset
);
reg rtc_dirty_r;
assign rtc_dirty = rtc_dirty_r;
@ -80,18 +80,17 @@ end
always @(posedge clkin) begin
if(reset_rising) begin
mode_r <= SRTC_READ;
rtc_ptr <= 4'hf;
rtc_ptr <= 4'hf;
end else if(mode_r == SRTC_WRITE2) begin
we_countdown_r <= we_countdown_r - 1;
if (we_countdown_r == 3'b000) begin
mode_r <= SRTC_WRITE;
rtc_we_r <= 0;
end
mode_r <= SRTC_WRITE;
rtc_we_r <= 0;
end
end else if(reg_we_rising && enable) begin
case (addr_in)
// 1'b0: // data register is read only
1'b1: // control register
// 1'b0: // data register is read only
1'b1: // control register
case (data_in[3:0])
4'hd: begin
mode_r <= SRTC_READ;
@ -100,86 +99,92 @@ always @(posedge clkin) begin
4'he: begin
mode_r <= SRTC_COMMAND;
end
4'hf: begin
end
default: begin
if(mode_r == SRTC_COMMAND) begin
case (data_in[3:0])
4'h0: begin
mode_r <= SRTC_WRITE;
rtc_data_out_r <= rtc_data_in;
rtc_ptr <= 4'h0;
end
4'h4: begin
mode_r <= SRTC_IDLE;
rtc_ptr <= 4'hf;
end
default:
mode_r <= SRTC_IDLE;
endcase
end else if(mode_r == SRTC_WRITE) begin
4'hf: begin
end
default: begin
if(mode_r == SRTC_COMMAND) begin
case (data_in[3:0])
4'h0: begin
mode_r <= SRTC_WRITE;
rtc_data_out_r <= rtc_data_in;
rtc_ptr <= 4'h0;
end
4'h4: begin
mode_r <= SRTC_IDLE;
rtc_ptr <= 4'hf;
end
default:
mode_r <= SRTC_IDLE;
endcase
end else if(mode_r == SRTC_WRITE) begin
rtc_ptr <= rtc_ptr + 1;
case(rtc_ptr)
0: rtc_data_out_r[3:0] <= data_in[3:0];
1: rtc_data_out_r[7:4] <= data_in[3:0];
2: rtc_data_out_r[11:8] <= data_in[3:0];
3: rtc_data_out_r[15:12] <= data_in[3:0];
4: rtc_data_out_r[19:16] <= data_in[3:0];
5: rtc_data_out_r[23:20] <= data_in[3:0];
6: rtc_data_out_r[27:24] <= data_in[3:0];
7: rtc_data_out_r[31:28] <= data_in[3:0];
8: begin
rtc_data_out_r[35:32] <= data_in[3:0] < 10 ? data_in[3:0]
: data_in[3:0] - 10;
rtc_data_out_r[39:36] <= data_in[3:0] < 10 ? 0 : 1;
end
9: rtc_data_out_r[43:40] <= data_in[3:0];
10: rtc_data_out_r[47:44] <= data_in[3:0];
11: begin
rtc_data_out_r[51:48] <= data_in[3:0] < 10 ? data_in[3:0]
: data_in[3:0] - 10;
rtc_data_out_r[55:52] <= data_in[3:0] < 10 ? 1 : 2;
end
default:
rtc_dirty_r <= 1;
endcase
mode_r <= SRTC_WRITE2;
we_countdown_r <= 5;
rtc_we_r <= 1;
end
end
case(rtc_ptr)
0: rtc_data_out_r[3:0] <= data_in[3:0];
1: rtc_data_out_r[7:4] <= data_in[3:0];
2: rtc_data_out_r[11:8] <= data_in[3:0];
3: rtc_data_out_r[15:12] <= data_in[3:0];
4: rtc_data_out_r[19:16] <= data_in[3:0];
5: rtc_data_out_r[23:20] <= data_in[3:0];
6: rtc_data_out_r[27:24] <= data_in[3:0];
7: rtc_data_out_r[31:28] <= data_in[3:0];
8: begin
rtc_data_out_r[35:32] <= (data_in[3:0] < 10)
? data_in[3:0]
: data_in[3:0] - 10;
rtc_data_out_r[39:36] <= data_in[3:0] < 10 ? 0 : 1;
end
9: rtc_data_out_r[43:40] <= data_in[3:0];
10: rtc_data_out_r[47:44] <= data_in[3:0];
11: begin
rtc_data_out_r[51:48] <= (data_in[3:0] < 10)
? data_in[3:0]
: data_in[3:0] - 10;
rtc_data_out_r[55:52] <= data_in[3:0] < 10 ? 1 : 2;
end
default:
rtc_dirty_r <= 1;
endcase
mode_r <= SRTC_WRITE2;
we_countdown_r <= 5;
rtc_we_r <= 1;
end
end
endcase
endcase
endcase
end else if(reg_oe_falling && enable) begin
case (addr_in)
1'b0: // read data register
if(mode_r == SRTC_READ) begin
case(rtc_ptr)
0: data_out_r <= rtc_data_r[3:0];
1: data_out_r <= rtc_data_r[7:4];
2: data_out_r <= rtc_data_r[11:8];
3: data_out_r <= rtc_data_r[15:12];
4: data_out_r <= rtc_data_r[19:16];
5: data_out_r <= rtc_data_r[23:20];
6: data_out_r <= rtc_data_r[27:24];
7: data_out_r <= rtc_data_r[31:28];
8: data_out_r <= rtc_data_r[35:32] + (rtc_data_r[39:36] << 1) + (rtc_data_r[39:36] << 3);
9: data_out_r <= rtc_data_r[43:40];
10: data_out_r <= rtc_data_r[47:44];
11: data_out_r <= rtc_data_r[51:48] + (rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3) - 10;
12: data_out_r <= rtc_data_r[59:56];
15: begin
rtc_data_r <= rtc_data_in;
data_out_r <= 8'h0f;
end
default: data_out_r <= 8'h0f;
endcase
rtc_ptr <= rtc_ptr == 13 ? 15 : rtc_ptr + 1;
end else begin
data_out_r <= 8'h00;
end
// 1'b1: // control register is write only
endcase
case (addr_in)
1'b0: // read data register
if(mode_r == SRTC_READ) begin
case(rtc_ptr)
0: data_out_r <= rtc_data_r[3:0];
1: data_out_r <= rtc_data_r[7:4];
2: data_out_r <= rtc_data_r[11:8];
3: data_out_r <= rtc_data_r[15:12];
4: data_out_r <= rtc_data_r[19:16];
5: data_out_r <= rtc_data_r[23:20];
6: data_out_r <= rtc_data_r[27:24];
7: data_out_r <= rtc_data_r[31:28];
8: data_out_r <= rtc_data_r[35:32]
+ (rtc_data_r[39:36] << 1)
+ (rtc_data_r[39:36] << 3);
9: data_out_r <= rtc_data_r[43:40];
10: data_out_r <= rtc_data_r[47:44];
11: data_out_r <= rtc_data_r[51:48]
+ (rtc_data_r[55:52] << 1)
+ (rtc_data_r[55:52] << 3) - 10;
12: data_out_r <= rtc_data_r[59:56];
15: begin
rtc_data_r <= rtc_data_in;
data_out_r <= 8'h0f;
end
default: data_out_r <= 8'h0f;
endcase
rtc_ptr <= rtc_ptr == 13 ? 15 : rtc_ptr + 1;
end else begin
data_out_r <= 8'h00;
end
// 1'b1: // control register is write only
endcase
end
end

38
verilog/sd2snes/upd77c25.v
View File

@ -33,7 +33,7 @@ module upd77c25(
input DAT_WR,
input [15:0] DAT_DI,
input [9:0] DAT_WR_ADDR,
// debug
output [15:0] DR,
output [15:0] SR,
@ -43,7 +43,7 @@ module upd77c25(
output [5:0] FL_A,
output [5:0] FL_B
);
parameter STATE_FETCH = 8'b00000001;
parameter STATE_LOAD = 8'b00000010;
parameter STATE_ALU1 = 8'b00000100;
@ -125,14 +125,18 @@ upd77c25_datrom datrom (
wire [15:0] ram_douta;
wire [7:0] ram_addra;
upd77c25_datram datram (
.clka(CLK),
.wea(ram_wea), // Bus [0 : 0]
.addra(ram_addra), // Bus [7 : 0]
.dina(ram_dina), // Bus [15 : 0]
.douta(ram_douta)); // Bus [15 : 0]
.clka(CLK),
.wea(ram_wea), // Bus [0 : 0]
.addra(ram_addra), // Bus [7 : 0]
.dina(ram_dina), // Bus [15 : 0]
.douta(ram_douta)); // Bus [15 : 0]
assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == STATE_NEXT);
assign ram_addra = {regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100) ? 4'b0100 : 4'b0000), regs_dpl};
assign ram_addra = {regs_dph | ((insn_state == STATE_ALU2 && op_dst == 4'b1100)
? 4'b0100
: 4'b0000),
regs_dpl};
reg signed [15:0] regs_k;
reg signed [15:0] regs_l;
reg [15:0] regs_trb;
@ -142,7 +146,6 @@ reg [15:0] regs_sr;
reg [15:0] regs_si;
reg [3:0] regs_sp;
reg cond_true;
reg [8:0] jp_brch;
@ -211,12 +214,12 @@ always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[6:0], nCS};
reg [5:0] reg_oe_sreg;
initial reg_oe_sreg = 6'b111111;
always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
wire reg_oe_rising = !reg_nCS_sreg[2] && (reg_oe_sreg[5:0] == 6'b000001);
wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
reg [5:0] reg_we_sreg;
initial reg_we_sreg = 6'b111111;
always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
wire reg_we_rising = !reg_nCS_sreg[2] && (reg_we_sreg[5:0] == 6'b000001);
wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
reg [7:0] A0r;
initial A0r = 8'b11111111;
@ -260,7 +263,7 @@ always @(posedge CLK) begin
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
end
end else if(reg_oe_rising) begin
case(A0r[3])
1'b0: begin
@ -270,7 +273,7 @@ always @(posedge CLK) begin
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
end
end
endcase
end
@ -352,7 +355,7 @@ always @(posedge CLK) begin
STATE_ALU1: begin
insn_state <= STATE_ALU2;
case(op)
I_OP, I_RT: begin
I_OP, I_RT: begin
alu_q <= regs_ab[op_asl];
if(op_alu[3:1] == 3'b100) begin
alu_p <= 16'h0001;
@ -428,7 +431,7 @@ always @(posedge CLK) begin
end
4'b1100: begin
regs_k <= ram_douta;
regs_l <= idb;
regs_l <= idb;
end
4'b1101: regs_l <= idb;
4'b1110: regs_trb <= idb;
@ -504,7 +507,7 @@ always @(posedge CLK) begin
4'b1101: regs_l <= ld_id;
4'b1110: regs_trb <= ld_id;
4'b1111: ram_dina_r <= ld_id;
endcase
endcase
end
I_JP: begin
case(jp_brch)
@ -563,7 +566,7 @@ always @(posedge CLK) begin
if(op == I_OP) pc <= pc + 1;
else begin
pc <= stack[regs_sp-1];
regs_sp <= regs_sp - 1;
regs_sp <= regs_sp - 1;
end
end
I_JP: begin
@ -582,7 +585,6 @@ always @(posedge CLK) begin
end
STATE_IDLE1: insn_state <= STATE_IDLE2;
STATE_IDLE2: insn_state <= STATE_FETCH;
endcase
end else begin
insn_state <= STATE_IDLE1;