diff --git a/pcb/cart/sd2snes19.brd b/pcb/cart/sd2snes19.brd index 33cd3af..0841eb9 100644 Binary files a/pcb/cart/sd2snes19.brd and b/pcb/cart/sd2snes19.brd differ diff --git a/snes/menu.a65 b/snes/menu.a65 index a973930..9f1f9a6 100644 --- a/snes/menu.a65 +++ b/snes/menu.a65 @@ -24,9 +24,9 @@ menu_init: rts menuloop: +menuloop_s1 sep #$20 : .as rep #$10 : .xl -menuloop_s1 lda isr_done lsr bcc menuloop_s1 diff --git a/src/filetypes.c b/src/filetypes.c index b026b04..d1499b0 100644 --- a/src/filetypes.c +++ b/src/filetypes.c @@ -81,7 +81,7 @@ uint16_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { } res = f_opendir(&dir, (unsigned char*)path); if (res == FR_OK) { - if(pass && parent_tgt) { + if(pass && parent_tgt && mkdb) { // write backlink to parent dir // switch to next bank if record does not fit in current bank if((db_tgt&0xffff) > ((0x10000-(sizeof(next_subdir_tgt)+sizeof(len)+4))&0xffff)) { diff --git a/src/fpga.c b/src/fpga.c index 08100c9..40453b0 100644 --- a/src/fpga.c +++ b/src/fpga.c @@ -141,6 +141,7 @@ void set_avr_bank(uint8_t val) { uint8_t fpga_test() { spi_fpga(); spiTransferByte(0xF0); // TEST + spiTransferByte(0x00); // dummy uint8_t result = spiTransferByte(0x00); spi_none(); return result; diff --git a/src/fpga.h b/src/fpga.h index 64be7ed..bd2bb14 100644 --- a/src/fpga.h +++ b/src/fpga.h @@ -21,6 +21,8 @@ void set_avr_mapper(uint8_t val); void set_avr_bank(uint8_t val); +#define FPGA_TEST_TOKEN (0xa5) + // some macros for bulk transfers (faster) #define FPGA_SEND_BYTE(data) do {SET_AVR_DATA(data); CCLK();} while (0) #define FPGA_SEND_BYTE_SERIAL(data) do {SET_AVR_DATA(data); CCLK();\ diff --git a/src/main.c b/src/main.c index d774293..63ccbee 100644 --- a/src/main.c +++ b/src/main.c @@ -49,6 +49,32 @@ #include "avrcompat.h" #include "filetypes.h" +void writetest(void) { +// HERE BE LIONS, GET IN THE CAR + char teststring[58]; + while(1) { + sram_writeblock((void*)"Testtext of DOOM!!1! 0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ", SRAM_SCRATCHPAD+0x20, 58); + sram_readblock((void*)teststring, SRAM_SCRATCHPAD+0x20, 58); + teststring[57]=0; + dprintf("%s\n", teststring); + } +// END OF LIONS +} + + +void memtest(void) { +/* HERE BE DRAGONS */ + uint32_t dbg_i; + for(dbg_i=0; dbg_i < 65536; dbg_i++) { + sram_writeshort((uint16_t)dbg_i&0xffff, dbg_i*2); + } + save_sram((uint8_t*)"/sd2snes/memtest", 0x20000, 0); + set_pwr_led(0); + while(1); +/* END OF DRAGONS */ +} + + /* Make sure the watchdog is disabled as soon as possible */ /* Copy this code to your bootloader if you use one and your */ /* MCU doesn't disable the WDT after reset! */ @@ -163,14 +189,13 @@ restart: uint16_t mem_dir_id = sram_readshort(SRAM_DIRID); uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD); + if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id)) { uint16_t curr_dir_id = scan_dir(fs_path, 0, 0); // generate files footprint dprintf("curr dir id = %x\n", curr_dir_id); - if((get_db_id(&saved_dir_id) != FR_OK) // no database? || saved_dir_id != curr_dir_id) { // files changed? // XXX dprintf("saved dir id = %x\n", saved_dir_id); - _delay_ms(50); dprintf("rebuilding database..."); _delay_ms(50); curr_dir_id = scan_dir(fs_path, 1, 0); // then rebuild database @@ -184,6 +209,7 @@ restart: dprintf("done\n"); sram_hexdump(SRAM_DB_ADDR, 0x400); } else { + dprintf("saved dir id = %x\n", saved_dir_id); dprintf("different card, consistent db, loading db...\n"); load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR); load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR); @@ -220,7 +246,6 @@ restart: uint8_t cmd = 0; while(!sram_reliable()); - while(!cmd) { cmd=menu_main_loop(); switch(cmd) { @@ -255,7 +280,8 @@ restart: cmd=0; uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0; uint16_t reset_count=0; - while(fpga_test() == 0xa5) { + while(fpga_test() == FPGA_TEST_TOKEN) { + dprintf("%02X\n", fpga_test()); snes_reset_now=get_snes_reset(); if(snes_reset_now) { if(!snes_reset_prev) { @@ -307,7 +333,6 @@ restart: _delay_ms(150); } - /* HERE BE LIONS */ while(1) { set_avr_addr(0x600000); @@ -335,6 +360,6 @@ while(1) { } spi_none(); } - while(1); + while(1); } diff --git a/src/memory.c b/src/memory.c index 8d5c003..d4ddd3a 100644 --- a/src/memory.c +++ b/src/memory.c @@ -286,6 +286,7 @@ uint8_t sram_reliable() { if(val==0x12345678) { score++; } +// dprintf("val=%08lX\n", val); } if(score (32'h0+2*cmd_data[4]))) + if (avr_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[0]) && (spi_byte_cnt > (32'h1+cmd_data[4]))) ADDR_OUT_BUF <= ADDR_OUT_BUF + 1; end +always @(posedge clk) begin + if (spi_bit_cnt == 3'h7) + if (cmd_data[7:4] == 4'hF) + AVR_DATA_IN_BUF <= 8'hA5; + else + AVR_DATA_IN_BUF <= avr_data_in; +end + always @(posedge clk) begin if (spi_bit_cnt == 3'h0) avr_nextaddr_buf <= {avr_nextaddr_buf[0], 1'b1}; @@ -120,15 +128,15 @@ always @(posedge clk) begin end always @(posedge clk) begin - if (spi_bit_cnt == 3'h1 & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1)) + if ((spi_bit_cnt == 3'h1) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1)) AVR_WRITE_BUF <= 1'b0; else AVR_WRITE_BUF <= 1'b1; - if ((spi_bit_cnt == 3'h7) & (cmd_data[7:4] == 4'h8) & (spi_byte_cnt > 32'h0)) + if ((spi_bit_cnt == 3'h6 || spi_bit_cnt == 3'h7) & (cmd_data[7:4] == 4'h8) & (spi_byte_cnt > 32'h0)) AVR_READ_BUF <= 1'b0; else - AVR_READ_BUF <= 1'b1; + AVR_READ_BUF <= 1'b1; end assign avr_nextaddr = avr_nextaddr_buf == 2'b01; diff --git a/verilog/sd2snes/data.v b/verilog/sd2snes/data.v index eab68f5..6067334 100644 --- a/verilog/sd2snes/data.v +++ b/verilog/sd2snes/data.v @@ -46,7 +46,7 @@ wire [7:0] FROM_SRAM_BYTE; assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM; -assign FROM_SRAM_BYTE = ((SRAM_ADDR0 ^ !AVR_ENA) ? SRAM_DATA[7:0] : SRAM_DATA[15:8]); +assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]); assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE) : (AVR_OUT_MEM); @@ -58,6 +58,7 @@ assign SRAM_DATA[7:0] = SRAM_ADDR0 ? (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'b assign SRAM_DATA[15:8] = SRAM_ADDR0 ? 8'bZ : (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) : (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ) : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ))); + always @(posedge CLK) begin if(SNES_DATA_TO_MEM) SNES_IN_MEM <= SNES_DATA; diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index 5c032a8..33a6d9f 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -26,8 +26,6 @@ NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33; NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33; NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33; NET "SNES_CS" IOSTANDARD = LVCMOS33; -NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33; -NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33; NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33; NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33; NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33; @@ -38,54 +36,14 @@ NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33; NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33; NET "SNES_READ" IOSTANDARD = LVCMOS33; NET "SNES_WRITE" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[0]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[10]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[11]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[12]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[13]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[14]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[15]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[16]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[17]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[18]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[19]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[1]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[2]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[3]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[4]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[5]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[6]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[7]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[8]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[9]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[0]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[1]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[2]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[3]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[4]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[5]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[6]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[7]" IOSTANDARD = LVCMOS33; -NET "SRAM_OE" IOSTANDARD = LVCMOS33; -NET "SRAM_WE" IOSTANDARD = LVCMOS33; NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33; -NET "SNES_IRQ" IOSTANDARD = LVCMOS33; NET "SNES_REFRESH" IOSTANDARD = LVCMOS33; NET "SPI_MISO" IOSTANDARD = LVCMOS33; NET "SPI_MOSI" IOSTANDARD = LVCMOS33; NET "SPI_SCK" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[10]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[11]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[12]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[13]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[14]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[15]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[8]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[9]" IOSTANDARD = LVCMOS33; NET "AVR_ENA" LOC = P58; -NET "CLKIN" LOC = P55; +NET "CLKIN" LOC = P125; NET "IRQ_DIR" LOC = P40; -NET "IRQ_DIR" IOSTANDARD = LVCMOS33; NET "SNES_ADDR[0]" LOC = P7; NET "SNES_ADDR[10]" LOC = P32; NET "SNES_ADDR[11]" LOC = P35; @@ -126,13 +84,9 @@ NET "SRAM_ADDR[19]" LOC = P69; NET "SRAM_ADDR[8]" LOC = P68; NET "SRAM_ADDR[9]" LOC = P63; NET "SRAM_CE2[0]" LOC = P77; -NET "SRAM_CE2[0]" IOSTANDARD = LVCMOS33; NET "SRAM_CE2[1]" LOC = P76; -NET "SRAM_CE2[1]" IOSTANDARD = LVCMOS33; NET "SRAM_CE2[2]" LOC = P74; -NET "SRAM_CE2[2]" IOSTANDARD = LVCMOS33; NET "SRAM_CE2[3]" LOC = P73; -NET "SRAM_CE2[3]" IOSTANDARD = LVCMOS33; NET "SRAM_WE" LOC = P70; NET "SNES_DATABUS_DIR" LOC = P141; NET "SNES_DATABUS_OE" LOC = P140; @@ -144,7 +98,7 @@ NET "SNES_DATA[4]" LOC = P135; NET "SNES_DATA[5]" LOC = P131; NET "SNES_DATA[6]" LOC = P129; NET "SNES_DATA[7]" LOC = P127; -NET "SNES_IRQ" LOC = P125; +NET "SNES_IRQ" LOC = P55; NET "SPI_MISO" LOC = P123; NET "SPI_MOSI" LOC = P122; NET "SPI_SCK" LOC = P124; @@ -160,9 +114,7 @@ NET "SRAM_ADDR[5]" LOC = P85; NET "SRAM_ADDR[6]" LOC = P84; NET "SRAM_ADDR[7]" LOC = P83; NET "SRAM_BHE" LOC = P78; -NET "SRAM_BHE" IOSTANDARD = LVCMOS33; NET "SRAM_BLE" LOC = P79; -NET "SRAM_BLE" IOSTANDARD = LVCMOS33; NET "SRAM_DATA[0]" LOC = P95; NET "SRAM_DATA[10]" LOC = P100; NET "SRAM_DATA[11]" LOC = P103; @@ -182,8 +134,58 @@ NET "SRAM_DATA[9]" LOC = P98; NET "SRAM_OE" LOC = P93; NET "CLKIN" IOSTANDARD = LVCMOS33; -NET "CLKIN" PULLUP; +//NET "CLKIN" PULLUP; NET "SPI_SS" IOSTANDARD = LVCMOS33; NET "SPI_SS" PULLUP; //NET "DCM_RST" LOC = P46; //NET "DCM_RST" IOSTANDARD = LVCMOS33; +NET "IRQ_DIR" IOSTANDARD = LVCMOS33; +NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33; +NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33; +NET "SNES_IRQ" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "SRAM_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "SRAM_BHE" IOSTANDARD = LVCMOS33; +NET "SRAM_BLE" IOSTANDARD = LVCMOS33; +NET "SRAM_CE2[0]" IOSTANDARD = LVCMOS33; +NET "SRAM_CE2[1]" IOSTANDARD = LVCMOS33; +NET "SRAM_CE2[2]" IOSTANDARD = LVCMOS33; +NET "SRAM_CE2[3]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[0]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[10]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[11]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[12]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[13]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[14]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[15]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[1]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[2]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[3]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[4]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[5]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[6]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[7]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[8]" IOSTANDARD = LVCMOS33; +NET "SRAM_DATA[9]" IOSTANDARD = LVCMOS33; +NET "SRAM_OE" IOSTANDARD = LVCMOS33; +NET "SRAM_WE" IOSTANDARD = LVCMOS33; +TEMPERATURE = 60 C; +VOLTAGE = 1.25 V; diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 3138e0b..d23c39b 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -309,13 +309,15 @@ initial begin SRAM_OE_ARRAY[2'b11] = 13'b0000000000000; SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0001000000000; // SNES write + /* 13'b0001000000000 */ SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // SNES read - AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000010000; // AVR write + AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0000000000000; // AVR read SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0000000000000; // SNES write SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0000100000000; // SNES read + /* 13'b0000100000000; */ SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0000000000000; // AVR write SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read @@ -328,7 +330,7 @@ end // we have 24 internal cycles to work with. (CLKIN * 4) always @(posedge CLK2) begin - CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start}; + CYCLE_RESET <= {CYCLE_RESET[0], SNES_RW_start}; end always @(posedge CLK2) begin diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index 86f2ad4..975f83b 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -66,8 +66,8 @@ - +