diff --git a/src/clock.c b/src/clock.c
index 9c4cf39..7cd5c8d 100644
--- a/src/clock.c
+++ b/src/clock.c
@@ -27,7 +27,7 @@ void clock_init() {
    -> FPGA freq = 11289473.7Hz
    First, disable and disconnect PLL0.
 */
-//  clock_disconnect();
+  clock_disconnect();
 
 /* PLL is disabled and disconnected. setup PCLK NOW as it cannot be changed
    reliably with PLL0 connected.
@@ -74,7 +74,7 @@ void disablePLL0() {
 }
 
 void connectPLL0() {
-  while(!(LPC_SC->PLL0STAT&PLOCK0));
+  while(!(LPC_SC->PLL0STAT & PLOCK0));
   LPC_SC->PLL0CON |= PLLC0;
   PLL0feed();
 }
diff --git a/src/clock.h b/src/clock.h
index 56be21a..503d1d0 100644
--- a/src/clock.h
+++ b/src/clock.h
@@ -74,6 +74,4 @@ void disableMainOsc(void);
 void PLL0feed(void);
 
 void setClkSrc(uint8_t src);
-
-
 #endif
diff --git a/src/main.c b/src/main.c
index a8f9014..bafa691 100644
--- a/src/main.c
+++ b/src/main.c
@@ -88,7 +88,9 @@ printf("PCONP=%lx\n", LPC_SC->PCONP);
   file_init();
   cic_init(0);
 /* setup timer (fpga clk) */
+  LPC_TIM3->TCR=2;
   LPC_TIM3->CTCR=0;
+  LPC_TIM3->PR=0;
   LPC_TIM3->EMR=EMC0TOGGLE;
   LPC_TIM3->MCR=MR0R;
   LPC_TIM3->MR0=1;
diff --git a/src/timer.c b/src/timer.c
index 65af756..30d6e94 100644
--- a/src/timer.c
+++ b/src/timer.c
@@ -57,9 +57,17 @@ void timer_init(void) {
   /* clear RIT mask */
   LPC_RIT->RIMASK = 0; /*xffffffff;*/
 
-  /* PCLK = CCLK */
+  /* PCLK_RIT = CCLK */
+  BITBAND(LPC_SC->PCLKSEL1, 27) = 0;
   BITBAND(LPC_SC->PCLKSEL1, 26) = 1;
+
+  /* PCLK_TIMER3 = CCLK/4 */
+  BITBAND(LPC_SC->PCLKSEL1, 15) = 0;
+  BITBAND(LPC_SC->PCLKSEL1, 14) = 0;
+
+  /* enable timer 3 */
   BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1;
+
   /* enable SysTick */
   SysTick_Config((SysTick->CALIB & SysTick_CALIB_TENMS_Msk));
 }