From b7d32d62855876c1257cab4cb045d3e62b40e3ce Mon Sep 17 00:00:00 2001 From: ikari Date: Thu, 8 Oct 2009 16:34:26 +0200 Subject: [PATCH] readjust CLKIN_PERIOD --- verilog/sd2snes/dcm.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/sd2snes/dcm.v b/verilog/sd2snes/dcm.v index ed97682..ff64fb0 100644 --- a/verilog/sd2snes/dcm.v +++ b/verilog/sd2snes/dcm.v @@ -37,7 +37,7 @@ module my_dcm ( .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature - .CLKIN_PERIOD(36.561), // Specify period of input clock + .CLKIN_PERIOD(47.000), // Specify period of input clock .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X .DESKEW_ADJUST("SOURCE_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or