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firmware: adjustments for Mk.II Rev.C; enable timesetting from SNES menu

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This commit is contained in:
ikari
2011-03-14 01:45:34 +01:00
parent 9af83658e7
commit bfe9a91d07
34 changed files with 2811 additions and 2564 deletions
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70
src/bootldr/config.h
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@@ -5,17 +5,18 @@
// #define DEBUG_IRQ
// #define DEBUG_MSU1
//#define DEBUG_BL
#ifdef DEBUG_BL
#define DBG_BL
#ifdef DEBUG_UART
#define DBG_UART
#else
#define DBG_BL while(0)
#define DBG_UART while(0)
#endif
#define DBG_BL while(0)
#define FW_START (0x00002000L)
#define FLASH_SECTORS (17)
#define VER "0.0.1(NSFW)"
#define IN_AHBRAM __attribute__ ((section(".ahbram")))
@@ -29,10 +30,10 @@
#define SD_CHANGE_CLR() do {LPC_GPIOINT->IO2IntClr = BV(SD_DT_BIT);} while(0)
#define SD_DT_REG LPC_GPIO2
#define SD_DT_BIT 3
#define SD_WP_REG LPC_GPIO2
#define SD_WP_BIT 4
#define SD_DT_REG LPC_GPIO0
#define SD_DT_BIT 8
#define SD_WP_REG LPC_GPIO0
#define SD_WP_BIT 6
#define SDCARD_DETECT (!(BITBAND(SD_DT_REG->FIOPIN, SD_DT_BIT)))
#define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT))
@@ -40,16 +41,16 @@
#define CONFIG_SD_BLOCKTRANSFER 1
#define CONFIG_SD_AUTO_RETRIES 10
// #define SD_CHANGE_VECT
// #define CONFIG_SD_DATACRC 1
#define CONFIG_SD_DATACRC 1
#define CONFIG_UART_NUM 3
// #define CONFIG_CPU_FREQUENCY 90315789
#define CONFIG_CPU_FREQUENCY (92000000L)
//#define CONFIG_CPU_FREQUENCY 46000000
#define CONFIG_UART_PCLKDIV 1
#define CONFIG_UART_TX_BUF_SHIFT 1
#define CONFIG_UART_TX_BUF_SHIFT 8
#define CONFIG_UART_BAUDRATE 921600
#define CONFIG_UART_DEADLOCKABLE
//#define CONFIG_UART_DEADLOCKABLE
#define SSP_CLK_DIVISOR_FAST 2
#define SSP_CLK_DIVISOR_SLOW 250
@@ -58,20 +59,19 @@
#define SSP_CLK_DIVISOR_FPGA_SLOW 20
#define SNES_RESET_REG LPC_GPIO1
#define SNES_RESET_BIT 29
/* XXX Rev.B: 1.26 */
#define SNES_CIC_D0_REG LPC_GPIO1
#define SNES_CIC_D0_BIT 26
/* XXX Rev.B: 0.1 */
#define SNES_CIC_D1_REG LPC_GPIO1
#define SNES_CIC_D1_BIT 25
/* XXX Rev.B: 0.0 */
#define SNES_CIC_STATUS_REG LPC_GPIO0
#define SNES_CIC_STATUS_BIT 1
/* XXX Rev.B: 1.29 */
#define SNES_CIC_PAIR_REG LPC_GPIO0
#define SNES_CIC_PAIR_BIT 0
/* XXX Rev.B: 1.25 */
#define SNES_RESET_BIT 26
#define SNES_CIC_D0_REG LPC_GPIO0
#define SNES_CIC_D0_BIT 1
#define SNES_CIC_D1_REG LPC_GPIO0
#define SNES_CIC_D1_BIT 0
#define SNES_CIC_STATUS_REG LPC_GPIO1
#define SNES_CIC_STATUS_BIT 29
#define SNES_CIC_PAIR_REG LPC_GPIO1
#define SNES_CIC_PAIR_BIT 25
#define QSORT_MAXELEM 1024
@@ -88,20 +88,18 @@
#define SD_CLKREG LPC_GPIO0
#define SD_CMDREG LPC_GPIO0
#define SD_DAT0REG LPC_GPIO0
#define SD_DAT1REG LPC_GPIO1
#define SD_DAT2REG LPC_GPIO1
#define SD_DAT3REG LPC_GPIO0
#define SD_DAT0REG LPC_GPIO2
#define SD_DAT1REG LPC_GPIO2
#define SD_DAT2REG LPC_GPIO2
#define SD_DAT3REG LPC_GPIO2
#define SD_CLKPIN (7)
#define SD_CMDPIN (9)
#define SD_DAT0PIN (8)
#define SD_DAT1PIN (14)
#define SD_DAT2PIN (15)
#define SD_DAT3PIN (6)
#define SD_DAT0PIN (0)
#define SD_DAT1PIN (1)
#define SD_DAT2PIN (2)
#define SD_DAT3PIN (3)
#define SD_DAT ((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))\
|((SD_DAT1REG->FIOPIN1 >> 5) & 0x6)\
|((BITBAND(SD_DAT3REG->FIOPIN, SD_DAT3PIN)) << 3))
#define SD_DAT (LPC_GPIO2->FIOPIN & 0xf)
#endif