Firmware/FPGA: replace magic numbers with constants
This commit is contained in:
Maximilian Rehkopf
parent
605fc2dfb1
commit
c204aa9a0b
@ -1,6 +1,6 @@
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/* sd2snes - SD card based universal cartridge for the SNES
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Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
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AVR firmware portion
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Copyright (C) 2009-2012 Maximilian Rehkopf <otakon@gmx.net>
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uC firmware portion
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Inspired by and based on code from sd2iec, written by Ingo Korb et al.
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See sdcard.c|h, config.h.
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@ -149,7 +149,7 @@ void fpga_spi_init(void) {
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void set_msu_addr(uint16_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x02);
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FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MSUBUF);
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FPGA_TX_BYTE((address>>8)&0xff);
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FPGA_TX_BYTE((address)&0xff);
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FPGA_DESELECT();
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@ -157,7 +157,7 @@ void set_msu_addr(uint16_t address) {
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void set_dac_addr(uint16_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x01);
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FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_DACBUF);
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FPGA_TX_BYTE((address>>8)&0xff);
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FPGA_TX_BYTE((address)&0xff);
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FPGA_DESELECT();
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@ -165,7 +165,7 @@ void set_dac_addr(uint16_t address) {
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void set_mcu_addr(uint32_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x00);
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FPGA_TX_BYTE(FPGA_CMD_SETADDR | FPGA_TGT_MEM);
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FPGA_TX_BYTE((address>>16)&0xff);
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FPGA_TX_BYTE((address>>8)&0xff);
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FPGA_TX_BYTE((address)&0xff);
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@ -174,7 +174,7 @@ void set_mcu_addr(uint32_t address) {
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void set_saveram_mask(uint32_t mask) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x20);
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FPGA_TX_BYTE(FPGA_CMD_SETRAMMASK);
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FPGA_TX_BYTE((mask>>16)&0xff);
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FPGA_TX_BYTE((mask>>8)&0xff);
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FPGA_TX_BYTE((mask)&0xff);
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@ -183,7 +183,7 @@ void set_saveram_mask(uint32_t mask) {
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void set_rom_mask(uint32_t mask) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x10);
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FPGA_TX_BYTE(FPGA_CMD_SETROMMASK);
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FPGA_TX_BYTE((mask>>16)&0xff);
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FPGA_TX_BYTE((mask>>8)&0xff);
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FPGA_TX_BYTE((mask)&0xff);
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@ -192,13 +192,13 @@ void set_rom_mask(uint32_t mask) {
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void set_mapper(uint8_t val) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x30 | (val & 0x0f));
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FPGA_TX_BYTE(FPGA_CMD_SETMAPPER(val));
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FPGA_DESELECT();
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}
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uint8_t fpga_test() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF0); /* TEST */
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FPGA_TX_BYTE(FPGA_CMD_TEST);
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uint8_t result = FPGA_RX_BYTE();
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FPGA_DESELECT();
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return result;
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@ -206,7 +206,7 @@ uint8_t fpga_test() {
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uint16_t fpga_status() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF1); /* STATUS */
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FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
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uint16_t result = (FPGA_RX_BYTE()) << 8;
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result |= FPGA_RX_BYTE();
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FPGA_DESELECT();
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@ -215,64 +215,48 @@ uint16_t fpga_status() {
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void fpga_set_sddma_range(uint16_t start, uint16_t end) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x60); /* DMA_RANGE */
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FPGA_TX_BYTE(FPGA_CMD_SDDMA_RANGE);
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FPGA_TX_BYTE(start>>8);
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FPGA_TX_BYTE(start&0xff);
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FPGA_TX_BYTE(end>>8);
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FPGA_TX_BYTE(end&0xff);
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//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
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FPGA_DESELECT();
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}
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void fpga_sddma(uint8_t tgt, uint8_t partial) {
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uint32_t test = 0;
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uint8_t status = 0;
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BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 0;
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FPGA_SELECT();
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FPGA_TX_BYTE(0x40 | (tgt & 0x3) | ((partial & 1) << 2) ); /* DO DMA */
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FPGA_TX_BYTE(FPGA_CMD_SDDMA | (tgt & 3) | partial ? FPGA_SDDMA_PARTIAL : 0);
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FPGA_TX_BYTE(0x00); /* dummy for falling DMA_EN edge */
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//if(tgt==1 && (test=FPGA_RX_BYTE()) != 0x41) printf("!!!!!!!!!!!!!!! -%02x- \n", test);
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FPGA_DESELECT();
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF1); /* STATUS */
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FPGA_TX_BYTE(FPGA_CMD_GETSTATUS);
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DBG_SD printf("FPGA DMA request sent, wait for completion...");
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while((status=FPGA_RX_BYTE()) & 0x80) {
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while(FPGA_RX_BYTE() & 0x80) {
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FPGA_RX_BYTE(); /* eat the 2nd status byte */
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test++;
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}
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DBG_SD printf("...complete\n");
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FPGA_DESELECT();
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// if(test<5)printf("loopy: %ld %02x\n", test, status);
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BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1;
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}
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void set_dac_vol(uint8_t volume) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0x50);
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FPGA_TX_BYTE(volume);
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FPGA_TX_BYTE(0x00); /* latch rise */
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FPGA_TX_BYTE(0x00); /* latch fall */
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FPGA_DESELECT();
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}
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void dac_play() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe2);
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FPGA_TX_BYTE(FPGA_CMD_DACPLAY);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void dac_pause() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe1);
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FPGA_TX_BYTE(FPGA_CMD_DACPAUSE);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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void dac_reset() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe3);
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FPGA_TX_BYTE(FPGA_CMD_DACRESETPTR);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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@ -280,7 +264,7 @@ void dac_reset() {
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void msu_reset(uint16_t address) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe4);
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FPGA_TX_BYTE(FPGA_CMD_MSUSETPTR);
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FPGA_TX_BYTE((address>>8) & 0xff); /* address hi */
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FPGA_TX_BYTE(address & 0xff); /* address lo */
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FPGA_TX_BYTE(0x00); /* latch reset */
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@ -290,24 +274,16 @@ void msu_reset(uint16_t address) {
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void set_msu_status(uint8_t set, uint8_t reset) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe0);
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FPGA_TX_BYTE(FPGA_CMD_MSUSETBITS);
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FPGA_TX_BYTE(set);
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FPGA_TX_BYTE(reset);
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FPGA_TX_BYTE(0x00); /* latch reset */
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FPGA_DESELECT();
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}
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uint8_t get_msu_volume() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF4); /* MSU_VOLUME */
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uint8_t result = FPGA_RX_BYTE();
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FPGA_DESELECT();
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return result;
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}
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uint16_t get_msu_track() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF3); /* MSU_TRACK */
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FPGA_TX_BYTE(FPGA_CMD_MSUGETTRACK);
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uint16_t result = (FPGA_RX_BYTE()) << 8;
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result |= FPGA_RX_BYTE();
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FPGA_DESELECT();
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@ -316,7 +292,7 @@ uint16_t get_msu_track() {
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uint32_t get_msu_offset() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xF2); /* MSU_OFFSET */
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FPGA_TX_BYTE(FPGA_CMD_MSUGETADDR);
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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result |= (FPGA_RX_BYTE()) << 8;
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@ -327,7 +303,7 @@ uint32_t get_msu_offset() {
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uint32_t get_snes_sysclk() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xFE); /* GET_SYSCLK */
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FPGA_TX_BYTE(FPGA_CMD_GETSYSCLK);
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FPGA_TX_BYTE(0x00); /* dummy (copy current sysclk count to register) */
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uint32_t result = (FPGA_RX_BYTE()) << 24;
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result |= (FPGA_RX_BYTE()) << 16;
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@ -339,7 +315,7 @@ uint32_t get_snes_sysclk() {
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void set_bsx_regs(uint8_t set, uint8_t reset) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe6);
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FPGA_TX_BYTE(FPGA_CMD_BSXSETBITS);
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FPGA_TX_BYTE(set);
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FPGA_TX_BYTE(reset);
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FPGA_TX_BYTE(0x00); /* latch reset */
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@ -348,7 +324,7 @@ void set_bsx_regs(uint8_t set, uint8_t reset) {
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void set_fpga_time(uint64_t time) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe5);
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FPGA_TX_BYTE(FPGA_CMD_RTCSET);
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FPGA_TX_BYTE((time >> 48) & 0xff);
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FPGA_TX_BYTE((time >> 40) & 0xff);
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FPGA_TX_BYTE((time >> 32) & 0xff);
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@ -362,7 +338,7 @@ void set_fpga_time(uint64_t time) {
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void fpga_reset_srtc_state() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe7);
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FPGA_TX_BYTE(FPGA_CMD_SRTCRESET);
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FPGA_TX_BYTE(0x00);
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FPGA_TX_BYTE(0x00);
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FPGA_DESELECT();
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@ -370,7 +346,7 @@ void fpga_reset_srtc_state() {
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void fpga_reset_dspx_addr() {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe8);
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FPGA_TX_BYTE(FPGA_CMD_DSPRESETPTR);
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FPGA_TX_BYTE(0x00);
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FPGA_TX_BYTE(0x00);
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FPGA_DESELECT();
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@ -378,7 +354,7 @@ void fpga_reset_dspx_addr() {
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void fpga_write_dspx_pgm(uint32_t data) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xe9);
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FPGA_TX_BYTE(FPGA_CMD_DSPWRITEPGM);
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FPGA_TX_BYTE((data>>16)&0xff);
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FPGA_TX_BYTE((data>>8)&0xff);
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FPGA_TX_BYTE((data)&0xff);
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@ -389,7 +365,7 @@ void fpga_write_dspx_pgm(uint32_t data) {
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void fpga_write_dspx_dat(uint16_t data) {
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FPGA_SELECT();
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FPGA_TX_BYTE(0xea);
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FPGA_TX_BYTE(FPGA_CMD_DSPWRITEDAT);
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FPGA_TX_BYTE((data>>8)&0xff);
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FPGA_TX_BYTE((data)&0xff);
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FPGA_TX_BYTE(0x00);
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@ -399,7 +375,7 @@ void fpga_write_dspx_dat(uint16_t data) {
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void fpga_dspx_reset(uint8_t reset) {
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FPGA_SELECT();
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FPGA_TX_BYTE(reset ? 0xeb : 0xec);
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FPGA_TX_BYTE(reset ? FPGA_CMD_DSPRESET : FPGA_CMD_DSPUNRESET);
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FPGA_TX_BYTE(0x00);
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FPGA_DESELECT();
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}
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@ -407,7 +383,7 @@ void fpga_dspx_reset(uint8_t reset) {
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void fpga_set_features(uint8_t feat) {
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printf("set features: %02x\n", feat);
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FPGA_SELECT();
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FPGA_TX_BYTE(0xed);
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FPGA_TX_BYTE(FPGA_CMD_SETFEATURE);
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FPGA_TX_BYTE(feat);
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FPGA_DESELECT();
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}
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@ -415,7 +391,7 @@ void fpga_set_features(uint8_t feat) {
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void fpga_set_213f(uint8_t data) {
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printf("set 213f: %d\n", data);
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FPGA_SELECT();
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FPGA_TX_BYTE(0xee);
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FPGA_TX_BYTE(FPGA_CMD_SET213F);
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FPGA_TX_BYTE(data);
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FPGA_DESELECT();
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}
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@ -57,6 +57,44 @@
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#define FPGA_WAIT_RDY() do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
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/* command parameters */
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#define FPGA_MEM_AUTOINC (0x8)
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#define FPGA_SDDMA_PARTIAL (0x4)
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#define FPGA_TGT_MEM (0x0)
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#define FPGA_TGT_DACBUF (0x1)
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#define FPGA_TGT_MSUBUF (0x2)
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/* commands */
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#define FPGA_CMD_SETADDR (0x00)
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#define FPGA_CMD_SETROMMASK (0x10)
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#define FPGA_CMD_SETRAMMASK (0x20)
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#define FPGA_CMD_SETMAPPER(x) (0x30 | (x & 15))
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#define FPGA_CMD_SDDMA (0x40)
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#define FPGA_CMD_SDDMA_RANGE (0x60)
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#define FPGA_CMD_READMEM (0x80)
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#define FPGA_CMD_WRITEMEM (0x90)
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#define FPGA_CMD_MSUSETBITS (0xe0)
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#define FPGA_CMD_DACPAUSE (0xe1)
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#define FPGA_CMD_DACPLAY (0xe2)
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#define FPGA_CMD_DACRESETPTR (0xe3)
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#define FPGA_CMD_MSUSETPTR (0xe4)
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#define FPGA_CMD_RTCSET (0xe5)
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#define FPGA_CMD_BSXSETBITS (0xe6)
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#define FPGA_CMD_SRTCRESET (0xe7)
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#define FPGA_CMD_DSPRESETPTR (0xe8)
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#define FPGA_CMD_DSPWRITEPGM (0xe9)
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#define FPGA_CMD_DSPWRITEDAT (0xea)
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#define FPGA_CMD_DSPRESET (0xeb)
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#define FPGA_CMD_DSPUNRESET (0xec)
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#define FPGA_CMD_SETFEATURE (0xed)
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#define FPGA_CMD_SET213F (0xee)
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#define FPGA_CMD_TEST (0xf0)
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#define FPGA_CMD_GETSTATUS (0xf1)
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#define FPGA_CMD_MSUGETADDR (0xf2)
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#define FPGA_CMD_MSUGETTRACK (0xf3)
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#define FPGA_CMD_GETSYSCLK (0xfe)
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#define FPGA_CMD_ECHO (0xff)
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void fpga_spi_init(void);
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uint8_t fpga_test(void);
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uint16_t fpga_status(void);
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@ -65,7 +103,6 @@ void spi_sd(void);
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void spi_none(void);
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void set_mcu_addr(uint32_t);
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void set_dac_addr(uint16_t);
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void set_dac_vol(uint8_t);
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void dac_play(void);
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void dac_pause(void);
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void dac_reset(void);
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@ -77,7 +114,6 @@ void set_rom_mask(uint32_t);
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void set_mapper(uint8_t val);
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void fpga_sddma(uint8_t tgt, uint8_t partial);
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void fpga_set_sddma_range(uint16_t start, uint16_t end);
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uint8_t get_msu_volume(void);
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uint16_t get_msu_track(void);
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uint32_t get_msu_offset(void);
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uint32_t get_snes_sysclk(void);
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@ -161,7 +161,6 @@ int msu1_check(uint8_t* filename) {
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int msu1_loop() {
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/* it is assumed that the MSU file is already opened by calling msu1_check(). */
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set_dac_vol(0x00);
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while(fpga_status() & 0x4000);
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uint16_t dac_addr = 0;
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uint16_t msu_addr = 0;
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