diff --git a/src/Makefile b/src/Makefile index 083cae1..82ef750 100644 --- a/src/Makefile +++ b/src/Makefile @@ -55,7 +55,7 @@ TARGET = $(OBJDIR)/sd2snes # List C source files here. (C dependencies are automatically generated.) -SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c sdcard.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c +SRC = main.c ff.c ccsbcs.c clock.c uart.c power.c led.c timer.c printf.c spi.c fileops.c rtc.c fpga.c fpga_spi.c snes.c smc.c memory.c filetypes.c faulthandler.c sort.c crc32.c cic.c cli.c xmodem.c irq.c rle.c sdnative.c # List Assembler source files here. diff --git a/src/config.h b/src/config.h index b135e92..c538e18 100644 --- a/src/config.h +++ b/src/config.h @@ -1,7 +1,7 @@ #ifndef _CONFIG_H #define _CONFIG_H -#define VER "0.0.1" +#define VER "0.0.1(NSFW)" #define IN_AHBRAM __attribute__ ((section(".ahbram"))) diff --git a/src/fileops.c b/src/fileops.c index 1cd5788..a596d7d 100644 --- a/src/fileops.c +++ b/src/fileops.c @@ -33,7 +33,6 @@ WCHAR ff_convert(WCHAR w, UINT dir) { return w; }*/ - void file_init() { file_res=f_mount(0, &fatfs); } @@ -44,6 +43,9 @@ void file_open_by_filinfo(FILINFO* fno) { void file_open(uint8_t* filename, BYTE flags) { file_res = f_open(&file_handle, (TCHAR*)filename, flags); + file_block_off = sizeof(file_buf); + file_block_max = sizeof(file_buf); + file_status = file_res ? FILE_ERR : FILE_OK; } void file_close() { @@ -79,3 +81,12 @@ UINT file_writeblock(void* buf, uint32_t addr, uint16_t size) { file_res = f_write(&file_handle, buf, size, &bytes_written); return bytes_written; } + +uint8_t file_getc() { + if(file_block_off == file_block_max) { + file_block_max = file_read(); + if(file_block_max == 0) file_status = FILE_EOF; + file_block_off = 0; + } + return file_buf[file_block_off++]; +} diff --git a/src/fileops.h b/src/fileops.h index fca81dc..8f55a70 100644 --- a/src/fileops.h +++ b/src/fileops.h @@ -29,11 +29,15 @@ #include #include "ff.h" +enum filestates { FILE_OK=0, FILE_ERR, FILE_EOF }; + BYTE file_buf[512]; FATFS fatfs; FIL file_handle; FRESULT file_res; uint8_t file_lfn[258]; +uint16_t file_block_off, file_block_max; +enum filestates file_status; void file_init(void); void file_open(uint8_t* filename, BYTE flags); @@ -43,4 +47,6 @@ UINT file_read(void); UINT file_write(void); UINT file_readblock(void* buf, uint32_t addr, uint16_t size); UINT file_writeblock(void* buf, uint32_t addr, uint16_t size); + +uint8_t file_getc(void); #endif diff --git a/src/filetypes.c b/src/filetypes.c index 271a189..a66001e 100644 --- a/src/filetypes.c +++ b/src/filetypes.c @@ -170,22 +170,22 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { numentries++; if(pass) { if(mkdb) { - snes_romprops_t romprops; +/* snes_romprops_t romprops; */ path[len]='/'; strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len); uint16_t pathlen = strlen(path); switch(type) { case TYPE_SMC: -/* file_open_by_filinfo(&fno); +/* file_open_by_filinfo(&fno); if(file_res){ printf("ZOMG NOOOO %d\n", file_res); } smc_id(&romprops); - file_close(); -*/ + file_close(); */ + /* write element pointer to current dir structure */ /* printf("d=%d Saving %lX to Address %lX [file]\n", depth, db_tgt, dir_tgt); */ - if((db_tgt&0xffff) > ((0x10000-(sizeof(romprops) + sizeof(len) + pathlen + 1))&0xffff)) { + if((db_tgt&0xffff) > ((0x10000-(sizeof(len) + pathlen + sizeof(fno.fsize) + 1))&0xffff)) { printf("switch! old=%lx ", db_tgt); db_tgt &= 0xffff0000; db_tgt += 0x00010000; @@ -195,11 +195,13 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { dir_tgt += 4; /* save element: - index of last slash character - - file name */ + - file name + - file size */ /* sram_writeblock((uint8_t*)&romprops, db_tgt, sizeof(romprops)); */ sram_writebyte(len+1, db_tgt); sram_writeblock(path, db_tgt + sizeof(len), pathlen + 1); - db_tgt += sizeof(len) + pathlen + 1; + sram_writelong(fno.fsize, db_tgt + sizeof(len) + pathlen + 1); + db_tgt += sizeof(len) + pathlen + sizeof(fno.fsize) + 1; break; case TYPE_UNKNOWN: default: @@ -222,6 +224,7 @@ uint32_t scan_dir(char* path, char mkdb, uint32_t this_dir_tgt) { } } else uart_putc(0x30+res); } + printf("db_tgt=%lx dir_end=%lx\n", db_tgt, dir_end); sram_writelong(db_tgt, SRAM_DB_ADDR+4); sram_writelong(dir_end, SRAM_DB_ADDR+8); return crc; diff --git a/src/fpga.c b/src/fpga.c index b3a89f9..1d7f029 100644 --- a/src/fpga.c +++ b/src/fpga.c @@ -51,6 +51,7 @@ #include "spi.h" #include "led.h" #include "timer.h" +#include "rle.h" void fpga_set_prog_b(uint8_t val) { if(val) @@ -95,6 +96,7 @@ void fpga_postinit() { void fpga_pgm(uint8_t* filename) { int MAXRETRIES = 10; int retries = MAXRETRIES; + uint8_t data; do { fpga_set_prog_b(0); uart_putc('P'); @@ -103,7 +105,6 @@ void fpga_pgm(uint8_t* filename) { LPC_GPIO2->FIOMASK1 = ~(BV(0)); uart_putc('p'); - UINT bytes_read; /* open configware file */ file_open(filename, FA_READ); @@ -112,14 +113,13 @@ void fpga_pgm(uint8_t* filename) { uart_putc(0x30+file_res); return; } - + uart_putc('C'); for (;;) { - bytes_read = file_read(); - if (file_res || bytes_read == 0) break; /* error or eof */ - for(int i=0; iPINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */ | BV(3) | BV(5); /* SSP0 (FPGA) except SS */ LPC_PINCON->PINSEL0 = BV(31) /* SSP0 */ - | BV(13) | BV(15) | BV(17) | BV(19) /* SSP1 (SD) */ +/* | BV(13) | BV(15) | BV(17) | BV(19) SSP1 (SD) */ | BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ /* pull-down CIC data lines */ @@ -58,7 +59,10 @@ int main(void) { /* do this last because the peripheral init()s change PCLK dividers */ clock_init(); - sd_init(); +// sd_init(); + sdn_init(); +// while(1); + fpga_spi_init(); delay_ms(10); printf("\n\nsd2snes mk.2\n============\nfw ver.: " VER "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY); @@ -82,7 +86,7 @@ int main(void) { LPC_TIM3->MR0=1; LPC_TIM3->TCR=1; fpga_init(); - fpga_pgm((uint8_t*)"/sd2snes/main.bit"); + fpga_pgm((uint8_t*)"/main.bit.rle"); restart: if(get_cic_state() == CIC_PAIR) { printf("PAIR MODE ENGAGED!\n"); @@ -102,6 +106,7 @@ restart: uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD); printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id); + mem_magic=0x12938712; /* always rescan card for now */ if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id)) { /* generate fs footprint (interesting files only) */ uint32_t curr_dir_id = scan_dir(fs_path, 0, 0); @@ -159,7 +164,6 @@ restart: printf("test sram\n"); while(!sram_reliable()); printf("ok\n"); - sram_hexdump(SRAM_DB_ADDR, 0x200); while(!cmd) { cmd=menu_main_loop(); diff --git a/src/memory.c b/src/memory.c index b7c8836..a30b917 100644 --- a/src/memory.c +++ b/src/memory.c @@ -174,6 +174,8 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr) { } f_lseek(&file_handle, romprops.offset); FPGA_DESELECT(); + FPGA_SELECT(); + FPGA_TX_BYTE(0x91); /* write w/ increment */ for(;;) { /* SPI_OFFLOAD=1; */ bytes_read = file_read(); @@ -183,14 +185,13 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr) { /* bounce_busy_led(); */ uart_putc('.'); } - FPGA_SELECT(); - FPGA_TX_BYTE(0x91); /* write w/ increment */ - for(int j=0; j +#include +#include +#include "config.h" +#include "crc.h" +#include "diskio.h" +#include "spi.h" +#include "timer.h" +#include "uart.h" +#include "led.h" +#include "sdnative.h" +#include "fileops.h" + +#define MAX_CARDS 1 + +// SD/MMC commands +#define GO_IDLE_STATE 0 +#define SEND_OP_COND 1 +#define SWITCH_FUNC 6 +#define SEND_IF_COND 8 +#define SEND_CSD 9 +#define SEND_CID 10 +#define STOP_TRANSMISSION 12 +#define SEND_STATUS 13 +#define SET_BLOCKLEN 16 +#define READ_SINGLE_BLOCK 17 +#define READ_MULTIPLE_BLOCK 18 +#define WRITE_BLOCK 24 +#define WRITE_MULTIPLE_BLOCK 25 +#define PROGRAM_CSD 27 +#define SET_WRITE_PROT 28 +#define CLR_WRITE_PROT 29 +#define SEND_WRITE_PROT 30 +#define ERASE_WR_BLK_STAR_ADDR 32 +#define ERASE_WR_BLK_END_ADDR 33 +#define ERASE 38 +#define LOCK_UNLOCK 42 +#define APP_CMD 55 +#define GEN_CMD 56 +#define READ_OCR 58 +#define CRC_ON_OFF 59 + +// SD ACMDs +#define SD_STATUS 13 +#define SD_SEND_NUM_WR_BLOCKS 22 +#define SD_SET_WR_BLK_ERASE_COUNT 23 +#define SD_SEND_OP_COND 41 +#define SD_SET_CLR_CARD_DETECT 42 +#define SD_SEND_SCR 51 + +// R1 status bits +#define STATUS_IN_IDLE 1 +#define STATUS_ERASE_RESET 2 +#define STATUS_ILLEGAL_COMMAND 4 +#define STATUS_CRC_ERROR 8 +#define STATUS_ERASE_SEQ_ERROR 16 +#define STATUS_ADDRESS_ERROR 32 +#define STATUS_PARAMETER_ERROR 64 + + +/* Card types - cardtype == 0 is MMC */ +#define CARD_SD (1<<0) +#define CARD_SDHC (1<<1) + +#define SD_CLKREG LPC_GPIO0 +#define SD_CMDREG LPC_GPIO0 +#define SD_DAT0REG LPC_GPIO0 +#define SD_DAT1REG LPC_GPIO1 +#define SD_DAT2REG LPC_GPIO1 +#define SD_DAT3REG LPC_GPIO0 + +#define SD_CLKPIN (7) +#define SD_CMDPIN (9) +#define SD_DAT0PIN (8) +#define SD_DAT1PIN (14) +#define SD_DAT2PIN (15) +#define SD_DAT3PIN (6) + +/* + 1 DAT3/SS P0.6 + 2 CMD/DI P0.9 + 5 Clock P0.7 + 7 DAT0/DO P0.8 + 8 DAT1/IRQ P1.14 + 9 DAT2/NC P1.15 +*/ + +/* SD init procedure + ================= + - initial clock frequency: ~100kHz + - cycle the clock for at least 74 cycles (some more may be safer) + - send CMD0 + - send CMD8 (SEND_OP_COND); if no response -> HCS=0; else HCS=1 + - send ACMD41 until OCR[31] (busy) becomes 1 (means: ready) + - if OCR[30] (CCS) set -> SDHC; else SDSC + - send CMD2 (read CID) (maybe log some stuff from the CID) + - send CMD3 (read RCA), store RCA +== end of initialisation == + - send CMD9 (read CSD) with RCA, maybe do sth with TRAN_SPEED + - send CMD7 with RCA, select card, put card in tran + - maybe send CMD13 with RCA to check state (tran) + - send ACMD51 with RCA to read SCR (maybe, to check 4bit support) + - increase clock speed + - send ACMD6 with RCA to set 4bit bus width + - send transfer cmds +*/ + +/* + static CMD payloads. (no CRC calc required) + - CMD0: 0x40 0x00 0x00 0x00 0x00 0x95 + - CMD8: 0x48 0x00 0x00 0x01 0xaa 0x87 + - CMD2: 0x42 0x00 0x00 0x00 0x00 0x4d + - CMD3: 0x43 0x00 0x00 0x00 0x00 0x21 + - CMD55: 0x77 0x00 0x00 0x00 0x00 0x65 +*/ + +uint8_t cmd[6]={0,0,0,0,0,0}; +uint8_t rsp[17]; +uint8_t csd[17]; +uint8_t ccs=0; +uint8_t rca1, rca2; + +int during_blocktrans = 0; +uint32_t last_block = 0; + +/** + * getbits - read value from bit buffer + * @buffer: pointer to the data buffer + * @start : index of the first bit in the value + * @bits : number of bits in the value + * + * This function returns a value from the memory region passed as + * buffer, starting with bit "start" and "bits" bit long. The buffer + * is assumed to be MSB first, passing 0 for start will read starting + * from the highest-value bit of the first byte of the buffer. + */ +static uint32_t getbits(void *buffer, uint16_t start, int8_t bits) { + uint8_t *buf = buffer; + uint32_t result = 0; + + if ((start % 8) != 0) { + /* Unaligned start */ + result += buf[start / 8] & (0xff >> (start % 8)); + bits -= 8 - (start % 8); + start += 8 - (start % 8); + } + while (bits >= 8) { + result = (result << 8) + buf[start / 8]; + start += 8; + bits -= 8; + } + if (bits > 0) { + result = result << bits; + result = result + (buf[start / 8] >> (8-bits)); + } else if (bits < 0) { + /* Fraction of a single byte */ + result = result >> -bits; + } + return result; +} + +static inline void wiggle_slow_pos(uint16_t times) { + while(times--) { + delay_us(5); + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + delay_us(5); + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_slow_neg(uint16_t times) { + while(times--) { + delay_us(5); + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + delay_us(5); + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_fast_pos(uint16_t times) { + while(times--) { + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + } +} + +static inline void wiggle_fast_neg(uint16_t times) { + while(times--) { + BITBAND(SD_CLKREG->FIOCLR, SD_CLKPIN) = 1; + BITBAND(SD_CLKREG->FIOSET, SD_CLKPIN) = 1; + } +} + + +/* + send_command_slow + send SD command and put response in rsp. + returns length of response or 0 if there was no response +*/ +int send_command_slow(uint8_t* cmd, uint8_t* rsp){ + uint8_t shift, i=6; + int rsplen; +// printf("send_command_slow: sending CMD:\n"); + wiggle_slow_pos(5); +// uart_trace(cmd, 0, 6); + switch(*cmd & 0x3f) { + case 0: + rsplen = 0; + break; + case 2: + case 9: + case 10: + rsplen = 17; + break; + default: + rsplen = 6; + } + /* send command */ + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + + while(i--) { + shift = 8; + do { + shift--; + uint8_t data = *cmd; + *cmd<<=1; + if(data&0x80) { + BITBAND(SD_CMDREG->FIOSET, SD_CMDPIN) = 1; + } else { + BITBAND(SD_CMDREG->FIOCLR, SD_CMDPIN) = 1; + } + wiggle_slow_pos(1); + } while (shift); + cmd++; + } + + wiggle_slow_pos(1); + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0; + + if(rsplen) { + uint16_t timeout=1000; + /* wait for responsebob */ + while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) { + wiggle_slow_neg(1); + } + // printf("timeout=%d\n", timeout); + if(!timeout) { + return 0; /* no response within timeout */ + } + + i=rsplen; + while(i--) { + shift = 8; + uint8_t data=0; + do { + shift--; + data |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << shift; + wiggle_slow_neg(1); + } while (shift); + *rsp=data; + rsp++; + } + } + return rsplen; +} + + +/* + send_command_fast + send SD command and put response in rsp. + returns length of response or 0 if there was no response +*/ +int send_command_fast(uint8_t* cmd, uint8_t* rsp, uint8_t* buf){ + uint8_t datshift=8, cmdshift, i=6; + int rsplen, dat=0, datcnt=512, j=0; + static int state=0; +// printf("send_command_fast: sending CMD:\n"); + wiggle_fast_pos(5); +// uart_trace(cmd, 0, 6); + switch(*cmd & 0x3f) { + case 0: + rsplen = 0; + break; + case 2: + case 9: + case 10: + rsplen = 17; + break; + case 17: + case 18: + dat = 1; + default: + rsplen = 6; + } + + if(dat && (buf==NULL)) { + printf("error: buf is null but data transfer expected.\n"); + return 0; + } + /* send command */ + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + + while(i--) { + cmdshift = 8; + do { + cmdshift--; + uint8_t data = *cmd; + *cmd<<=1; + if(data&0x80) { + BITBAND(SD_CMDREG->FIOSET, SD_CMDPIN) = 1; + } else { + BITBAND(SD_CMDREG->FIOCLR, SD_CMDPIN) = 1; + } + wiggle_fast_pos(1); + } while (cmdshift); + cmd++; + } + + wiggle_fast_pos(1); + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 0; + + if(rsplen) { + uint16_t timeout=65535; + /* wait for responsebob */ + while((BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) && --timeout) { + wiggle_fast_neg(1); + } + // printf("timeout=%d\n", timeout); + if(!timeout) { + return 0; /* no response within timeout */ + } + + i=rsplen; + uint8_t cmddata=0, datdata=0; + while(i--) { /* process response */ + cmdshift = 8; + do { + if(dat) { + if(!(BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))) { +// printf("data start\n"); + j=datcnt; + state=1; + break; + } + } + cmdshift--; + cmddata |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << cmdshift; + wiggle_fast_neg(1); + } while (cmdshift); + if(state==1)break; + *rsp=cmddata; + cmddata=0; + rsp++; + } + + if(state==1) { /* process response+data */ + int startbit=1; + printf("processing rsp+data cmdshift=%d i=%d j=%d\n", cmdshift, i, j); + datshift=8; + while(1) { + cmdshift--; + cmddata |= (BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN)) << cmdshift; + if(!cmdshift) { + cmdshift=8; + *rsp=cmddata; + cmddata=0; + rsp++; + i--; + if(!i) { + printf("response end\n"); + if(j) state=2; /* response over, remaining data */ + break; + } + } + if(!startbit) { + datshift--; + datdata |= (BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) << datshift; + + if(!datshift) { + datshift=8; + *buf=datdata; + datdata=0; + buf++; + j--; + if(!j) break; + } + } + startbit=0; + wiggle_fast_neg(1); + } + } + + if(dat && state!=2) { /* response ended before data */ + state=2; + j=datcnt; + datshift=8; +// printf("response over, waiting for data...\n"); + while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { + wiggle_fast_neg(1); + } + wiggle_fast_neg(1); /* eat the start bit */ + } + + if(state==2) { /* transfer rest of data */ +// printf("remaining data: %d\n", j); + while(1) { + datshift-=4; + datdata |= ((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) + |((SD_DAT1REG->FIOPIN >> 13) & 0x6) + |((BITBAND(SD_DAT3REG->FIOPIN, SD_DAT3PIN)) << 3)) << datshift; + if(!datshift) { + datshift=8; + *buf=datdata; + datdata=0; + buf++; + j--; + if(!j) break; + } + wiggle_fast_neg(1); + } + } + /* just eat the crcs for now */ + wiggle_fast_neg(17); + state=3; + } + return rsplen; +} + + +void make_crc7(uint8_t* cmd) { + cmd[5]=crc7update(0, cmd[0]); + cmd[5]=crc7update(cmd[5], cmd[1]); + cmd[5]=crc7update(cmd[5], cmd[2]); + cmd[5]=crc7update(cmd[5], cmd[3]); + cmd[5]=crc7update(cmd[5], cmd[4]); + cmd[5]=(cmd[5] << 1) | 1; +} + +void stream_datablock(uint8_t* buf) { + uint8_t datshift=8; + int j=512; + uint8_t datdata=0; + uint16_t timeout=65535; + + while((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) && --timeout) { + wiggle_fast_neg(1); + } + wiggle_fast_neg(1); /* eat the start bit */ + + while(1) { + datshift-=4; + datdata |= ((BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN)) + |((SD_DAT1REG->FIOPIN >> 13) & 0x6) + |((BITBAND(SD_DAT3REG->FIOPIN, SD_DAT3PIN)) << 3)) << datshift; + if(!datshift) { + datshift=8; + *buf=datdata; + datdata=0; + buf++; + j--; + if(!j) break; + } + wiggle_fast_neg(1); + } + + /* eat the crc for now */ + wiggle_fast_neg(17); +} + +void read_block(uint32_t address, uint8_t* buf) { + if(during_blocktrans && (last_block == address-1)) { + stream_datablock(buf); + last_block=address; + } else { + if(during_blocktrans) { + /* send STOP_TRANSMISSION */ + cmd[0]=0x40+STOP_TRANSMISSION; + cmd[1]=0; + cmd[2]=0; + cmd[3]=0; + cmd[4]=0; + cmd[5]=0x61; + send_command_fast(cmd, rsp, NULL); + } + last_block=address; + if(!ccs) address <<= 9; + cmd[0]=0x40+READ_MULTIPLE_BLOCK; + cmd[1]=address>>24; + cmd[2]=address>>16; + cmd[3]=address>>8; + cmd[4]=address; + make_crc7(cmd); + send_command_fast(cmd, rsp, buf); +// uart_trace(cmd, 0, 6); +// uart_trace(rsp, 0, rsplen); + during_blocktrans = 1; + } +// uart_trace(buf, 0, 512); +} + +// +// Public functions +// + +DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count) { + uint8_t sec; + if(drv >= MAX_CARDS) { + return RES_PARERR; + } + for(sec=0; sec=MAX_CARDS) + return STA_NOINIT|STA_NODISK; + + data=BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN); + /* if the card is sending data from before a reset we try to deselect it + prior to initialization */ + for(rsplen=0; rsplen<1042; rsplen++) { + if((data != BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN))) { + printf("card seems to be sending data, attempting deselect\n"); + cmd[0]=0x40+7; + cmd[1]=0; + cmd[2]=0; + cmd[3]=0; + cmd[4]=0; + make_crc7(cmd); + if(send_command_slow(cmd, rsp)) { + printf("card was sending data, CMD7 succeeded\n"); + } else { + printf("CMD7 deselect no response! D:\n"); + } + } + data=BITBAND(SD_DAT0REG->FIOPIN, SD_DAT0PIN); + wiggle_slow_neg(1); + } + cmd[0]=0x40+GO_IDLE_STATE; + cmd[5]=0x95; + printf("sd_init start\n"); + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD0 response?!:\n"); +// uart_trace(rsp, 0, rsplen); + } + + wiggle_slow_pos(1000); + cmd[0]=0x40+SEND_IF_COND; + cmd[3]=0x01; + cmd[4]=0xaa; + cmd[5]=0x87; + if((rsplen=send_command_slow(cmd, rsp))) { +// uart_trace(cmd, 0, 6); +// printf("CMD8 response:\n"); +// uart_trace(rsp, 0, rsplen); + hcs=1; + } + while(1) { + cmd[0]=0x40+APP_CMD; + cmd[1]=0; + cmd[2]=0; + cmd[3]=0; + cmd[4]=0; + cmd[5]=0x65; + + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD55 response:\n"); +// uart_trace(rsp, 0, rsplen); + } else { + printf("CMD55 no response!\n"); + } + + cmd[0]=0x40+41; + cmd[1]=hcs<<6; + cmd[2]=0xfc; /* 2.7-3.6V */ + cmd[3]=0x00; + cmd[4]=0x00; + cmd[5]=hcs ? 0x53 : 0xc1; +// printf("send ACMD41 hcs=%d\n", hcs); + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("ACMD41 response:\n"); +// uart_trace(rsp, 0, rsplen); +// printf("busy=%d\n ccs=%d\n", rsp[1]>>7, (rsp[1]>>6)&1); + } else { + printf("ACMD41 no response!\n"); + } + if(rsp[1]&0x80) break; + } + + ccs = (rsp[1]>>6) & 1; /* SDHC */ + + cmd[0]=0x40+2; + cmd[1]=0; + cmd[2]=0; + cmd[3]=0; + cmd[4]=0; + cmd[5]=0x4d; + + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD2 response:\n"); +// uart_trace(rsp, 0, rsplen); + } else { + printf("CMD2 no response!\n"); + } + + cmd[0]=0x40+3; + cmd[1]=0; + cmd[2]=0; + cmd[3]=0; + cmd[4]=0; + cmd[5]=0x21; + + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD3 response:\n"); +// uart_trace(rsp, 0, rsplen); + rca1=rsp[1]; + rca2=rsp[2]; +// printf("RCA: %02x%02x\n", rca1, rca2); + } else { + printf("CMD3 no response!\n"); + rca1=0; + rca2=0; + } + + cmd[0]=0x40+9; + cmd[1]=rca1; + cmd[2]=rca2; + cmd[3]=0; + cmd[4]=0; + make_crc7(cmd); + + if((rsplen=send_command_slow(cmd, csd))) { +// printf("CMD9 response:\n"); +// uart_trace(rsp, 0, rsplen); + } else { + printf("CMD9 no response!\n"); + } + + cmd[0]=0x40+7; + cmd[1]=rca1; + cmd[2]=rca2; + cmd[3]=0; + cmd[4]=0; + make_crc7(cmd); + + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD7 response:\n"); +// uart_trace(rsp, 0, rsplen); + printf("card selected!\n"); + } else { + printf("CMD7 no response!\n"); + } + + cmd[0]=0x40+13; + cmd[1]=rca1; + cmd[2]=rca2; + cmd[3]=0; + cmd[4]=0; + make_crc7(cmd); + + if((rsplen=send_command_fast(cmd, rsp, NULL))) { +// printf("CMD13 response:\n"); +// uart_trace(rsp, 0, rsplen); + } else { + printf("CMD13 no response!\n"); + } + + cmd[0]=0x40+55; + cmd[1]=rca1; + cmd[2]=rca2; + cmd[3]=0; + cmd[4]=0; + make_crc7(cmd); + + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD55 response:\n"); +// uart_trace(rsp, 0, rsplen); + } else { + printf("CMD55 no response!\n"); + } + + cmd[0]=0x40+6; + cmd[1]=0; + cmd[2]=0; + cmd[3]=0; + cmd[4]=2; + make_crc7(cmd); + if((rsplen=send_command_slow(cmd, rsp))) { +// printf("CMD55 response:\n"); +// uart_trace(rsp, 0, rsplen); + } else { + printf("ACMD6 no response!\n"); + } + +/* int i; + printf("start 4MB streaming test\n"); + for(i=0; i<8192; i++) { + read_block(i, file_buf); + } + printf("end 4MB streaming test\n");*/ + printf("SD init complete. SDHC/XC=%d\n", ccs); + + return sdn_status(drv); +} + +DSTATUS disk_initialize(BYTE drv) __attribute__ ((weak, alias("sdn_initialize"))); + +void sdn_init(void) { + /* enable GPIO interrupt on SD detect pin, both edges */ + NVIC_EnableIRQ(EINT3_IRQn); + SD_DT_INT_SETUP(); + /* disconnect SSP1 */ + LPC_PINCON->PINSEL0 &= ~(BV(13) | BV(15) | BV(17) | BV(19)); + /* prepare GPIOs */ + BITBAND(SD_DAT3REG->FIODIR, SD_DAT3PIN) = 0; + BITBAND(SD_DAT2REG->FIODIR, SD_DAT2PIN) = 0; + BITBAND(SD_DAT1REG->FIODIR, SD_DAT1PIN) = 0; + BITBAND(SD_DAT0REG->FIODIR, SD_DAT0PIN) = 0; + BITBAND(SD_CLKREG->FIODIR, SD_CLKPIN) = 1; + BITBAND(SD_CMDREG->FIODIR, SD_CMDPIN) = 1; + BITBAND(SD_CMDREG->FIOPIN, SD_CMDPIN) = 1; +} +void disk_init(void) __attribute__ ((weak, alias("sdn_init"))); + + +DSTATUS sdn_status(BYTE drv) { + if (SDCARD_DETECT) + if (SDCARD_WP) + return STA_PROTECT; + else + return RES_OK; + else + return STA_NOINIT|STA_NODISK; +} +DSTATUS disk_status(BYTE drv) __attribute__ ((weak, alias("sdn_status"))); + +DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer) { + uint32_t capacity; + + if (drv >= MAX_CARDS) + return RES_NOTRDY; + + if (sdn_status(drv) & STA_NODISK) + return RES_NOTRDY; + + if (page != 0) + return RES_ERROR; + + if (ccs) { + /* Special CSD for SDHC cards */ + capacity = (1 + getbits(csd,127-69+8,22)) * 1024; + } else { + /* Assume that MMC-CSD 1.0/1.1/1.2 and SD-CSD 1.1 are the same... */ + uint8_t exponent = 2 + getbits(csd, 127-49+8, 3); + capacity = 1 + getbits(csd, 127-73+8, 12); + exponent += getbits(csd, 127-83+8,4) - 9; + while (exponent--) capacity *= 2; + } + + diskinfo0_t *di = buffer; + di->validbytes = sizeof(diskinfo0_t); + di->disktype = DISK_TYPE_SD; + di->sectorsize = 2; + di->sectorcount = capacity; + return RES_OK; +} +DRESULT disk_getinfo(BYTE drv, BYTE page, void *buffer) __attribute__ ((weak, alias("sdn_getinfo"))); + +DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count) { + return RES_OK; +} +DRESULT disk_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count) __attribute__ ((weak, alias("sdn_write"))); + +/* Detect changes of SD card 0 */ +void sdn_changed() { + if (SDCARD_DETECT) + disk_state = DISK_CHANGED; + else + disk_state = DISK_REMOVED; +} + diff --git a/src/sdnative.h b/src/sdnative.h new file mode 100644 index 0000000..9086917 --- /dev/null +++ b/src/sdnative.h @@ -0,0 +1,19 @@ +/* DISCLAIMER */ + +#ifndef SDNATIVE_H +#define SDNATIVE_H + +#include "diskio.h" + +/* These functions are weak-aliased to disk_... */ +void sdn_init(void); +DSTATUS sdn_status(BYTE drv); +DSTATUS sdn_initialize(BYTE drv); +DRESULT sdn_read(BYTE drv, BYTE *buffer, DWORD sector, BYTE count); +DRESULT sdn_write(BYTE drv, const BYTE *buffer, DWORD sector, BYTE count); +DRESULT sdn_getinfo(BYTE drv, BYTE page, void *buffer); + +void sdn_changed(void); + +#endif + diff --git a/src/smc.c b/src/smc.c index 7e79de8..d3120a9 100644 --- a/src/smc.c +++ b/src/smc.c @@ -98,7 +98,7 @@ void smc_id(snes_romprops_t* props) { } } } -printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */ +//printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */ if(score>=maxscore) { score_idx=num; maxscore=score; @@ -166,7 +166,6 @@ printf("%d: offset = %lX; score = %d\n", num, hdr_addr[num], score); // */ props->ramsize_bytes = 0; } /*dprintf("ramsize_bytes: %ld\n", props->ramsize_bytes); */ - f_lseek(&file_handle, 0); } uint8_t smc_headerscore(snes_header_t* header) { diff --git a/src/spi.c b/src/spi.c index d2847d0..9358478 100644 --- a/src/spi.c +++ b/src/spi.c @@ -154,7 +154,7 @@ void spi_tx_block(const void *ptr, unsigned int length, int device) { ssp_props *ssp = &(SSP_SEL[device]); while (length--) { - /* Wait until TX fifo can accept data */ + /* Wait until TX fifo can accept data */ while (!BITBAND(ssp->SSP_REGS->SR, SSP_TNF)) ; ssp->SSP_REGS->DR = *data++; diff --git a/src/timer.c b/src/timer.c index 0b7da98..b2f1665 100644 --- a/src/timer.c +++ b/src/timer.c @@ -47,11 +47,9 @@ void timer_init(void) { BITBAND(LPC_SC->PCLKSEL1, 26) = 1; BITBAND(LPC_SC->PCLKSEL1, PCLK_TIMER3) = 1; /* enable SysTick */ -// XXX SysTick_Config(SysTick->CALIB & SysTick_CALIB_TENMS_Msk); + SysTick_Config(SysTick->CALIB & SysTick_CALIB_TENMS_Msk); } -extern int testval; - void delay_us(unsigned int time) { /* Prepare RIT */ LPC_RIT->RICOUNTER = 0; diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v index 56ddf6b..5defd3f 100644 --- a/verilog/sd2snes/address.v +++ b/verilog/sd2snes/address.v @@ -14,66 +14,56 @@ // Dependencies: // // Revision: -// Revision 0.02 - All new combinatorial glory. fucking slow. // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module address( input CLK, - input [2:0] MAPPER, // AVR detected mapper + input [2:0] MAPPER, // MCU detected mapper input [23:0] SNES_ADDR, // requested address from SNES input SNES_CS, // "CART" pin from SNES (active low) - output [19:0] SRAM_ADDR, // Address to request from SRAM - output [3:0] ROM_SEL, // which SRAM unit to access (active low) - input AVR_ENA, // enable AVR master mode (active low) - input MODE, // AVR(1) or SNES(0) ("bus phase") + output [22:0] ROM_ADDR, // Address to request from SRAM0 + output ROM_SEL, // enable SRAM0 (active low) + input MCU_OVR, // enable MCU master mode (active low) + input MODE, // MCU(1) or SNES(0) ("bus phase") output IS_SAVERAM, // address/CS mapped as SRAM? output IS_ROM, // address mapped as ROM? - input [23:0] AVR_ADDR, // allow address to be set externally + input [23:0] MCU_ADDR, // allow address to be set externally input ADDR_WRITE, - output SRAM_ADDR0, + output ROM_ADDR0, input [23:0] SAVERAM_MASK, input [23:0] ROM_MASK ); -reg [3:0] AVR_ROM_SEL_BUF; -reg [3:0] CS_ARRAY[3:0]; wire [1:0] SRAM_BANK; -wire [3:0] CURRENT_ROM_SEL; -wire [22:0] SRAM_ADDR_FULL; - -initial begin - CS_ARRAY[0] = 4'b0001; - CS_ARRAY[1] = 4'b0010; - CS_ARRAY[2] = 4'b0100; - CS_ARRAY[3] = 4'b1000; -end +wire [23:0] SRAM_ADDR_FULL; /* currently supported mappers: Index Mapper 000 HiROM 001 LoROM 010 ExHiROM (48-64Mbit) - + 110 brainfuck interleaved 96MBit Star Ocean =) 111 menu (ROM in upper SRAM) */ /* HiROM: SRAM @ Bank 0x30-0x3f, 0xb0-0xbf Offset 6000-7fff */ -assign IS_ROM = ( (MAPPER == 3'b000) ? ( (!SNES_ADDR[22] - & SNES_ADDR[15]) +assign IS_ROM = ( (MAPPER == 3'b000) ? ((!SNES_ADDR[22] & SNES_ADDR[15]) |(SNES_ADDR[22])) - : (MAPPER == 3'b001) ? ( (SNES_ADDR[15] & !SNES_ADDR[22]) - |(SNES_ADDR[22])) + : (MAPPER == 3'b001) ? ((!SNES_ADDR[22] & SNES_ADDR[15]) + |(SNES_ADDR[22])) : (MAPPER == 3'b010) ? ((!SNES_ADDR[22] & SNES_ADDR[15]) |(SNES_ADDR[22])) + : (MAPPER == 3'b110) ? ((!SNES_ADDR[22] & SNES_ADDR[15]) + |(SNES_ADDR[22])) : (MAPPER == 3'b111) ? ((!SNES_ADDR[22] & SNES_ADDR[15]) |(SNES_ADDR[22])) : 1'b0); -assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b111) ? (!SNES_ADDR[22] +assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b110 || MAPPER == 3'b111) ? (!SNES_ADDR[22] & SNES_ADDR[21:20] & &SNES_ADDR[14:13] & !SNES_ADDR[15] @@ -88,26 +78,29 @@ assign IS_SAVERAM = ((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b111) & !SNES_CS) : 1'b0); -assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR +assign SRAM_ADDR_FULL = (MODE) ? MCU_ADDR : ((MAPPER == 3'b000) ? - (IS_SAVERAM ? (SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK - : (SNES_ADDR[22:0] & ROM_MASK)) + (IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK) + : ({1'b0, SNES_ADDR[22:0]} & ROM_MASK)) :(MAPPER == 3'b001) ? - (IS_SAVERAM ? SNES_ADDR[14:0] & SAVERAM_MASK - : ({1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK)) + (IS_SAVERAM ? 24'hE00000 + (SNES_ADDR[14:0] & SAVERAM_MASK) + : ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK)) :(MAPPER == 3'b010) ? - (IS_SAVERAM ? (SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK - : ({!SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK)) + (IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK) + : ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK)) + :(MAPPER == 3'b110) ? + (IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK) + : (SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]}) + : ({2'b10, SNES_ADDR[23], SNES_ADDR[21:16], SNES_ADDR[14:0]}))) :(MAPPER == 3'b111) ? - (IS_SAVERAM ? 23'h7F0000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK) - : ((SNES_ADDR[22:0] & ROM_MASK) + 23'h600000)) - : 23'b0); + (IS_SAVERAM ? 24'hFF0000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK) + : (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) + 24'hE00000)) + : 24'b0); -assign SRAM_BANK = SRAM_ADDR_FULL[22:21]; -assign SRAM_ADDR = SRAM_ADDR_FULL[20:1]; +assign ROM_ADDR = SRAM_ADDR_FULL[23:1]; -assign ROM_SEL = (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK]; +assign ROM_SEL = 1'b0; // (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK]; -assign SRAM_ADDR0 = SRAM_ADDR_FULL[0]; +assign ROM_ADDR0 = SRAM_ADDR_FULL[0]; endmodule diff --git a/verilog/sd2snes/avr_cmd.v b/verilog/sd2snes/avr_cmd.v index 523c974..6b732fa 100644 --- a/verilog/sd2snes/avr_cmd.v +++ b/verilog/sd2snes/avr_cmd.v @@ -5,7 +5,7 @@ // // Create Date: 21:57:50 08/25/2009 // Design Name: -// Module Name: avr_cmd +// Module Name: mcu_cmd // Project Name: // Target Devices: // Tool versions: @@ -18,18 +18,18 @@ // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// -module avr_cmd( +module mcu_cmd( input clk, input cmd_ready, input param_ready, input [7:0] cmd_data, input [7:0] param_data, - output [3:0] avr_mapper, - output [3:0] avr_sram_size, - output avr_read, - output avr_write, - output [7:0] avr_data_out, - input [7:0] avr_data_in, + output [3:0] mcu_mapper, + output [3:0] mcu_sram_size, + output mcu_read, + output mcu_write, + output [7:0] mcu_data_out, + input [7:0] mcu_data_in, output [7:0] spi_data_out, input [31:0] spi_byte_cnt, input [2:0] spi_bit_cnt, @@ -49,13 +49,13 @@ module avr_cmd( reg [3:0] MAPPER_BUF; reg [3:0] SRAM_SIZE_BUF; -reg AVR_READ_BUF; -reg AVR_WRITE_BUF; +reg MCU_READ_BUF; +reg MCU_WRITE_BUF; reg [23:0] ADDR_OUT_BUF; -reg [7:0] AVR_DATA_OUT_BUF; -reg [7:0] AVR_DATA_IN_BUF; -reg [1:0] avr_nextaddr_buf; -wire avr_nextaddr; +reg [7:0] MCU_DATA_OUT_BUF; +reg [7:0] MCU_DATA_IN_BUF; +reg [1:0] mcu_nextaddr_buf; +wire mcu_nextaddr; wire spi_dma_nextaddr_trig; reg [2:0] spi_dma_nextaddr_r; @@ -63,7 +63,7 @@ reg [1:0] SRAM_MASK_IDX; reg [23:0] SAVERAM_MASK; reg [23:0] ROM_MASK; -assign spi_data_out = AVR_DATA_IN_BUF; +assign spi_data_out = MCU_DATA_IN_BUF; initial begin ADDR_OUT_BUF = 0; @@ -109,28 +109,30 @@ always @(posedge clk) begin SAVERAM_MASK[7:0] <= param_data; endcase 4'h9: - AVR_DATA_OUT_BUF <= param_data; + MCU_DATA_OUT_BUF <= param_data; endcase end - if (spi_dma_nextaddr_trig | (avr_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[0]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) + if (spi_dma_nextaddr_trig | (mcu_nextaddr & (cmd_data[7:5] == 3'h4) && (cmd_data[0]) && (spi_byte_cnt > (32'h1+cmd_data[4])))) ADDR_OUT_BUF <= ADDR_OUT_BUF + 1; end // value fetch during last SPI bit always @(posedge clk) begin if (spi_bit_cnt == 3'h7) - if (cmd_data[7:4] == 4'hF) - AVR_DATA_IN_BUF <= 8'hA5; - else - AVR_DATA_IN_BUF <= avr_data_in; + if (cmd_data[7:0] == 8'hF0) + MCU_DATA_IN_BUF <= 8'hA5; + else if (cmd_data[7:0] == 8'hFF) + MCU_DATA_IN_BUF <= param_data; + else + MCU_DATA_IN_BUF <= mcu_data_in; end // nextaddr pulse generation always @(posedge clk) begin if (spi_bit_cnt == 3'h0) - avr_nextaddr_buf <= {avr_nextaddr_buf[0], 1'b1}; + mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b1}; else - avr_nextaddr_buf <= {avr_nextaddr_buf[0], 1'b0}; + mcu_nextaddr_buf <= {mcu_nextaddr_buf[0], 1'b0}; end assign spi_dma_nextaddr_trig = (spi_dma_nextaddr_r[2:1] == 2'b01); @@ -141,27 +143,27 @@ end // r/w pulse always @(posedge clk) begin if ((spi_bit_cnt == 3'h1 || spi_bit_cnt == 3'h2 || spi_bit_cnt == 3'h3) & (cmd_data[7:4] == 4'h9) & (spi_byte_cnt > 32'h1)) - AVR_WRITE_BUF <= 1'b0; + MCU_WRITE_BUF <= 1'b0; else - AVR_WRITE_BUF <= 1'b1; + MCU_WRITE_BUF <= 1'b1; // Read pulse is two spi cycles to ensure that the value -// is ready in the 2nd cycle in AVR master mode +// is ready in the 2nd cycle in MCU master mode if ((spi_bit_cnt == 3'h5 || spi_bit_cnt == 3'h6 || spi_bit_cnt == 3'h7) & (cmd_data[7:4] == 4'h8) & (spi_byte_cnt > 32'h0)) - AVR_READ_BUF <= 1'b0; + MCU_READ_BUF <= 1'b0; else - AVR_READ_BUF <= 1'b1; + MCU_READ_BUF <= 1'b1; end // trigger for nextaddr -assign avr_nextaddr = avr_nextaddr_buf == 2'b01; +assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01; -assign avr_read = AVR_READ_BUF; -assign avr_write = spi_dma_ovr ? spi_dma_sram_we : AVR_WRITE_BUF; +assign mcu_read = MCU_READ_BUF; +assign mcu_write = spi_dma_ovr ? spi_dma_sram_we : MCU_WRITE_BUF; assign addr_out = ADDR_OUT_BUF; -assign avr_data_out = spi_dma_ovr ? spi_dma_sram_data : AVR_DATA_OUT_BUF; -assign avr_mapper = MAPPER_BUF; -assign avr_sram_size = SRAM_SIZE_BUF; +assign mcu_data_out = spi_dma_ovr ? spi_dma_sram_data : MCU_DATA_OUT_BUF; +assign mcu_mapper = MAPPER_BUF; +assign mcu_sram_size = SRAM_SIZE_BUF; assign rom_mask_out = ROM_MASK; assign saveram_mask_out = SAVERAM_MASK; diff --git a/verilog/sd2snes/data.v b/verilog/sd2snes/data.v index 6067334..d3f405f 100644 --- a/verilog/sd2snes/data.v +++ b/verilog/sd2snes/data.v @@ -22,52 +22,52 @@ module data( input CLK, input SNES_READ, input SNES_WRITE, - input AVR_READ, - input AVR_WRITE, + input MCU_READ, + input MCU_WRITE, inout [7:0] SNES_DATA, - inout [15:0] SRAM_DATA, - input [7:0] AVR_IN_DATA, - output [7:0] AVR_OUT_DATA, + inout [15:0] ROM_DATA, + input [7:0] MCU_IN_DATA, + output [7:0] MCU_OUT_DATA, input MODE, input SNES_DATA_TO_MEM, - input AVR_DATA_TO_MEM, - input SRAM_DATA_TO_SNES_MEM, - input SRAM_DATA_TO_AVR_MEM, - input AVR_ENA, - input SRAM_ADDR0 + input MCU_DATA_TO_MEM, + input ROM_DATA_TO_SNES_MEM, + input ROM_DATA_TO_MCU_MEM, + input MCU_OVR, + input ROM_ADDR0 ); reg [7:0] SNES_IN_MEM; reg [7:0] SNES_OUT_MEM; -reg [7:0] AVR_IN_MEM; -reg [7:0] AVR_OUT_MEM; +reg [7:0] MCU_IN_MEM; +reg [7:0] MCU_OUT_MEM; -wire [7:0] FROM_SRAM_BYTE; +wire [7:0] FROM_ROM_BYTE; assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM; -assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]); +assign FROM_ROM_BYTE = (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]); -assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE) - : (AVR_OUT_MEM); +assign MCU_OUT_DATA = !MCU_OVR ? (FROM_ROM_BYTE) + : (MCU_OUT_MEM); -assign SRAM_DATA[7:0] = SRAM_ADDR0 ? (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) - : (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ) +assign ROM_DATA[7:0] = ROM_ADDR0 ? (!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ) + : (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ) : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ))) : 8'bZ; -assign SRAM_DATA[15:8] = SRAM_ADDR0 ? 8'bZ : (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) - : (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ) +assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ : (!MCU_OVR ? (!MCU_WRITE ? MCU_IN_DATA : 8'bZ) + : (MODE ? (!MCU_WRITE ? MCU_IN_MEM : 8'bZ) : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ))); always @(posedge CLK) begin if(SNES_DATA_TO_MEM) SNES_IN_MEM <= SNES_DATA; - if(AVR_DATA_TO_MEM) - AVR_IN_MEM <= AVR_IN_DATA; - if(SRAM_DATA_TO_SNES_MEM) - SNES_OUT_MEM <= FROM_SRAM_BYTE; - if(SRAM_DATA_TO_AVR_MEM) - AVR_OUT_MEM <= FROM_SRAM_BYTE; + if(MCU_DATA_TO_MEM) + MCU_IN_MEM <= MCU_IN_DATA; + if(ROM_DATA_TO_SNES_MEM) + SNES_OUT_MEM <= FROM_ROM_BYTE; + if(ROM_DATA_TO_MCU_MEM) + MCU_OUT_MEM <= FROM_ROM_BYTE; end endmodule diff --git a/verilog/sd2snes/dcm.v b/verilog/sd2snes/dcm.v index 1df56ef..6399370 100644 --- a/verilog/sd2snes/dcm.v +++ b/verilog/sd2snes/dcm.v @@ -35,9 +35,9 @@ module my_dcm ( .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 - .CLKFX_MULTIPLY(7), // Can be any integer from 2 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature - .CLKIN_PERIOD(81.380), // Specify period of input clock + .CLKIN_PERIOD(44.289), // Specify period of input clock .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index d943775..dd0007d 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -1,140 +1,13 @@ NET "CLKIN" TNM_NET = CLKIN; -TIMESPEC TS_CLKIN = PERIOD "CLKIN" 12.288 MHz HIGH 50 %; -NET "AVR_ENA" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33; -NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33; +TIMESPEC TS_CLKIN = PERIOD "CLKIN" 22.579 MHz HIGH 50 %; NET "SNES_CS" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[3]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[4]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[5]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33; -NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33; NET "SNES_READ" IOSTANDARD = LVCMOS33; NET "SNES_WRITE" IOSTANDARD = LVCMOS33; NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33; NET "SNES_REFRESH" IOSTANDARD = LVCMOS33; -NET "SPI_MISO" IOSTANDARD = LVCMOS33; -NET "SPI_MOSI" IOSTANDARD = LVCMOS33; -NET "AVR_ENA" LOC = P58; -NET "CLKIN" LOC = P125; -NET "IRQ_DIR" LOC = P40; -NET "SNES_ADDR[0]" LOC = P7; -NET "SNES_ADDR[10]" LOC = P32; -NET "SNES_ADDR[11]" LOC = P35; -NET "SNES_ADDR[12]" LOC = P33; -NET "SNES_ADDR[13]" LOC = P31; -NET "SNES_ADDR[14]" LOC = P28; -NET "SNES_ADDR[15]" LOC = P26; -NET "SNES_ADDR[16]" LOC = P24; -NET "SNES_ADDR[17]" LOC = P21; -NET "SNES_ADDR[18]" LOC = P18; -NET "SNES_ADDR[19]" LOC = P15; -NET "SNES_ADDR[1]" LOC = P10; -NET "SNES_ADDR[20]" LOC = P13; -NET "SNES_ADDR[21]" LOC = P11; -NET "SNES_ADDR[22]" LOC = P8; -NET "SNES_ADDR[23]" LOC = P6; -NET "SNES_ADDR[2]" LOC = P12; -NET "SNES_ADDR[3]" LOC = P14; -NET "SNES_ADDR[4]" LOC = P17; -NET "SNES_ADDR[5]" LOC = P20; -NET "SNES_ADDR[6]" LOC = P23; -NET "SNES_ADDR[7]" LOC = P25; -NET "SNES_ADDR[8]" LOC = P27; -NET "SNES_ADDR[9]" LOC = P30; -NET "SNES_CPU_CLK" LOC = P1; -NET "SNES_CS" LOC = P5; -NET "SNES_READ" LOC = P2; -NET "SNES_REFRESH" LOC = P36; -NET "SNES_WRITE" LOC = P4; -NET "SPI_SS" LOC = P65; -NET "SRAM_ADDR[10]" LOC = P60; -NET "SRAM_ADDR[11]" LOC = P59; -NET "SRAM_ADDR[12]" LOC = P57; -NET "SRAM_ADDR[13]" LOC = P56; -NET "SRAM_ADDR[14]" LOC = P51; -NET "SRAM_ADDR[15]" LOC = P50; -NET "SRAM_ADDR[19]" LOC = P69; -NET "SRAM_ADDR[8]" LOC = P68; -NET "SRAM_ADDR[9]" LOC = P63; -NET "SRAM_CE2[0]" LOC = P77; -NET "SRAM_CE2[1]" LOC = P76; -NET "SRAM_CE2[2]" LOC = P74; -NET "SRAM_CE2[3]" LOC = P73; -NET "SRAM_WE" LOC = P70; -NET "SNES_DATABUS_DIR" LOC = P141; -NET "SNES_DATABUS_OE" LOC = P140; -NET "SNES_DATA[0]" LOC = P137; -NET "SNES_DATA[1]" LOC = P132; -NET "SNES_DATA[2]" LOC = P130; -NET "SNES_DATA[3]" LOC = P128; -NET "SNES_DATA[4]" LOC = P135; -NET "SNES_DATA[5]" LOC = P131; -NET "SNES_DATA[6]" LOC = P129; -NET "SNES_DATA[7]" LOC = P127; -NET "SNES_IRQ" LOC = P55; -NET "SPI_MISO" LOC = P123; -NET "SPI_MOSI" LOC = P122; -NET "SPI_SCK" LOC = P124; -NET "SRAM_ADDR[0]" LOC = P92; -NET "SRAM_ADDR[16]" LOC = P119; -NET "SRAM_ADDR[17]" LOC = P82; -NET "SRAM_ADDR[18]" LOC = P80; -NET "SRAM_ADDR[1]" LOC = P90; -NET "SRAM_ADDR[2]" LOC = P89; -NET "SRAM_ADDR[3]" LOC = P87; -NET "SRAM_ADDR[4]" LOC = P86; -NET "SRAM_ADDR[5]" LOC = P85; -NET "SRAM_ADDR[6]" LOC = P84; -NET "SRAM_ADDR[7]" LOC = P83; -NET "SRAM_BHE" LOC = P78; -NET "SRAM_BLE" LOC = P79; -NET "SRAM_DATA[0]" LOC = P95; -NET "SRAM_DATA[10]" LOC = P100; -NET "SRAM_DATA[11]" LOC = P103; -NET "SRAM_DATA[12]" LOC = P105; -NET "SRAM_DATA[13]" LOC = P108; -NET "SRAM_DATA[14]" LOC = P113; -NET "SRAM_DATA[15]" LOC = P118; -NET "SRAM_DATA[1]" LOC = P97; -NET "SRAM_DATA[2]" LOC = P99; -NET "SRAM_DATA[3]" LOC = P102; -NET "SRAM_DATA[4]" LOC = P104; -NET "SRAM_DATA[5]" LOC = P107; -NET "SRAM_DATA[6]" LOC = P112; -NET "SRAM_DATA[7]" LOC = P116; -NET "SRAM_DATA[8]" LOC = P96; -NET "SRAM_DATA[9]" LOC = P98; -NET "SRAM_OE" LOC = P93; NET "CLKIN" IOSTANDARD = LVCMOS33; //NET "CLKIN" PULLUP; -NET "SPI_SS" IOSTANDARD = LVCMOS33; NET "SPI_SS" PULLUP; //NET "DCM_RST" LOC = P46; //NET "DCM_RST" IOSTANDARD = LVCMOS33; @@ -142,53 +15,597 @@ NET "IRQ_DIR" IOSTANDARD = LVCMOS33; NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33; NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33; NET "SNES_IRQ" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[0]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[10]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[11]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[12]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[13]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[14]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[15]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[16]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[17]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[18]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[19]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[1]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[2]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[3]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[4]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[5]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[6]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[7]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[8]" IOSTANDARD = LVCMOS33; -NET "SRAM_ADDR[9]" IOSTANDARD = LVCMOS33; -NET "SRAM_BHE" IOSTANDARD = LVCMOS33; -NET "SRAM_BLE" IOSTANDARD = LVCMOS33; -NET "SRAM_CE2[0]" IOSTANDARD = LVCMOS33; -NET "SRAM_CE2[1]" IOSTANDARD = LVCMOS33; -NET "SRAM_CE2[2]" IOSTANDARD = LVCMOS33; -NET "SRAM_CE2[3]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[0]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[10]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[11]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[12]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[13]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[14]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[15]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[1]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[2]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[3]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[4]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[5]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[6]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[7]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[8]" IOSTANDARD = LVCMOS33; -NET "SRAM_DATA[9]" IOSTANDARD = LVCMOS33; -NET "SRAM_OE" IOSTANDARD = LVCMOS33; -NET "SRAM_WE" IOSTANDARD = LVCMOS33; -NET "SPI_DMA_CTRL" LOC = P41; -NET "SPI_DMA_CTRL" IOSTANDARD = LVCMOS33; NET "SPI_DMA_CTRL" PULLUP; + +# PlanAhead generated physical constraints + +NET "SNES_ADDR[0]" LOC = P119; +NET "SNES_ADDR[10]" LOC = P146; +NET "SNES_ADDR[11]" LOC = P148; +NET "SNES_ADDR[12]" LOC = P147; +NET "SNES_ADDR[13]" LOC = P144; +NET "SNES_ADDR[14]" LOC = P141; +NET "SNES_ADDR[15]" LOC = P139; +NET "SNES_ADDR[16]" LOC = P137; +NET "SNES_ADDR[17]" LOC = P133; +NET "SNES_ADDR[18]" LOC = P131; +NET "SNES_ADDR[19]" LOC = P128; +NET "SNES_ADDR[1]" LOC = P122; +NET "SNES_ADDR[20]" LOC = P125; +NET "SNES_ADDR[21]" LOC = P123; +NET "SNES_ADDR[22]" LOC = P120; +NET "SNES_ADDR[23]" LOC = P117; +NET "SNES_ADDR[2]" LOC = P124; +NET "SNES_ADDR[3]" LOC = P126; +NET "SNES_ADDR[4]" LOC = P130; +NET "SNES_ADDR[5]" LOC = P132; +NET "SNES_ADDR[6]" LOC = P135; +NET "SNES_ADDR[7]" LOC = P138; +NET "SNES_ADDR[8]" LOC = P140; +NET "SNES_ADDR[9]" LOC = P143; +NET "SNES_DATA[0]" LOC = P107; +NET "SNES_DATA[1]" LOC = P102; +NET "SNES_DATA[2]" LOC = P100; +NET "SNES_DATA[3]" LOC = P96; +NET "SNES_DATA[4]" LOC = P108; +NET "SNES_DATA[5]" LOC = P106; +NET "SNES_DATA[6]" LOC = P101; +NET "SNES_DATA[7]" LOC = P97; + +# PlanAhead generated physical constraints + +NET "CLKIN" LOC = P80; +NET "IRQ_DIR" LOC = P113; +NET "MCU_OVR" LOC = P92; + +# PlanAhead generated IO constraints + +NET "MCU_OVR" IOSTANDARD = LVCMOS33; +NET "MCU_OVR" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[0]" LOC = P166; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[0]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[10]" LOC = P197; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[10]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[11]" LOC = P196; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[11]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[12]" LOC = P2; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[12]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[13]" LOC = P194; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[13]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[14]" LOC = P200; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[14]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[15]" LOC = P184; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[15]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[16]" LOC = P199; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[16]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[17]" LOC = P11; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[17]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[18]" LOC = P3; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[18]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[19]" LOC = P4; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[19]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[1]" LOC = P168; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[1]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[20]" LOC = P191; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[20]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[20]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[21]" LOC = P203; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[21]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[21]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[22]" LOC = P198; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[22]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[22]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[2]" LOC = P171; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[2]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[3]" LOC = P165; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[3]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[4]" LOC = P169; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[4]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[5]" LOC = P18; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[5]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[6]" LOC = P175; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[6]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[7]" LOC = P167; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[7]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[8]" LOC = P205; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[8]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_ADDR[9]" LOC = P204; + +# PlanAhead generated IO constraints + +NET "ROM_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "ROM_ADDR[9]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_BHE" LOC = P161; + +# PlanAhead generated IO constraints + +NET "ROM_BHE" IOSTANDARD = LVCMOS33; +NET "ROM_BHE" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_BLE" LOC = P156; + +# PlanAhead generated IO constraints + +NET "ROM_BLE" IOSTANDARD = LVCMOS33; +NET "ROM_BLE" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_CE" LOC = P172; + +# PlanAhead generated IO constraints + +NET "ROM_CE" IOSTANDARD = LVCMOS33; +NET "ROM_CE" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[0]" LOC = P176; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[0]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[0]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[10]" LOC = P15; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[10]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[10]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[11]" LOC = P12; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[11]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[11]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[12]" LOC = P10; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[12]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[12]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[13]" LOC = P7; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[13]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[13]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[14]" LOC = P9; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[14]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[14]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[15]" LOC = P5; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[15]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[15]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[1]" LOC = P178; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[1]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[1]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[2]" LOC = P181; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[2]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[2]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[3]" LOC = P182; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[3]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[3]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[4]" LOC = P183; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[4]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[4]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[5]" LOC = P187; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[5]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[5]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[6]" LOC = P185; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[6]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[6]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[7]" LOC = P189; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[7]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[7]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[8]" LOC = P16; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[8]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[8]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_DATA[9]" LOC = P13; + +# PlanAhead generated IO constraints + +NET "ROM_DATA[9]" IOSTANDARD = LVCMOS33; +NET "ROM_DATA[9]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_OE" LOC = P162; + +# PlanAhead generated IO constraints + +NET "ROM_OE" IOSTANDARD = LVCMOS33; +NET "ROM_OE" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "ROM_WE" LOC = P190; + +# PlanAhead generated IO constraints + +NET "ROM_WE" IOSTANDARD = LVCMOS33; +NET "ROM_WE" DRIVE = 8; +NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[0]" DRIVE = 8; +NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[10]" DRIVE = 8; +NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[11]" DRIVE = 8; +NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[12]" DRIVE = 8; +NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[13]" DRIVE = 8; +NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[14]" DRIVE = 8; +NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[15]" DRIVE = 8; +NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[16]" DRIVE = 8; +NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[17]" DRIVE = 8; +NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[18]" DRIVE = 8; +NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[19]" DRIVE = 8; +NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[1]" DRIVE = 8; +NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[20]" DRIVE = 8; +NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[21]" DRIVE = 8; +NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[22]" DRIVE = 8; +NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[23]" DRIVE = 8; +NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[2]" DRIVE = 8; +NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[3]" DRIVE = 8; +NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[4]" DRIVE = 8; +NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[5]" DRIVE = 8; +NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[6]" DRIVE = 8; +NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[7]" DRIVE = 8; +NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[8]" DRIVE = 8; +NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33; +NET "SNES_ADDR[9]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "SNES_CPU_CLK" LOC = P94; +NET "SNES_CS" LOC = P116; +NET "SNES_DATABUS_DIR" LOC = P111; +NET "SNES_DATABUS_OE" LOC = P109; + +# PlanAhead generated IO constraints + +NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[0]" DRIVE = 8; +NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[1]" DRIVE = 8; +NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[2]" DRIVE = 8; +NET "SNES_DATA[3]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[3]" DRIVE = 8; +NET "SNES_DATA[4]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[4]" DRIVE = 8; +NET "SNES_DATA[5]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[5]" DRIVE = 8; +NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[6]" DRIVE = 8; +NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33; +NET "SNES_DATA[7]" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "SNES_IRQ" LOC = P114; +NET "SNES_READ" LOC = P115; +NET "SNES_REFRESH" LOC = P155; +NET "SNES_WRITE" LOC = P95; +NET "SPI_DMA_CTRL" LOC = P83; + +# PlanAhead generated IO constraints + +NET "SPI_DMA_CTRL" IOSTANDARD = LVCMOS33; +NET "SPI_DMA_CTRL" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "SPI_MISO" LOC = P72; + +# PlanAhead generated IO constraints + +NET "SPI_MISO" IOSTANDARD = LVCMOS33; +NET "SPI_MISO" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "SPI_MOSI" LOC = P74; + +# PlanAhead generated IO constraints + +NET "SPI_MOSI" IOSTANDARD = LVCMOS33; +NET "SPI_MOSI" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "SPI_SCK" LOC = P71; + +# PlanAhead generated IO constraints + NET "SPI_SCK" IOSTANDARD = LVCMOS33; -NET "SPI_SCK" DRIVE = 16; +NET "SPI_SCK" DRIVE = 8; NET "SPI_SCK" PULLUP; + +# PlanAhead generated physical constraints + +NET "SPI_SS" LOC = P68; + +# PlanAhead generated IO constraints + +NET "SPI_SS" IOSTANDARD = LVCMOS33; +NET "SPI_SS" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "DAC_LRCK" LOC = P77; + +# PlanAhead generated IO constraints + +NET "DAC_LRCK" IOSTANDARD = LVCMOS33; +NET "DAC_LRCK" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "DAC_MCLK" LOC = P76; + +# PlanAhead generated IO constraints + +NET "DAC_MCLK" IOSTANDARD = LVCMOS33; +NET "DAC_MCLK" DRIVE = 8; + +# PlanAhead generated physical constraints + +NET "DAC_SDOUT" LOC = P78; + +# PlanAhead generated IO constraints + +NET "DAC_SDOUT" IOSTANDARD = LVCMOS33; +NET "DAC_SDOUT" DRIVE = 8; diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 107bf4e..a034e40 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -36,22 +36,32 @@ module main( output IRQ_DIR, /* SRAM signals */ - inout [15:0] SRAM_DATA, - output [19:0] SRAM_ADDR, - output [3:0] SRAM_CE2, - output SRAM_OE, - output SRAM_WE, - output SRAM_BHE, - output SRAM_BLE, + inout [15:0] ROM_DATA, + output [22:0] ROM_ADDR, + output ROM_CE, + output ROM_OE, + output ROM_WE, + output ROM_BHE, + output ROM_BLE, - /* AVR signals */ + /* MCU signals */ input SPI_MOSI, inout SPI_MISO, input SPI_SS, inout SPI_SCK, - input AVR_ENA, - inout SPI_DMA_CTRL - + input MCU_OVR, + inout SPI_DMA_CTRL, + + output DAC_MCLK, + output DAC_LRCK, + output DAC_SDOUT, + + /* SD signals */ + inout SD_MOSI, + input SD_MISO, + inout SD_SS, + inout SD_SCK + /* debug */ //output DCM_IN_STOPPED, //output DCM_FX_STOPPED @@ -62,18 +72,24 @@ wire [7:0] spi_param_data; wire [7:0] spi_input_data; wire [31:0] spi_byte_cnt; wire [2:0] spi_bit_cnt; -wire [23:0] AVR_ADDR; -wire [7:0] avr_data_in; -wire [7:0] avr_data_out; -wire [7:0] AVR_IN_DATA; -wire [7:0] AVR_OUT_DATA; +wire [23:0] MCU_ADDR; +wire [7:0] mcu_data_in; +wire [7:0] mcu_data_out; +wire [7:0] MCU_IN_DATA; +wire [7:0] MCU_OUT_DATA; wire [3:0] MAPPER; wire [23:0] SAVERAM_MASK; wire [23:0] ROM_MASK; wire [23:0] spi_dma_addr; wire [7:0] spi_dma_sram_data; -wire spi_dma_trig = SPI_DMA_CTRL; +wire spi_dma_trig = 1'b1; //SPI_DMA_CTRL; +dac_test snes_dac_test(.clkin(CLK2), + .mclk(DAC_MCLK), + .lrck(DAC_LRCK), + .sdout(DAC_SDOUT) +); + spi snes_spi(.clk(CLK2), .MOSI(SPI_MOSI), .MISO(SPI_MISO), @@ -93,22 +109,22 @@ spi snes_spi(.clk(CLK2), .spi_dma_ovr(spi_dma_ovr) ); -avr_cmd snes_avr_cmd( +mcu_cmd snes_mcu_cmd( .clk(CLK2), .cmd_ready(spi_cmd_ready), .param_ready(spi_param_ready), .cmd_data(spi_cmd_data), .param_data(spi_param_data), - .avr_mapper(MAPPER), - .avr_sram_size(SRAM_SIZE), - .avr_read(AVR_READ), - .avr_write(AVR_WRITE), - .avr_data_in(AVR_OUT_DATA), - .avr_data_out(AVR_IN_DATA), + .mcu_mapper(MAPPER), + .mcu_sram_size(SRAM_SIZE), + .mcu_read(MCU_READ), + .mcu_write(MCU_WRITE), + .mcu_data_in(MCU_OUT_DATA), + .mcu_data_out(MCU_IN_DATA), .spi_byte_cnt(spi_byte_cnt), .spi_bit_cnt(spi_bit_cnt), .spi_data_out(spi_input_data), - .addr_out(AVR_ADDR), + .addr_out(MCU_ADDR), .endmessage(spi_endmessage), .startmessage(spi_startmessage), .saveram_mask_out(SAVERAM_MASK), @@ -122,14 +138,14 @@ avr_cmd snes_avr_cmd( spi_dma snes_spi_dma( .clk(CLK2), - .spi_dma_ovr(spi_dma_ovr), // to spi, avr_cmd + .spi_dma_ovr(spi_dma_ovr), // to spi, mcu_cmd .spi_dma_miso(SPI_MISO), // to spi .spi_dma_sck(spi_dma_sck), // to spi - .spi_dma_trig(spi_dma_trig), // from avr - .spi_dma_nextaddr(spi_dma_nextaddr), // to avr_cmd? - .spi_dma_sram_data(spi_dma_sram_data), // to avr_cmd? - .spi_dma_sram_we(spi_dma_sram_we), // to avr_cmd? - .spi_dma_done(spi_dma_done) // to avr + .spi_dma_trig(spi_dma_trig), // from mcu + .spi_dma_nextaddr(spi_dma_nextaddr), // to mcu_cmd? + .spi_dma_sram_data(spi_dma_sram_data), // to mcu_cmd? + .spi_dma_sram_we(spi_dma_sram_we), // to mcu_cmd? + .spi_dma_done(spi_dma_done) // to mcu ); assign SPI_DMA_CTRL = spi_dma_ovr ? 1'b0 : 1'bZ; @@ -216,137 +232,139 @@ reg ADDR_WRITE; //reg [23:0] SNES_ADDRr; //wire [23:0] SNES_ADDRw = SNES_ADDR; +wire ROM_SEL; address snes_addr( .CLK(CLK2), .MAPPER(MAPPER), .SNES_ADDR(SNES_ADDR), // requested address from SNES .SNES_CS(SNES_CS), // "CART" pin from SNES (active low) - .SRAM_ADDR(SRAM_ADDR), // Address to request from SRAM (active low) - .ROM_SEL(SRAM_CE2), // which SRAM unit to access - .AVR_ENA(AVR_ENA), // enable AVR mode (active low) - .MODE(MODE), // AVR(1) or SNES(0) ("bus phase") + .ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low) + .ROM_SEL(ROM_SEL), // which SRAM unit to access + .MCU_OVR(MCU_OVR), // enable MCU mode (active low) + .MODE(MODE), // MCU(1) or SNES(0) ("bus phase") .IS_SAVERAM(IS_SAVERAM), .IS_ROM(IS_ROM), - .AVR_ADDR(AVR_ADDR), - .SRAM_ADDR0(SRAM_ADDR0), + .MCU_ADDR(MCU_ADDR), + .ROM_ADDR0(ROM_ADDR0), .SAVERAM_MASK(SAVERAM_MASK), .ROM_MASK(ROM_MASK) ); wire SNES_READ_CYCLEw; wire SNES_WRITE_CYCLEw; -wire AVR_READ_CYCLEw; -wire AVR_WRITE_CYCLEw; - +wire MCU_READ_CYCLEw; +wire MCU_WRITE_CYCLEw; + data snes_data(.CLK(CLK2), .SNES_READ(SNES_READ), .SNES_WRITE(SNES_WRITE), - .AVR_READ(AVR_READ), - .AVR_WRITE(AVR_WRITE), + .MCU_READ(MCU_READ), + .MCU_WRITE(MCU_WRITE), .SNES_DATA(SNES_DATA), - .SRAM_DATA(SRAM_DATA), + .ROM_DATA(ROM_DATA), .MODE(MODE), .SNES_DATA_TO_MEM(SNES_DATA_TO_MEM), - .AVR_DATA_TO_MEM(AVR_DATA_TO_MEM), - .SRAM_DATA_TO_SNES_MEM(SRAM_DATA_TO_SNES_MEM), - .SRAM_DATA_TO_AVR_MEM(SRAM_DATA_TO_AVR_MEM), - .AVR_ENA(AVR_ENA), - .AVR_IN_DATA(AVR_IN_DATA), - .AVR_OUT_DATA(AVR_OUT_DATA), - .SRAM_ADDR0(SRAM_ADDR0) + .MCU_DATA_TO_MEM(MCU_DATA_TO_MEM), + .ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM), + .ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM), + .MCU_OVR(MCU_OVR), + .MCU_IN_DATA(MCU_IN_DATA), + .MCU_OUT_DATA(MCU_OUT_DATA), + .ROM_ADDR0(ROM_ADDR0) ); parameter MODE_SNES = 1'b0; -parameter MODE_AVR = 1'b1; +parameter MODE_MCU = 1'b1; -parameter STATE_0 = 13'b0000000000001; -parameter STATE_1 = 13'b0000000000010; -parameter STATE_2 = 13'b0000000000100; -parameter STATE_3 = 13'b0000000001000; -parameter STATE_4 = 13'b0000000010000; -parameter STATE_5 = 13'b0000000100000; -parameter STATE_6 = 13'b0000001000000; -parameter STATE_7 = 13'b0000010000000; -parameter STATE_8 = 13'b0000100000000; -parameter STATE_9 = 13'b0001000000000; -parameter STATE_10 = 13'b0010000000000; -parameter STATE_11 = 13'b0100000000000; -parameter STATE_IDLE = 13'b1000000000000; +parameter STATE_0 = 14'b00000000000001; +parameter STATE_1 = 14'b00000000000010; +parameter STATE_2 = 14'b00000000000100; +parameter STATE_3 = 14'b00000000001000; +parameter STATE_4 = 14'b00000000010000; +parameter STATE_5 = 14'b00000000100000; +parameter STATE_6 = 14'b00000001000000; +parameter STATE_7 = 14'b00000010000000; +parameter STATE_8 = 14'b00000100000000; +parameter STATE_9 = 14'b00001000000000; +parameter STATE_10 = 14'b00010000000000; +parameter STATE_11 = 14'b00100000000000; +parameter STATE_12 = 14'b01000000000000; +parameter STATE_IDLE = 14'b10000000000000; -reg [12:0] STATE; +reg [13:0] STATE; reg [3:0] STATEIDX; reg [1:0] CYCLE_RESET; -reg SRAM_WE_MASK; -reg SRAM_OE_MASK; +reg ROM_WE_MASK; +reg ROM_OE_MASK; -reg [12:0] SRAM_WE_ARRAY [3:0]; -reg [12:0] SRAM_OE_ARRAY [3:0]; +reg [13:0] ROM_WE_ARRAY [3:0]; +reg [13:0] ROM_OE_ARRAY [3:0]; -reg [12:0] SNES_DATA_TO_MEM_ARRAY[1:0]; -reg [12:0] AVR_DATA_TO_MEM_ARRAY[1:0]; -reg [12:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0]; -reg [12:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0]; +reg [13:0] SNES_DATA_TO_MEM_ARRAY[1:0]; +reg [13:0] MCU_DATA_TO_MEM_ARRAY[1:0]; +reg [13:0] ROM_DATA_TO_SNES_MEM_ARRAY[1:0]; +reg [13:0] ROM_DATA_TO_MCU_MEM_ARRAY[1:0]; -reg [12:0] MODE_ARRAY; +reg [13:0] MODE_ARRAY; reg SNES_READ_CYCLE; reg SNES_WRITE_CYCLE; -reg AVR_READ_CYCLE; -reg AVR_WRITE_CYCLE; -reg AVR_SPI_WRITEONCE; -reg AVR_SPI_READONCE; -reg AVR_SPI_WRITE; -reg AVR_SPI_READ; -reg AVR_SPI_ADDR_INCREMENT; -reg [7:0] AVR_DATA_IN; +reg MCU_READ_CYCLE; +reg MCU_WRITE_CYCLE; +reg MCU_SPI_WRITEONCE; +reg MCU_SPI_READONCE; +reg MCU_SPI_WRITE; +reg MCU_SPI_READ; +reg MCU_SPI_ADDR_INCREMENT; +reg [7:0] MCU_DATA_IN; reg [3:0] MAPPER_BUF; reg SNES_DATABUS_OE_BUF; reg SNES_DATABUS_DIR_BUF; -assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX]; +assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX]; initial begin CYCLE_RESET = 2'b0; STATE = STATE_IDLE; - STATEIDX = 12; - SRAM_WE_MASK = 1'b1; - SRAM_OE_MASK = 1'b1; + STATEIDX = 13; + ROM_WE_MASK = 1'b1; + ROM_OE_MASK = 1'b1; SNES_READ_CYCLE = 1'b1; SNES_WRITE_CYCLE = 1'b1; - AVR_READ_CYCLE = 1'b1; - AVR_WRITE_CYCLE = 1'b1; - MODE_ARRAY = 13'b0_000000_111111; + MCU_READ_CYCLE = 1'b1; + MCU_WRITE_CYCLE = 1'b1; + MODE_ARRAY = 14'b0_000000_1111111; - SRAM_WE_ARRAY[2'b00] = 13'b1_000000_000000; - SRAM_WE_ARRAY[2'b01] = 13'b1_000000_111111; - SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000; - SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111; + ROM_WE_ARRAY[2'b00] = 14'b1_000000_0000000; + ROM_WE_ARRAY[2'b01] = 14'b1_000000_1111111; + ROM_WE_ARRAY[2'b10] = 14'b1_111111_0000000; + ROM_WE_ARRAY[2'b11] = 14'b1_111111_1111111; - SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111; - SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000; - SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111; - SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000; + ROM_OE_ARRAY[2'b00] = 14'b1_111111_1111111; + ROM_OE_ARRAY[2'b01] = 14'b1_111111_0000000; + ROM_OE_ARRAY[2'b10] = 14'b0_000000_1111111; + ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000; - SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000; // SNES write + SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write /* 13'b0001000000000 */ - SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // SNES read + SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read - AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111; // AVR write -// AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // AVR write + MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write +// MCU_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000; // MCU write - AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000; // AVR read + MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read - SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // SNES write - SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000100_000000; // SNES read + ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write + ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read /* 13'b0000100000000; */ - SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 13'b0_000000_000000; // AVR write - SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0_000000_000001; // AVR read -// SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 13'b0000000000001; // AVR read + ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write + ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read +// SRAM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 13'b0000000000001; // MCU read end @@ -357,60 +375,63 @@ end // we have 24 internal cycles to work with. (CLKIN * 4) always @(posedge CLK2) begin - CYCLE_RESET <= {CYCLE_RESET[0], SNES_RW_start}; + CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start}; end always @(posedge CLK2) begin - AVR_READ_CYCLE <= AVR_READ; - AVR_WRITE_CYCLE <= AVR_WRITE; - if (SNES_RW_start) begin + MCU_READ_CYCLE <= MCU_READ; + MCU_WRITE_CYCLE <= MCU_WRITE; + if (SNES_cycle_start) begin SNES_READ_CYCLE <= SNES_READ; SNES_WRITE_CYCLE <= SNES_WRITE; STATE <= STATE_0; - STATEIDX <= 11; + STATEIDX <= 12; end else begin case (STATE) STATE_0: begin - STATE <= STATE_1; STATEIDX <= 10; + STATE <= STATE_1; STATEIDX <= 11; end STATE_1: begin - STATE <= STATE_2; STATEIDX <= 9; + STATE <= STATE_2; STATEIDX <= 10; end STATE_2: begin - STATE <= STATE_3; STATEIDX <= 8; + STATE <= STATE_3; STATEIDX <= 9; end STATE_3: begin - STATE <= STATE_4; STATEIDX <= 7; + STATE <= STATE_4; STATEIDX <= 8; end STATE_4: begin - STATE <= STATE_5; STATEIDX <= 6; + STATE <= STATE_5; STATEIDX <= 7; end STATE_5: begin - STATE <= STATE_6; STATEIDX <= 5; + STATE <= STATE_6; STATEIDX <= 6; end STATE_6: begin - STATE <= STATE_7; STATEIDX <= 4; + STATE <= STATE_7; STATEIDX <= 5; end STATE_7: begin - STATE <= STATE_8; STATEIDX <= 3; + STATE <= STATE_8; STATEIDX <= 4; end STATE_8: begin - STATE <= STATE_9; STATEIDX <= 2; + STATE <= STATE_9; STATEIDX <= 3; end STATE_9: begin - STATE <= STATE_10; STATEIDX <= 1; + STATE <= STATE_10; STATEIDX <= 2; end STATE_10: begin - STATE <= STATE_11; STATEIDX <= 0; + STATE <= STATE_11; STATEIDX <= 1; end STATE_11: begin - STATE <= STATE_IDLE; STATEIDX <= 12; + STATE <= STATE_12; STATEIDX <= 0; end + STATE_12: begin + STATE <= STATE_IDLE; STATEIDX <= 13; + end STATE_IDLE: begin - STATE <= STATE_IDLE; STATEIDX <= 12; + STATE <= STATE_IDLE; STATEIDX <= 13; end default: begin - STATE <= STATE_IDLE; STATEIDX <= 12; + STATE <= STATE_IDLE; STATEIDX <= 13; end endcase end @@ -463,35 +484,37 @@ always @(posedge CLK2) begin endcase end */ -// When in AVR mode, enable SRAM_WE according to AVR programming +// When in MCU mode, enable SRAM_WE according to MCU programming // else enable SRAM_WE according to state&cycle -assign SRAM_WE = !AVR_ENA ? AVR_WRITE - : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]); +assign ROM_WE = !MCU_OVR ? MCU_WRITE + : ((!IS_SAVERAM & !MODE) | ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]); -// When in AVR mode, enable SRAM_OE whenever not writing +// When in MCU mode, enable SRAM_OE whenever not writing // else enable SRAM_OE according to state&cycle -assign SRAM_OE = !AVR_ENA ? AVR_READ - : SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]; +assign ROM_OE = !MCU_OVR ? MCU_READ + : ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]; -assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0; -assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0; +assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL; + +assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0; +assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; //assign SRAM_BHE = SRAM_ADDR0; //assign SRAM_BLE = ~SRAM_ADDR0; // dumb version -//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs; -//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1; +//assign SRAM_OE = !MCU_ENA ? MCU_READ : SNES_READs; +//assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1; //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE); assign SNES_DATABUS_OE = (IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE); assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX]; -assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX]; +assign MCU_DATA_TO_MEM = MCU_DATA_TO_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX]; -assign SRAM_DATA_TO_SNES_MEM = SRAM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX]; -assign SRAM_DATA_TO_AVR_MEM = SRAM_DATA_TO_AVR_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX]; +assign ROM_DATA_TO_SNES_MEM = ROM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX]; +assign ROM_DATA_TO_MCU_MEM = ROM_DATA_TO_MCU_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX]; assign SNES_READ_CYCLEw = SNES_READ_CYCLE; assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE; diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index 855cc35..135d419 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -9,10 +9,10 @@ - + - + @@ -84,6 +84,10 @@ + + + + @@ -115,7 +119,7 @@ - + @@ -149,7 +153,7 @@ - + @@ -159,18 +163,18 @@ - + - + - + @@ -187,7 +191,7 @@ - + @@ -222,6 +226,7 @@ + @@ -236,7 +241,6 @@ - @@ -246,6 +250,7 @@ + @@ -268,7 +273,6 @@ - @@ -284,19 +288,25 @@ - + + + + + + + @@ -310,7 +320,7 @@ - + @@ -332,7 +342,7 @@ - + @@ -356,8 +366,8 @@ - - + + @@ -375,11 +385,15 @@ + + + + @@ -389,16 +403,19 @@ + + - - - + + + + @@ -408,6 +425,7 @@ + @@ -419,7 +437,6 @@ - @@ -428,12 +445,18 @@ + + + + + + @@ -447,6 +470,7 @@ + @@ -458,7 +482,7 @@ - + @@ -470,28 +494,29 @@ - - - - + + + + - - - - - - - + - + + + + + + + + diff --git a/verilog/sd2snes/spi.v b/verilog/sd2snes/spi.v index 318090f..c6bfe85 100644 --- a/verilog/sd2snes/spi.v +++ b/verilog/sd2snes/spi.v @@ -65,20 +65,23 @@ always @(posedge clk) begin end assign SCK = spi_dma_ovr ? spi_dma_sck : spi_dma_leadout ? 1'b0 : 1'bZ; reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK}; -wire SCK_risingedge = spi_dma_ovr ? 0 : (SCKr[2:1]==2'b01); // now we can detect SCK rising edges -wire SCK_fallingedge = spi_dma_ovr ? 0 : (SCKr[2:1]==2'b10); // and falling edges +wire SCK_risingedge = spi_dma_ovr ? 0 : (SCKr[1:0]==2'b01); // now we can detect SCK rising edges +wire SCK_fallingedge = spi_dma_ovr ? 0 : (SCKr[1:0]==2'b10); // and falling edges + +// wire SCK_risingedge = spi_dma_ovr ? 0 : ({SCKr[0], SCK}==2'b01); // now we can detect SCK rising edges +// wire SCK_fallingedge = spi_dma_ovr ? 0 : ({SCKr[0], SCK}==2'b10); // and falling edges // same thing for SSEL reg [2:0] SSELr; always @(posedge clk) SSELr <= {SSELr[1:0], SSEL}; wire SSEL_active = ~SSELr[1]; // SSEL is active low -wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge -wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge +wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge +wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge assign endmessage = SSEL_endmessage; assign startmessage = SSEL_startmessage; // and for MOSI reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI}; -wire MOSI_data = MOSIr[1]; +wire MOSI_data = MOSIr[0]; // bit count for one SPI byte + byte count for the message reg [2:0] bitcnt;