From ceb5bec774dc339fd87426a15a5e9365dcda2b48 Mon Sep 17 00:00:00 2001 From: ikari Date: Fri, 4 Sep 2009 10:07:57 +0200 Subject: [PATCH] new SRAM access (SPI) --- src/config.h | 4 +- src/fpga.c | 10 ++- src/led.c | 9 +++ src/led.h | 11 +-- src/main.c | 42 +++++++--- src/memory.c | 66 ++++++++-------- src/memory.h | 2 +- src/snes.c | 8 +- verilog/sd2snes/address.v | 13 +-- verilog/sd2snes/data.v | 15 ++-- verilog/sd2snes/main.ucf | 4 - verilog/sd2snes/main.v | 148 +++++++++++++++++++---------------- verilog/sd2snes/sd2snes.xise | 2 +- 13 files changed, 184 insertions(+), 150 deletions(-) diff --git a/src/config.h b/src/config.h index 6036cfe..6c33409 100644 --- a/src/config.h +++ b/src/config.h @@ -62,8 +62,8 @@ # error Unknown chip! # endif # define SD_CHANGE_VECT INT0_vect -# define SDCARD_WP (PIND & _BV(PD6)) -# define SDCARD_WP_SETUP() do { DDRD &= ~ _BV(PD6); PORTD |= _BV(PD6); } while(0) +# define SDCARD_WP (PINB & _BV(PB3)) +# define SDCARD_WP_SETUP() do { DDRB &= ~ _BV(PB3); PORTB |= _BV(PB3); } while(0) # define SD_CHANGE_ICR MCUCR # define SD_SUPPLY_VOLTAGE (1L<<21) # define DEVICE_SELECT (8+!(PINA & _BV(PA2))+2*!(PINA & _BV(PA3))) diff --git a/src/fpga.c b/src/fpga.c index 5be7c27..59eb110 100644 --- a/src/fpga.c +++ b/src/fpga.c @@ -200,6 +200,12 @@ void set_avr_mapper(uint8_t val) { } void set_avr_bank(uint8_t val) { - PORTB &= 0xFC; - PORTB |= val&0x03; + SPI_SS_HIGH(); + FPGA_SS_LOW(); + spiTransferByte(0x00); // SET ADDRESS + spiTransferByte(val * 0x20); // select chip + spiTransferByte(0x00); // select chip + spiTransferByte(0x00); // select chip + FPGA_SS_HIGH(); + SPI_SS_LOW(); } diff --git a/src/led.c b/src/led.c index 67d96d9..02091ba 100644 --- a/src/led.c +++ b/src/led.c @@ -46,3 +46,12 @@ void toggle_busy_led(void) { PORTB &= ~_BV(PB1); DDRB ^= _BV(PB1); } + +void set_busy_led(uint8_t state) { + PORTB &= ~_BV(PB1); + if(state) { + DDRB |= _BV(PB1); + } else { + DDRB &= ~_BV(PB1); + } +} diff --git a/src/led.h b/src/led.h index 858f36d..d21d51d 100644 --- a/src/led.h +++ b/src/led.h @@ -40,16 +40,7 @@ extern volatile uint8_t led_state; /* Update the LEDs to match the buffer state */ void update_leds(void); void toggle_busy_led(void); +void set_busy_led(uint8_t); -/* Wrapped in do..while to avoid "ambigious else" warnings */ -#ifdef SINGLE_LED -# define set_dirty_led(x) do{if (x) { led_state |= LED_DIRTY; } else { led_state &= (uint8_t)~LED_DIRTY; }}while(0) -# define set_busy_led(x) do{if (x) { led_state |= LED_BUSY ; } else { led_state &= (uint8_t)~LED_BUSY ; }}while(0) -# define set_error_led(x) do{if (x) { led_state |= LED_ERROR; } else { led_state &= (uint8_t)~LED_ERROR; }}while(0) -#else -# define set_dirty_led(x) do{if (x) { DIRTY_LED_ON(); } else { DIRTY_LED_OFF(); }}while(0) -# define set_busy_led(x) do{if (x) { BUSY_LED_ON(); } else { BUSY_LED_OFF(); }}while(0) -# define set_error_led(x) do{if (x) { led_state |= LED_ERROR; } else { led_state &= (uint8_t)~LED_ERROR; update_leds(); }}while(0) -#endif #endif diff --git a/src/main.c b/src/main.c index 0c3f6e7..e42bbe3 100644 --- a/src/main.c +++ b/src/main.c @@ -45,6 +45,8 @@ #include "fileops.h" #include "memory.h" #include "fpga_spi.h" +#include "spi.h" +#include "avrcompat.h" char stringbuf[100]; @@ -168,33 +170,49 @@ int main(void) { load_rom("/test.smc"); uart_putc(')'); -/*XXX uart_putc('['); + uart_putc('['); load_sram("/test.srm"); - uart_putc(']');*/ - - set_avr_mapper(1); + uart_putc(']'); + set_busy_led(0); + set_avr_mapper(0); set_avr_ena(1); _delay_ms(100); uart_puts_P(PSTR("SNES GO!")); snes_reset(0); - - _delay_ms(6553.6); while(1) { -// snes_main_loop(); + snes_main_loop(); } - while(1) { - uint8_t data=PINC; + + + /* HERE BE LIONS */ +while(1) { + SPI_SS_HIGH(); + FPGA_SS_LOW(); + spiTransferByte(0x00); + spiTransferByte(0x00); + spiTransferByte(0x7f); + spiTransferByte(0xc0); + FPGA_SS_HIGH(); + FPGA_SS_LOW(); + spiTransferByte(0x81); // read w/ increment... hopefully + spiTransferByte(0x00); // 1 dummy read + uart_putcrlf(); + for(uint8_t cnt=0; cnt<16; cnt++) { + uint8_t data=spiTransferByte(0x00); _delay_ms(2); if(data>=0x20 && data <= 0x7a) { uart_putc(data); } else { - uart_putc('.'); +// uart_putc('.'); + uart_putc("0123456789ABCDEF"[data>>4]); + uart_putc("0123456789ABCDEF"[data&15]); + uart_putc(' '); } - SET_AVR_NEXTADDR(); - CLR_AVR_NEXTADDR(); // set_avr_bank(3); } + FPGA_SS_HIGH(); +} while(1); } diff --git a/src/memory.c b/src/memory.c index 59c2e41..346209d 100644 --- a/src/memory.c +++ b/src/memory.c @@ -39,10 +39,10 @@ uint32_t load_rom(char* filename) { SPI_SS_HIGH(); if (file_res || !bytes_read) break; FPGA_SS_LOW(); - _delay_us(1); spiTransferByte(0x91); // write w/ increment if(!(count++ % 16)) { toggle_busy_led(); + uart_putc('.'); } for(int j=0; j>4)]); + uart_putc(hex[data&0xf]); + uart_putc(' '); + _delay_ms(2);*/ crc += crc16_update(crc, &data, 1); - CLR_AVR_ADDR_EN(); - SET_AVR_NEXTADDR(); - _delay_us(5); - CLR_AVR_NEXTADDR(); - SET_AVR_ADDR_EN(); } - + FPGA_SS_HIGH(); /* uart_putc(hex[(crc>>28)&0xf]); uart_putc(hex[(crc>>24)&0xf]); uart_putc(hex[(crc>>20)&0xf]); diff --git a/src/memory.h b/src/memory.h index 541c371..6e0aa60 100644 --- a/src/memory.h +++ b/src/memory.h @@ -5,6 +5,6 @@ #define MEMORY_H uint32_t load_rom(char* filename); uint32_t load_sram(char* filename); - void save_sram(char* filename, uint32_t sram_size); + void save_sram(char* filename, uint32_t sram_size, uint32_t base_addr); uint32_t calc_sram_crc(uint32_t size); #endif diff --git a/src/snes.c b/src/snes.c index f817c92..89b7a11 100644 --- a/src/snes.c +++ b/src/snes.c @@ -10,12 +10,13 @@ #include "memory.h" #include "fileops.h" #include "ff.h" +#include "led.h" uint8_t initloop=1; uint32_t sram_crc, sram_crc_old; uint32_t sram_size = 8192; // sane default - +uint32_t sram_base_addr = 0x600000; // chip 3 void snes_init() { DDRD |= _BV(PD5); // PD5 = RESET_DIR DDRD |= _BV(PD6); // PD6 = RESET @@ -46,13 +47,16 @@ void snes_reset(int state) { void snes_main_loop() { if(initloop) { sram_crc_old = calc_sram_crc(sram_size); + save_sram("/test.srm", sram_size, sram_base_addr); initloop=0; } sram_crc = calc_sram_crc(sram_size); if(sram_crc != sram_crc_old) { uart_putc('U'); uart_putcrlf(); - save_sram("/test.srm", sram_size); + set_busy_led(1); + save_sram("/test.srm", sram_size, sram_base_addr); + set_busy_led(0); } sram_crc_old = sram_crc; uart_putc('.'); diff --git a/verilog/sd2snes/address.v b/verilog/sd2snes/address.v index 1094979..45b3276 100644 --- a/verilog/sd2snes/address.v +++ b/verilog/sd2snes/address.v @@ -31,8 +31,6 @@ module address( output IS_ROM, // address mapped as ROM? input [23:0] AVR_ADDR, // allow address to be set externally input ADDR_WRITE, - output SRAM_BHE, - output SRAM_BLE, output SRAM_ADDR0 ); @@ -40,7 +38,7 @@ reg [22:0] SRAM_ADDR_BUF; reg [3:0] ROM_SEL_BUF; reg [3:0] AVR_ROM_SEL_BUF; reg [3:0] CS_ARRAY[3:0]; -reg [1:0] AVR_BANK; +wire [1:0] SRAM_BANK; wire [3:0] CURRENT_ROM_SEL; wire [22:0] SRAM_ADDR_FULL; @@ -50,7 +48,6 @@ initial begin CS_ARRAY[1] = 4'b0010; CS_ARRAY[2] = 4'b0100; CS_ARRAY[3] = 4'b1000; - AVR_BANK = 2'b0; end /* currently supported mappers: @@ -84,7 +81,7 @@ assign IS_ROM = ( (MAPPER == 3'b000) ? ( (!SNES_ADDR[22] assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR : ((MAPPER == 3'b000) ? (IS_SAVERAM ? SNES_ADDR[14:0] - 15'h6000 - : SNES_ADDR[22:0]) + : (SNES_ADDR[22:0] & 23'b00111111111111111111111)) :(MAPPER == 3'b001) ? (IS_SAVERAM ? SNES_ADDR[14:0] : {1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]}) @@ -93,11 +90,9 @@ assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR assign SRAM_BANK = SRAM_ADDR_FULL[22:21]; assign SRAM_ADDR = SRAM_ADDR_FULL[20:1]; -// XXX assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK]; -assign ROM_SEL = 4'b0001; +assign ROM_SEL = (MODE) ? CS_ARRAY[SRAM_BANK] : IS_SAVERAM ? 4'b1000 : CS_ARRAY[SRAM_BANK]; +// assign ROM_SEL = 4'b0001; -assign SRAM_BHE = !AVR_ENA ? SRAM_ADDR_FULL[0] : 1'b0; -assign SRAM_BLE = !AVR_ENA ? !SRAM_ADDR_FULL[0] : 1'b0; assign SRAM_ADDR0 = SRAM_ADDR_FULL[0]; endmodule diff --git a/verilog/sd2snes/data.v b/verilog/sd2snes/data.v index f01b6bf..5a7720c 100644 --- a/verilog/sd2snes/data.v +++ b/verilog/sd2snes/data.v @@ -43,21 +43,22 @@ reg [7:0] AVR_IN_MEM; reg [7:0] AVR_OUT_MEM; wire [7:0] FROM_SRAM_BYTE; -wire [7:0] TO_SRAM_BYTE; assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM; assign FROM_SRAM_BYTE = (SRAM_ADDR0 ? SRAM_DATA[7:0] : SRAM_DATA[15:8]); -assign TO_SRAM_BYTE = !AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) // /**/ : 8'bZ; - : MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ) - : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ); - + assign AVR_OUT_DATA = !AVR_ENA ? (FROM_SRAM_BYTE) : (AVR_OUT_MEM); // XXX assign SRAM_DATA = (SRAM_BHE ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ}); -assign SRAM_DATA = !AVR_ENA ? ((SRAM_ADDR0 ? {8'bZ, TO_SRAM_BYTE} : {TO_SRAM_BYTE, 8'bZ})) : 16'bZ; - +assign SRAM_DATA[7:0] = SRAM_ADDR0 ? (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) + : (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ) + : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ))) + : 8'bZ; +assign SRAM_DATA[15:8] = SRAM_ADDR0 ? 8'bZ : (!AVR_ENA ? (!AVR_WRITE ? AVR_IN_DATA : 8'bZ) + : (MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ) + : (!SNES_WRITE ? SNES_IN_MEM : 8'bZ))); always @(posedge CLK) begin if(SNES_DATA_TO_MEM) SNES_IN_MEM <= SNES_DATA; diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf index 3524e84..df137f3 100644 --- a/verilog/sd2snes/main.ucf +++ b/verilog/sd2snes/main.ucf @@ -1,4 +1,3 @@ -NET "CLK" TNM_NET = CLK; NET "CLKIN" TNM_NET = CLKIN; TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 MHz HIGH 50 %; NET "AVR_ENA" IOSTANDARD = LVCMOS33; @@ -73,7 +72,6 @@ NET "SRAM_WE" IOSTANDARD = LVCMOS33; NET "SNES_CPU_CLK" IOSTANDARD = LVCMOS33; NET "SNES_IRQ" IOSTANDARD = LVCMOS33; NET "SNES_REFRESH" IOSTANDARD = LVCMOS33; -NET "SPI_LSB" IOSTANDARD = LVCMOS33; NET "SPI_MISO" IOSTANDARD = LVCMOS33; NET "SPI_MOSI" IOSTANDARD = LVCMOS33; NET "SPI_SCK" IOSTANDARD = LVCMOS33; @@ -185,5 +183,3 @@ NET "SRAM_DATA[8]" LOC = P96; NET "SRAM_DATA[9]" LOC = P98; NET "SRAM_OE" LOC = P93; NET "CLKIN" IOSTANDARD = LVCMOS33; -NET "CLKIN" SLEW = FAST; -NET "CLKIN" PULLUP; diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v index 6615848..36ca342 100644 --- a/verilog/sd2snes/main.v +++ b/verilog/sd2snes/main.v @@ -49,11 +49,10 @@ module main( output SPI_MISO, input SPI_SS, input SPI_SCK, - input AVR_ENA, + input AVR_ENA /* debug */ - output MODE, - output SPI_LSB + ); wire [7:0] spi_cmd_data; wire [7:0] spi_param_data; @@ -67,7 +66,7 @@ wire [7:0] AVR_IN_DATA; wire [7:0] AVR_OUT_DATA; wire [3:0] MAPPER; -spi snes_spi(.clk(CLK), +spi snes_spi(.clk(CLK2), .MOSI(SPI_MOSI), .MISO(SPI_MISO), .SSEL(SPI_SS), @@ -78,13 +77,14 @@ spi snes_spi(.clk(CLK), .cmd_data(spi_cmd_data), .param_data(spi_param_data), .endmessage(spi_endmessage), + .startmessage(spi_startmessage), .input_data(spi_input_data), .byte_cnt(spi_byte_cnt), .bit_cnt(spi_bit_cnt) ); avr_cmd snes_avr_cmd( - .clk(CLK), + .clk(CLK2), .cmd_ready(spi_cmd_ready), .param_ready(spi_param_ready), .cmd_data(spi_cmd_data), @@ -97,7 +97,10 @@ avr_cmd snes_avr_cmd( .avr_data_out(AVR_IN_DATA), .spi_byte_cnt(spi_byte_cnt), .spi_bit_cnt(spi_bit_cnt), - .addr_out(AVR_ADDR) + .spi_data_out(spi_input_data), + .addr_out(AVR_ADDR), + .endmessage(spi_endmessage), + .startmessage(spi_startmessage) ); my_dcm snes_dcm(.CLKIN(CLKIN), @@ -131,7 +134,7 @@ reg ADDR_WRITE; address snes_addr( - .CLK(CLK), + .CLK(CLK2), .MAPPER(MAPPER), .SNES_ADDR(SNES_ADDR), // requested address from SNES .SNES_CS(SNES_CSs), // "CART" pin from SNES (active low) @@ -142,12 +145,10 @@ address snes_addr( .IS_SAVERAM(IS_SAVERAM), .IS_ROM(IS_ROM), .AVR_ADDR(AVR_ADDR), - .SRAM_BHE(SRAM_BHE), - .SRAM_BLE(SRAM_BLE), .SRAM_ADDR0(SRAM_ADDR0) ); -data snes_data(.CLK(CLK), +data snes_data(.CLK(CLK2), .SNES_READ(SNES_READs), .SNES_WRITE(SNES_WRITEs), .AVR_READ(AVR_READ), @@ -168,31 +169,33 @@ data snes_data(.CLK(CLK), parameter MODE_SNES = 1'b0; parameter MODE_AVR = 1'b1; -parameter STATE_0 = 8'b00000001; -parameter STATE_1 = 8'b00000010; -parameter STATE_2 = 8'b00000100; -parameter STATE_3 = 8'b00001000; -parameter STATE_4 = 8'b00010000; -parameter STATE_5 = 8'b00100000; -parameter STATE_6 = 8'b01000000; -parameter STATE_7 = 8'b10000000; +parameter STATE_0 = 10'b0000000001; +parameter STATE_1 = 10'b0000000010; +parameter STATE_2 = 10'b0000000100; +parameter STATE_3 = 10'b0000001000; +parameter STATE_4 = 10'b0000010000; +parameter STATE_5 = 10'b0000100000; +parameter STATE_6 = 10'b0001000000; +parameter STATE_7 = 10'b0010000000; +parameter STATE_8 = 10'b0100000000; +parameter STATE_9 = 10'b1000000000; -reg [7:0] STATE; -reg [2:0] STATEIDX; +reg [9:0] STATE; +reg [3:0] STATEIDX; reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK; reg SRAM_WE_MASK; reg SRAM_OE_MASK; -reg [7:0] SRAM_WE_ARRAY [3:0]; -reg [7:0] SRAM_OE_ARRAY [3:0]; +reg [9:0] SRAM_WE_ARRAY [3:0]; +reg [9:0] SRAM_OE_ARRAY [3:0]; -reg [7:0] SNES_DATA_TO_MEM_ARRAY[1:0]; -reg [7:0] AVR_DATA_TO_MEM_ARRAY[1:0]; -reg [7:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0]; -reg [7:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0]; +reg [9:0] SNES_DATA_TO_MEM_ARRAY[1:0]; +reg [9:0] AVR_DATA_TO_MEM_ARRAY[1:0]; +reg [9:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0]; +reg [9:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0]; -reg [7:0] MODE_ARRAY; +reg [9:0] MODE_ARRAY; reg SNES_READ_CYCLE; reg SNES_WRITE_CYCLE; @@ -215,8 +218,8 @@ initial begin CYCLE_RESET = 0; CYCLE_RESET_ACK = 0; - STATE = STATE_7; - STATEIDX = 7; + STATE = STATE_9; + STATEIDX = 9; SRAM_WE_MASK = 1'b1; SRAM_OE_MASK = 1'b1; SNES_READ_CYCLE = 1'b1; @@ -224,29 +227,29 @@ initial begin AVR_READ_CYCLE = 1'b1; AVR_WRITE_CYCLE = 1'b1; - MODE_ARRAY = 8'b00001111; + MODE_ARRAY = 10'b0000011111; - SRAM_WE_ARRAY[2'b00] = 8'b10001000; - SRAM_WE_ARRAY[2'b01] = 8'b10001111; - SRAM_WE_ARRAY[2'b10] = 8'b11111000; - SRAM_WE_ARRAY[2'b11] = 8'b11111111; + SRAM_WE_ARRAY[2'b00] = 10'b1000010000; + SRAM_WE_ARRAY[2'b01] = 10'b1000011111; + SRAM_WE_ARRAY[2'b10] = 10'b1111110000; + SRAM_WE_ARRAY[2'b11] = 10'b1111111111; - SRAM_OE_ARRAY[2'b00] = 8'b11111111; - SRAM_OE_ARRAY[2'b01] = 8'b11110000; - SRAM_OE_ARRAY[2'b10] = 8'b00001111; - SRAM_OE_ARRAY[2'b11] = 8'b00000000; + SRAM_OE_ARRAY[2'b00] = 10'b1111111111; + SRAM_OE_ARRAY[2'b01] = 10'b1111100000; + SRAM_OE_ARRAY[2'b10] = 10'b0000011111; + SRAM_OE_ARRAY[2'b11] = 10'b0000000000; - SNES_DATA_TO_MEM_ARRAY[1'b0] = 8'b10000000; - SNES_DATA_TO_MEM_ARRAY[1'b1] = 8'b00000000; + SNES_DATA_TO_MEM_ARRAY[1'b0] = 10'b1000000000; + SNES_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000; - AVR_DATA_TO_MEM_ARRAY[1'b0] = 8'b00010000; - AVR_DATA_TO_MEM_ARRAY[1'b1] = 8'b00000000; + AVR_DATA_TO_MEM_ARRAY[1'b0] = 10'b0000100000; + AVR_DATA_TO_MEM_ARRAY[1'b1] = 10'b0000000000; - SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 8'b00000000; - SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 8'b00100000; + SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 10'b0000000000; + SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 10'b0000100000; - SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 8'b00000000; - SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 8'b00000001; + SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 10'b0000000000; + SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 10'b0000000001; end // falling edge of SNES /RD or /WR marks the beginning of a new cycle @@ -263,7 +266,7 @@ always @(posedge CLK2) begin end end -always @(posedge CLK) begin +always @(posedge CLK2) begin if (CYCLE_RESET && !CYCLE_RESET_ACK) begin CYCLE_RESET_ACK <= 1; STATE <= STATE_0; @@ -283,53 +286,65 @@ always @(posedge CLK) begin STATE <= STATE_6; STATE_6: STATE <= STATE_7; - STATE_7: begin + STATE_7: + STATE <= STATE_8; + STATE_8: + STATE <= STATE_9; + STATE_9: begin if (SNES_RW /* || !AVR_ENA */) // check for end of SNES cycle to avoid looping CYCLE_RESET_ACK <= 0; // ready for new cycle - STATE <= STATE_7; + STATE <= STATE_9; end default: - STATE <= STATE_7; + STATE <= STATE_9; endcase end end always @(posedge CLK2) begin - case (STATE) - - STATE_7: begin + case (STATE) + STATE_9: begin SNES_READ_CYCLE <= SNES_READs; SNES_WRITE_CYCLE <= SNES_WRITEs; AVR_READ_CYCLE <= AVR_READ; AVR_WRITE_CYCLE <= AVR_WRITE; - STATEIDX <= 7; + STATEIDX <= 9; end + STATE_0: begin - STATEIDX <= 6; + STATEIDX <= 8; end STATE_1: begin - STATEIDX <= 5; + STATEIDX <= 7; end STATE_2: begin - STATEIDX <= 4; + STATEIDX <= 6; end STATE_3: begin - STATEIDX <= 3; + STATEIDX <= 5; end STATE_4: begin - STATEIDX <= 2; + STATEIDX <= 4; end STATE_5: begin - STATEIDX <= 1; + STATEIDX <= 3; end STATE_6: begin + STATEIDX <= 2; + end + + STATE_7: begin + STATEIDX <= 1; + end + + STATE_8: begin STATEIDX <= 0; end endcase @@ -337,21 +352,20 @@ end // When in AVR mode, enable SRAM_WE according to AVR programming // else enable SRAM_WE according to state&cycle -//assign SRAM_WE = !AVR_ENA ? AVR_WRITE -// : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]); +assign SRAM_WE = !AVR_ENA ? AVR_WRITE + : ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]); // When in AVR mode, enable SRAM_OE whenever not writing // else enable SRAM_OE according to state&cycle assign SRAM_OE = !AVR_ENA ? AVR_READ : SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]; +assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0; +assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0; + // dumb version //assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs; -assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1; - -always @(posedge CLK) begin - SNES_DATABUS_OE_BUF <= SNES_CSs | (SNES_READs & SNES_WRITEs); -end +//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1; //assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE); assign SNES_DATABUS_OE = (IS_ROM & SNES_CSs) | (!IS_ROM & !IS_SAVERAM) | (SNES_READs & SNES_WRITEs); diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise index 6816022..dbcc7a9 100644 --- a/verilog/sd2snes/sd2snes.xise +++ b/verilog/sd2snes/sd2snes.xise @@ -81,7 +81,7 @@ - +