begin ARM firmware

src/flash.cfg

@@ -0,0 +1,4 @@
+# script running on reset
+init
+script  flash.script 
+

src/flash.script

@@ -0,0 +1,13 @@
+# mthomas 4/2008, tested with OpenOCD SVN555
+
+#flash probe 0
+#flash erase_check 0
+#flash protect_check 0
+#flash info 0
+
+reset init
+flash write_image erase unlock obj/sd2snes.bin 0 bin
+sleep 200
+reset run
+shutdown
+

src/lpc1754.cfg

@@ -0,0 +1,75 @@
+# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+# reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc1754
+}
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK ] } {
+	set _CCLK $CCLK
+} else {
+	set _CCLK 4000
+}
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+#delays on reset lines
+adapter_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 & LPC1700 -> SRST causes TRST
+#reset_config srst_pulls_trst
+reset_config trst_and_srst srst_push_pull trst_push_pull
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+jtag newtap x3s tap -irlen 6 -ircapture 0x11 -irmask 0x11 -expected-id 0x0141c093
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME -event reset-init 0
+
+# LPC1754 has 16kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
+# and 16K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x4000
+$_TARGETNAME configure -work-area-phys 0x2007c000 -work-area-size 0x4000
+
+# LPC1754 has 128kB of flash memory, managed by ROM code (including a
+# boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x20000 0 0 $_TARGETNAME \
+	lpc1700 $_CCLK calc_checksum
+
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+jtag_khz 1000
+
+$_TARGETNAME configure -event reset-init {
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
+	# Bit Symbol Value Description Reset
+	# value
+	# 0 MAP Memory map control. 0
+	# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
+	# 1 User mode. The on-chip Flash memory is mapped to address 0.
+	# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
+	#
+	# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
+
+	mww 0x400FC040 0x01
+}

src/lpc1754.ld

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+/* Linker script for LPC1754
+ *
+ * Written 2010 by Ingo Korb
+ *
+ * Partially based on the linker scripts of avr-libc
+ */
+
+OUTPUT_FORMAT(elf32-littlearm)
+ENTRY(_start)
+
+MEMORY 
+{
+  flash  (rx)  : ORIGIN = 0x00000000, LENGTH = 128K
+  ram    (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
+  ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
+}
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.vectors))
+    KEEP(*(.init))
+    *(.text)
+    *(.text.*)
+    *(.gnu.linkonce.t.*)
+
+    /* C++ con-/destructors */
+    __ctors_start = . ;
+    *(.ctors)
+    __ctors_end = . ;
+    __dtors_start = . ;
+    *(.dtors)
+    __dtors_end = . ;
+    KEEP(SORT(*)(.ctors))
+    KEEP(SORT(*)(.dtors))
+
+    KEEP(*(.fini))
+
+    __text_end = .;
+  } > flash
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+  __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >flash
+  __exidx_end = .;
+
+  /* I hope this does what I think it does */
+  .rodata : AT (ALIGN(__exidx_end,4))
+  {
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    __rodata_end = .;
+  } > flash
+
+  /* Data section */
+  .data : AT (ALIGN(__rodata_end,4))
+  {
+    __data_start = .;
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    __data_end = .;
+  } > ram
+
+  /* Addresses of in-rom data section */
+  __data_load_start = LOADADDR(.data);
+  __data_load_end   = __data_load_start + SIZEOF(.data);
+
+  . = ALIGN(4);
+
+  /* BSS */
+  .bss :
+  {
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    __bss_end__ = .;
+  } > ram
+
+  /* second BSS in AHB ram */
+  .ahbram (NOLOAD) :
+  {
+    __ahbram_start__ = .;
+    *(.ahbram)
+    *(.ahbram.*)
+    __ahbram_end__ = .;
+  } > ahbram
+
+  __heap_start = ALIGN(__bss_end__, 4);
+
+  /* Default stack starts at end of ram */
+  PROVIDE(__stack = ORIGIN(ram) + LENGTH(ram)) ;
+
+
+  /* Everyone seems to copy the stuff below straight from somewhere else, so I'll do that too */
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+}

src/openocd-usb.cfg

@@ -0,0 +1,12 @@
+#
+# Hubert Hoegl's USB to JTAG
+#
+# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
+#
+
+interface ft2232
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232"
+ft2232_layout "oocdlink"
+ft2232_latency 2
+adapter_khz 10

src/startup.S

@@ -0,0 +1,101 @@
+/* startup code for LPC17xx
+ *
+ * Written 2010 by Ingo Korb
+ */
+        .syntax unified
+
+        .section .vectors
+
+        .macro  except label
+        .weak   \label
+        .set    \label, __unhandled_exception
+        .word   \label
+        .endm
+        
+        /* Cortex M3 standard except vectors */
+        .word   __stack
+        .word   _start
+        except  NMI_Handler
+        except  HardFault_Handler
+        except  MemManage_Handler
+        except  BusFault_Handler
+        except  UsageFault_Handler
+        .word   0
+        .word   0
+        .word   0
+        .word   0
+        except  SVC_Handler
+        except  DebugMon_Handler
+        .word   0
+        except  PendSV_Handler
+        except  SysTick_Handler
+
+        /* External interrupt vectors */
+        except  WDT_IRQHandler
+        except  TIMER0_IRQHandler
+        except  TIMER1_IRQHandler
+        except  TIMER2_IRQHandler
+        except  TIMER3_IRQHandler
+        except  UART0_IRQHandler
+        except  UART1_IRQHandler
+        except  UART2_IRQHandler
+        except  UART3_IRQHandler
+        except  PWM1_IRQHandler
+        except  I2C0_IRQHandler
+        except  I2C1_IRQHandler
+        except  I2C2_IRQHandler
+        except  SPI_IRQHandler
+        except  SSP0_IRQHandler
+        except  SSP1_IRQHandler
+        except  PLL0_IRQHandler
+        except  RTC_IRQHandler
+        except  EINT0_IRQHandler
+        except  EINT1_IRQHandler
+        except  EINT2_IRQHandler
+        except  EINT3_IRQHandler
+        except  ADC_IRQHandler
+        except  BOD_IRQHandler
+        except  USB_IRQHandler
+        except  CAN_IRQHandler
+        except  DMA_IRQHandler
+        except  I2S_IRQHandler
+        except  ENET_IRQHandler
+        except  RIT_IRQHandler
+        except  MCPWM_IRQHandler
+        except  QEI_IRQHandler
+        except  PLL1_IRQHandler
+
+        .section .text
+
+        .global _start
+        .thumb_func
+_start:
+        /* copy data section to ram */
+        ldr     r0, =__data_load_start
+        ldr     r1, =__data_load_end
+        ldr     r2, =__data_start
+dataloop:
+        ldr.w   r3, [r0], #4
+        str.w   r3, [r2], #4
+        cmp     r0, r1
+        blo     dataloop
+
+        /* clear bss section */
+        ldr     r0, =__bss_start__
+        ldr     r1, =__bss_end__
+        ldr     r2, =0
+bssloop:
+        str.w   r2, [r0], #4
+        cmp     r0, r1
+        blo     bssloop
+
+        /* start main() */
+        b       main
+
+        /* endless loop */
+        .weak __unhandled_exception
+        .thumb_func
+__unhandled_exception:
+        b       __unhandled_exception
+        
+        .end

src/utils/Makefile

@@ -0,0 +1,12 @@
+
+CC = gcc
+CFLAGS = -Wall -Wstrict-prototypes -Werror
+
+all: lpcchksum
+
+lpcchksum: lpcchksum.o
+	$(CC) $(CFLAGS) $^ --output $@
+
+%.o: %.c
+	$(CC) -c $(CFLAGS) $< -o $@
+

src/utils/lpcchksum.c

@@ -0,0 +1,67 @@
+/*
+ * calculate+inject LPC1700 vector checksum
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+
+uint32_t getu32(uint8_t *buffer) {
+	return buffer[0]+(buffer[1]<<8)+(buffer[2]<<16)+(buffer[3]<<24);
+}
+
+void putu32(uint8_t *buffer, uint32_t data) {
+	buffer[0]=(uint8_t)(data&0xff);
+	buffer[1]=(uint8_t)((data>>8)&0xff);
+	buffer[2]=(uint8_t)((data>>16)&0xff);
+	buffer[3]=(uint8_t)((data>>24)&0xff);
+}
+
+int main(int argc, char **argv) {
+	FILE *bin;
+	uint32_t data;
+	size_t len;
+	int count;
+	uint8_t *buffer;
+
+	if(argc<2) {
+		fprintf(stderr, "Usage: %s <binfile>\nThe original file will be modified!\n", argv[0]);
+		return 1;
+	}
+
+	if((bin=fopen(argv[1], "rb"))==NULL) {
+		perror("could not open input file");
+		return 1;
+	}
+	
+	fseek(bin, 0, SEEK_END);
+	len=ftell(bin);
+	fseek(bin, 0, SEEK_SET);
+	if((buffer=malloc(len))==NULL) {
+		perror("could not reserve memory");
+		fclose(bin);
+		return 1;
+	}
+	fread(buffer, len, 1, bin);
+	fclose(bin);
+
+	data=0;
+	for(count=0; count<7; count++) {
+		data+=getu32(buffer+4*count);
+	}
+	printf("data=%x chksum=%x\n", data, ~data+1);
+	putu32(buffer+28,~data+1);
+
+	if((bin=fopen(argv[1], "wb"))==NULL) {
+		perror("could not open output file");
+		return 1;
+	}
+
+	fwrite(buffer, len, 1, bin);
+	fclose(bin);
+	printf("done\n");
+	free(buffer);
+
+	return 0;
+}