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Firmware: remove SPI speed switching

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This commit is contained in:
Maximilian Rehkopf 2012-07-01 03:15:27 +02:00
parent 57bb6351e7
commit d9e1680800
5 changed files with 5 additions and 45 deletions
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6
src/config.h
View File

@ -42,11 +42,7 @@
#define CONFIG_UART_BAUDRATE 921600
#define CONFIG_UART_DEADLOCKABLE
#define SSP_CLK_DIVISOR_FAST 2
#define SSP_CLK_DIVISOR_SLOW 250
#define SSP_CLK_DIVISOR_FPGA_FAST 6
#define SSP_CLK_DIVISOR_FPGA_SLOW 20
#define SSP_CLK_DIVISOR 2
#define SNES_RESET_REG LPC_GPIO1
#define SNES_RESET_BIT 26

2
src/fpga_spi.c
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@ -143,7 +143,7 @@
#include "sdnative.h"
void fpga_spi_init(void) {
spi_init(SPI_SPEED_FAST);
spi_init();
BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0;
}

3
src/fpga_spi.h
View File

@ -47,9 +47,6 @@
#define FPGA_TX_BLOCK(x,y) spi_tx_block(x,y)
#define FPGA_RX_BLOCK(x,y) spi_rx_block(x,y)
#define FPGA_SPI_FAST() spi_set_speed(SPI_SPEED_FPGA_FAST)
#define FPGA_SPI_SLOW() spi_set_speed(SPI_SPEED_FPGA_SLOW)
#define FEAT_213F (1 << 4)
#define FEAT_MSU1 (1 << 3)
#define FEAT_SRTC (1 << 2)

34
src/spi.c
View File

@ -36,21 +36,13 @@ void spi_preinit() {
BITBAND(LPC_SC->SSP_PCLKREG, SSP_PCLKBIT) = 1;
}
void spi_init(spi_speed_t speed) {
void spi_init() {
/* configure data format - 8 bits, SPI, CPOL=0, CPHA=0, 1 clock per bit */
SSP_REGS->CR0 = (8-1);
/* set clock prescaler */
if (speed == SPI_SPEED_FAST) {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
} else if (speed == SPI_SPEED_SLOW) {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
} else if (speed == SPI_SPEED_FPGA_FAST) {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
} else {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
}
SSP_REGS->CPSR = SSP_CLK_DIVISOR;
/* Enable SSP */
SSP_REGS->CR1 = BV(1);
@ -189,25 +181,3 @@ void spi_rx_block(void *ptr, unsigned int length) {
SSP_REGS->DMACR = 0;
}
}
void spi_set_speed(spi_speed_t speed) {
/* Wait until TX fifo is empty */
while (!BITBAND(SSP_REGS->SR, 0)) ;
/* Disable SSP (FIXME: Is this required?) */
SSP_REGS->CR1 = 0;
/* Change clock divisor */
if (speed == SPI_SPEED_FAST) {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_FAST;
} else if (speed == SPI_SPEED_SLOW) {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_SLOW;
} else if (speed == SPI_SPEED_FPGA_FAST) {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_FAST;
} else {
SSP_REGS->CPSR = SSP_CLK_DIVISOR_FPGA_SLOW;
}
/* Enable SSP */
SSP_REGS->CR1 = BV(1);
}

5
src/spi.h
View File

@ -42,7 +42,7 @@ typedef enum { SPI_SPEED_FAST, SPI_SPEED_SLOW, SPI_SPEED_FPGA_FAST, SPI_SPEED_FP
void spi_preinit(void);
/* Initialize SPI interface */
void spi_init(spi_speed_t speed);
void spi_init(void);
/* Transmit a single byte */
void spi_tx_byte(uint8_t data);
@ -59,9 +59,6 @@ uint8_t spi_rx_byte(void);
/* Receive a data block */
void spi_rx_block(void *data, unsigned int length);
/* Switch speed of SPI interface */
void spi_set_speed(spi_speed_t speed);
/* wait for SPI TX FIFO to become empty */
void spi_tx_sync(void);