Initial Commit
This commit is contained in:
ikari
118
verilog/sd2snes/address.v
Normal file
118
verilog/sd2snes/address.v
Normal file
@@ -0,0 +1,118 @@
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`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: address
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Address logic w/ SaveRAM masking
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.02 - All new combinatorial glory. fucking slow.
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module address(
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input CLK,
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input [2:0] MAPPER, // AVR detected mapper
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input [23:0] SNES_ADDR, // requested address from SNES
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input SNES_CS, // "CART" pin from SNES (active low)
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output [20:0] SRAM_ADDR, // Address to request from SRAM
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output [3:0] ROM_SEL, // which SRAM unit to access (active low)
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input AVR_ADDR_RESET, // reset AVR sequence (active low)
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input AVR_NEXTADDR, // next byte request from AVR
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input AVR_ENA, // enable AVR master mode (active low)
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input AVR_ADDR_EN, // enable address counter (active low)
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input [1:0] AVR_BANK, // which bank does the AVR want
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input MODE, // AVR(1) or SNES(0) ("bus phase")
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output IS_SAVERAM, // address/CS mapped as SRAM?
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output IS_ROM, // address mapped as ROM?
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input AVR_NEXTADDR_CURR,
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input AVR_NEXTADDR_PREV
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);
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reg [22:0] SRAM_ADDR_BUF;
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reg [3:0] ROM_SEL_BUF;
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reg [3:0] AVR_ROM_SEL_BUF;
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reg [20:0] AVR_ADDR;
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reg [3:0] CS_ARRAY[3:0];
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wire [3:0] CURRENT_ROM_SEL;
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wire [22:0] SRAM_ADDR_FULL;
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initial begin
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AVR_ADDR = 21'b0;
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CS_ARRAY[0] = 4'b1110;
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CS_ARRAY[1] = 4'b1101;
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CS_ARRAY[2] = 4'b1011;
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CS_ARRAY[3] = 4'b0111;
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end
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/* currently supported mappers:
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Index Mapper
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000 HiROM
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001 LoROM
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*/
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/* HiROM: SRAM @ Bank 0x20-0x3f, 0xa0-0xbf
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Offset 6000-7fff */
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assign IS_SAVERAM = ((MAPPER == 3'b000) ? (!SNES_ADDR[22]
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& SNES_ADDR[21]
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& &SNES_ADDR[14:13]
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& !SNES_ADDR[15]
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)
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/* LoROM: SRAM @ Bank 0x70-0x7f, 0xf0-0xff
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Offset 0000-7fff */
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:(MAPPER == 3'b001) ? (&SNES_ADDR[22:20]
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& !SNES_ADDR[15]
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& !SNES_CS)
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: 1'b0);
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assign IS_ROM = ((MAPPER == 3'b000) ? ( (!SNES_ADDR[22]
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& SNES_ADDR[15])
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|(SNES_ADDR[22]))
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:(MAPPER == 3'b001) ? ( (SNES_ADDR[15]) )
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: 1'b0);
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assign SRAM_ADDR_FULL = (MODE) ? AVR_ADDR
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: ((MAPPER == 3'b000) ?
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(IS_SAVERAM ? SNES_ADDR[14:0] - 15'h6000
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: SNES_ADDR[22:0])
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:(MAPPER == 3'b001) ?
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(IS_SAVERAM ? SNES_ADDR[14:0]
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: {1'b0, SNES_ADDR[22:16], SNES_ADDR[14:0]})
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: 21'b0);
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assign SRAM_BANK = SRAM_ADDR_FULL[22:21];
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assign SRAM_ADDR = SRAM_ADDR_FULL[20:0];
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assign ROM_SEL = (MODE) ? CS_ARRAY[AVR_BANK] : IS_SAVERAM ? 4'b0111 : 4'b1110; // CS_ARRAY[SRAM_BANK];
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//assign ROM_SEL = 4'b1110;
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always @(posedge CLK) begin
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if(AVR_NEXTADDR_CURR) begin
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if(!AVR_NEXTADDR_PREV) begin
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if(!AVR_ADDR_RESET)
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AVR_ADDR <= 21'b0;
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else if (!AVR_ADDR_EN)
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AVR_ADDR <= AVR_ADDR + 1;
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end
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end
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end
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/*
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always @(posedge AVR_NEXTADDR) begin
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if (!AVR_ADDR_RESET)
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AVR_ADDR <= 21'b0;
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else if (!AVR_ADDR_EN)
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AVR_ADDR <= AVR_ADDR + 1;
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end
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*/
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endmodule
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83
verilog/sd2snes/data.v
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83
verilog/sd2snes/data.v
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@@ -0,0 +1,83 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:03:06 05/13/2009
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// Design Name:
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// Module Name: data
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module data(
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input CLK,
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input SNES_READ,
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input SNES_WRITE,
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input AVR_READ,
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input AVR_WRITE,
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inout [7:0] SNES_DATA,
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inout [7:0] SRAM_DATA,
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inout [7:0] AVR_DATA,
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input MODE,
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input SNES_DATA_TO_MEM,
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input AVR_DATA_TO_MEM,
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input SRAM_DATA_TO_SNES_MEM,
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input SRAM_DATA_TO_AVR_MEM,
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input AVR_ENA,
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input AVR_NEXTADDR_PREV,
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input AVR_NEXTADDR_CURR
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);
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reg [7:0] SNES_IN_MEM;
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reg [7:0] SNES_OUT_MEM;
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reg [7:0] AVR_IN_MEM;
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reg [7:0] AVR_OUT_MEM;
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assign SNES_DATA = SNES_READ ? 8'bZ : SNES_OUT_MEM;
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assign AVR_DATA = !AVR_ENA ? (!AVR_READ ? SRAM_DATA : 8'bZ)
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: (AVR_READ ? 8'bZ : AVR_OUT_MEM);
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assign SRAM_DATA = !AVR_ENA ? (!AVR_WRITE ? AVR_DATA : 8'bZ)// /**/ : 8'bZ;
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: MODE ? (!AVR_WRITE ? AVR_IN_MEM : 8'bZ)
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: (!SNES_WRITE ? SNES_IN_MEM : 8'bZ);
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always @(posedge CLK) begin
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if(SNES_DATA_TO_MEM)
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SNES_IN_MEM <= SNES_DATA;
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if(AVR_DATA_TO_MEM)
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AVR_IN_MEM <= AVR_DATA;
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if(SRAM_DATA_TO_SNES_MEM)
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SNES_OUT_MEM <= SRAM_DATA;
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if(SRAM_DATA_TO_AVR_MEM)
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AVR_OUT_MEM <= SRAM_DATA;
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end
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/*
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always @(posedge SNES_DATA_TO_MEM) begin
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SNES_IN_MEM <= SNES_DATA;
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end
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always @(posedge AVR_DATA_TO_MEM) begin
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AVR_IN_MEM <= AVR_DATA;
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end
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always @(posedge SRAM_DATA_TO_SNES_MEM) begin
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SNES_OUT_MEM <= SRAM_DATA;
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end
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always @(posedge SRAM_DATA_TO_AVR_MEM) begin
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AVR_OUT_MEM <= SRAM_DATA;
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end
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*/
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endmodule
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70
verilog/sd2snes/dcm.v
Normal file
70
verilog/sd2snes/dcm.v
Normal file
@@ -0,0 +1,70 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 13:06:52 06/28/2009
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// Design Name:
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// Module Name: dcm
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module my_dcm (
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input CLKIN,
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input CLKFB,
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output CLK2X
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);
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// DCM: Digital Clock Manager Circuit
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// Spartan-3
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// Xilinx HDL Language Template, version 11.1
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DCM #(
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.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
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.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
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.CLKFX_MULTIPLY(16), // Can be any integer from 2 to 32
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.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
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.CLKIN_PERIOD(0.0), // Specify period of input clock
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.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
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.CLK_FEEDBACK("2X"), // Specify clock feedback of NONE, 1X or 2X
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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// an integer from 0 to 15
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.FACTORY_JF(16'hC080), // FACTORY JF values
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.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
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.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_inst (
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.CLK0(CLK0), // 0 degree DCM CLK output
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.CLK180(CLK180), // 180 degree DCM CLK output
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.CLK270(CLK270), // 270 degree DCM CLK output
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.CLK2X(CLK2X), // 2X DCM CLK output
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.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
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.CLK90(CLK90), // 90 degree DCM CLK output
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.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
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.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
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.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
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.LOCKED(LOCKED), // DCM LOCK status output
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.PSDONE(PSDONE), // Dynamic phase adjust done output
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.STATUS(STATUS), // 8-bit DCM status bits output
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.CLKFB(CLKFB), // DCM clock feedback
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.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
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.PSCLK(PSCLK), // Dynamic phase adjust clock input
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.PSEN(PSEN), // Dynamic phase adjust enable input
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.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
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.RST(RST) // DCM asynchronous reset input
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);
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assign RST=0;
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endmodule
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191
verilog/sd2snes/main.ucf
Normal file
191
verilog/sd2snes/main.ucf
Normal file
@@ -0,0 +1,191 @@
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# INST "AVR_NEXTADDR_BUFGP" LOC = BUFGMUX7;
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# INST "CLK_BUFGP" LOC = BUFGMUX0;
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NET "AVR_BANK[0]" LOC = P56;
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NET "AVR_BANK[1]" LOC = P57;
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NET "AVR_ENA" LOC = P40;
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NET "AVR_READ" LOC = P41;
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NET "MAPPER[0]" LOC = P68;
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NET "MAPPER[1]" LOC = P69;
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NET "MAPPER[2]" LOC = P70;
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NET "ROM_SEL[0]" LOC = P124;
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NET "ROM_SEL[1]" LOC = P125;
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NET "ROM_SEL[2]" LOC = P122;
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NET "ROM_SEL[3]" LOC = P123;
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NET "SNES_ADDR[0]" LOC = P1;
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NET "SNES_ADDR[10]" LOC = P13;
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NET "SNES_ADDR[11]" LOC = P14;
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NET "SNES_ADDR[12]" LOC = P15;
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NET "SNES_ADDR[13]" LOC = P17;
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NET "SNES_ADDR[14]" LOC = P18;
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NET "SNES_ADDR[15]" LOC = P20;
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NET "SNES_ADDR[16]" LOC = P21;
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NET "SNES_ADDR[17]" LOC = P23;
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NET "SNES_ADDR[18]" LOC = P24;
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NET "SNES_ADDR[19]" LOC = P25;
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NET "SNES_ADDR[1]" LOC = P2;
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NET "SNES_ADDR[20]" LOC = P26;
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NET "SNES_ADDR[21]" LOC = P27;
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NET "SNES_ADDR[22]" LOC = P28;
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NET "SNES_ADDR[23]" LOC = P30;
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NET "SNES_ADDR[2]" LOC = P4;
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NET "SNES_ADDR[3]" LOC = P5;
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NET "SNES_ADDR[4]" LOC = P6;
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NET "SNES_ADDR[5]" LOC = P7;
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NET "SNES_ADDR[6]" LOC = P8;
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NET "SNES_ADDR[7]" LOC = P10;
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NET "SNES_ADDR[8]" LOC = P11;
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NET "SNES_ADDR[9]" LOC = P12;
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NET "SRAM_ADDR[0]" LOC = P92;
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NET "SRAM_ADDR[10]" LOC = P104;
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NET "SRAM_ADDR[11]" LOC = P105;
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NET "SRAM_ADDR[12]" LOC = P107;
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NET "SRAM_ADDR[13]" LOC = P108;
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NET "SRAM_ADDR[14]" LOC = P73;
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NET "SRAM_ADDR[15]" LOC = P74;
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NET "SRAM_ADDR[16]" LOC = P76;
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NET "SRAM_ADDR[17]" LOC = P77;
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NET "SRAM_ADDR[18]" LOC = P78;
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NET "SRAM_ADDR[19]" LOC = P79;
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NET "SRAM_ADDR[1]" LOC = P93;
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NET "SRAM_ADDR[20]" LOC = P80;
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NET "SRAM_ADDR[2]" LOC = P95;
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NET "SRAM_ADDR[3]" LOC = P96;
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NET "SRAM_ADDR[4]" LOC = P97;
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NET "SRAM_ADDR[5]" LOC = P98;
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NET "SRAM_ADDR[6]" LOC = P99;
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NET "SRAM_ADDR[7]" LOC = P100;
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NET "SRAM_ADDR[8]" LOC = P102;
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NET "SRAM_ADDR[9]" LOC = P103;
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NET "SRAM_DATA[0]" LOC = P82;
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NET "SRAM_DATA[1]" LOC = P83;
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NET "SRAM_DATA[2]" LOC = P84;
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NET "SRAM_DATA[3]" LOC = P85;
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NET "SRAM_DATA[4]" LOC = P86;
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NET "SRAM_DATA[5]" LOC = P87;
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NET "SRAM_DATA[6]" LOC = P89;
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NET "SRAM_DATA[7]" LOC = P90;
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NET "SRAM_OE" LOC = P118;
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NET "SRAM_WE" LOC = P119;
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NET "AVR_ADDR_RESET" LOC = P44;
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NET "CLKIN" LOC = P55;
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NET "AVR_NEXTADDR" LOC = P128;
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NET "SNES_READ" LOC = P31;
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NET "SNES_WRITE" LOC = P32;
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NET "AVR_WRITE" LOC = P58;
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NET "SNES_CS" LOC = P52;
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NET "AVR_ADDR_EN" LOC = P53;
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NET "CLK" TNM_NET = CLK;
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NET "AVR_DATA[0]" LOC = P46;
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NET "AVR_DATA[1]" LOC = P47;
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NET "AVR_DATA[2]" LOC = P50;
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NET "AVR_DATA[3]" LOC = P51;
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NET "AVR_DATA[4]" LOC = P59;
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NET "AVR_DATA[5]" LOC = P60;
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NET "AVR_DATA[6]" LOC = P63;
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NET "AVR_DATA[7]" LOC = P65;
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NET "SNES_DATA[0]" LOC = P129;
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NET "SNES_DATA[1]" LOC = P130;
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NET "SNES_DATA[2]" LOC = P131;
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NET "SNES_DATA[3]" LOC = P132;
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NET "SNES_DATA[4]" LOC = P135;
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NET "SNES_DATA[5]" LOC = P137;
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NET "SNES_DATA[6]" LOC = P140;
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NET "SNES_DATA[7]" LOC = P141;
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NET "SNES_DATABUS_DIR" LOC = P35;
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NET "SNES_DATABUS_OE" LOC = P33;
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NET "MODE" LOC = P112;
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NET "CLKIN" TNM_NET = CLKIN;
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TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 MHz HIGH 50 %;
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NET "AVR_ADDR_EN" IOSTANDARD = LVCMOS33;
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NET "AVR_ADDR_RESET" IOSTANDARD = LVCMOS33;
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NET "AVR_BANK[0]" IOSTANDARD = LVCMOS33;
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NET "AVR_BANK[1]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[0]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[1]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[2]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[3]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[4]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[5]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[6]" IOSTANDARD = LVCMOS33;
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NET "AVR_DATA[7]" IOSTANDARD = LVCMOS33;
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NET "AVR_ENA" IOSTANDARD = LVCMOS33;
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NET "AVR_NEXTADDR" IOSTANDARD = LVCMOS33;
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NET "AVR_READ" IOSTANDARD = LVCMOS33;
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NET "AVR_WRITE" IOSTANDARD = LVCMOS33;
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NET "CLKIN" IOSTANDARD = LVCMOS33;
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NET "MAPPER[0]" IOSTANDARD = LVCMOS33;
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NET "MAPPER[1]" IOSTANDARD = LVCMOS33;
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NET "MAPPER[2]" IOSTANDARD = LVCMOS33;
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NET "MODE" IOSTANDARD = LVCMOS33;
|
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NET "ROM_SEL[0]" IOSTANDARD = LVCMOS33;
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NET "ROM_SEL[1]" IOSTANDARD = LVCMOS33;
|
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NET "ROM_SEL[2]" IOSTANDARD = LVCMOS33;
|
||||
NET "ROM_SEL[3]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[12]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[13]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[14]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[15]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[16]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[17]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[18]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[19]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[1]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[20]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[21]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[22]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[23]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[2]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[3]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[4]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[5]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[6]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[7]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[8]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_ADDR[9]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_CS" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATABUS_DIR" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATABUS_OE" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[0]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[1]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[2]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[3]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[4]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[5]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[6]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_DATA[7]" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_READ" IOSTANDARD = LVCMOS33;
|
||||
NET "SNES_WRITE" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[0]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[10]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[11]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[12]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[13]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[14]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[15]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[16]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[17]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[18]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[19]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[1]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[20]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[2]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[3]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[4]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[5]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[6]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[7]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[8]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_ADDR[9]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[0]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[1]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[2]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[3]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[4]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[5]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[6]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_DATA[7]" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_OE" IOSTANDARD = LVCMOS33;
|
||||
NET "SRAM_WE" IOSTANDARD = LVCMOS33;
|
||||
299
verilog/sd2snes/main.v
Normal file
299
verilog/sd2snes/main.v
Normal file
@@ -0,0 +1,299 @@
|
||||
`timescale 1 ns / 1 ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Rehkopf
|
||||
// Engineer: Rehkopf
|
||||
//
|
||||
// Create Date: 01:13:46 05/09/2009
|
||||
// Design Name:
|
||||
// Module Name: main
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description: Master Control FSM
|
||||
//
|
||||
// Dependencies: address
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module main(
|
||||
input CLKIN,
|
||||
input [2:0] MAPPER,
|
||||
input [23:0] SNES_ADDR,
|
||||
input SNES_READ,
|
||||
input SNES_WRITE,
|
||||
input SNES_CS,
|
||||
inout [7:0] SNES_DATA,
|
||||
inout [7:0] SRAM_DATA,
|
||||
inout [7:0] AVR_DATA,
|
||||
output [20:0] SRAM_ADDR,
|
||||
output [3:0] ROM_SEL,
|
||||
output SRAM_OE,
|
||||
output SRAM_WE,
|
||||
output SNES_DATABUS_OE,
|
||||
output SNES_DATABUS_DIR,
|
||||
input AVR_ADDR_RESET,
|
||||
input AVR_ADDR_EN,
|
||||
input AVR_READ,
|
||||
input AVR_WRITE,
|
||||
input AVR_NEXTADDR,
|
||||
input AVR_ENA,
|
||||
input [1:0] AVR_BANK,
|
||||
output MODE
|
||||
);
|
||||
|
||||
my_dcm snes_dcm(.CLKIN(CLKIN),
|
||||
.CLK2X(CLK),
|
||||
.CLKFB(CLKFB)
|
||||
);
|
||||
|
||||
assign CLKFB = CLK;
|
||||
|
||||
address snes_addr(
|
||||
.CLK(CLK),
|
||||
.MAPPER(MAPPER),
|
||||
.SNES_ADDR(SNES_ADDR), // requested address from SNES
|
||||
.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
|
||||
.SRAM_ADDR(SRAM_ADDR), // Address to request from SRAM (active low)
|
||||
.ROM_SEL(ROM_SEL), // which SRAM unit to access
|
||||
.AVR_ADDR_RESET(AVR_ADDR_RESET), // reset AVR sequence (active low)
|
||||
.AVR_NEXTADDR(AVR_NEXTADDR), // next byte request from AVR
|
||||
.AVR_ENA(AVR_ENA), // enable AVR mode (active low)
|
||||
.AVR_ADDR_EN(AVR_ADDR_EN), // enable AVR address counter (active low)
|
||||
.AVR_BANK(AVR_BANK), // which bank does the AVR want
|
||||
.MODE(MODE), // AVR(1) or SNES(0) ("bus phase")
|
||||
.IS_SAVERAM(IS_SAVERAM),
|
||||
.IS_ROM(IS_ROM),
|
||||
.AVR_NEXTADDR_PREV(AVR_NEXTADDR_PREV),
|
||||
.AVR_NEXTADDR_CURR(AVR_NEXTADDR_CURR)
|
||||
);
|
||||
|
||||
data snes_data(.CLK(CLK),
|
||||
.SNES_READ(SNES_READ),
|
||||
.SNES_WRITE(SNES_WRITE),
|
||||
.AVR_READ(AVR_READ),
|
||||
.AVR_WRITE(AVR_WRITE),
|
||||
.SNES_DATA(SNES_DATA),
|
||||
.SRAM_DATA(SRAM_DATA),
|
||||
.AVR_DATA(AVR_DATA),
|
||||
.MODE(MODE),
|
||||
.SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
|
||||
.AVR_DATA_TO_MEM(AVR_DATA_TO_MEM),
|
||||
.SRAM_DATA_TO_SNES_MEM(SRAM_DATA_TO_SNES_MEM),
|
||||
.SRAM_DATA_TO_AVR_MEM(SRAM_DATA_TO_AVR_MEM),
|
||||
.AVR_ENA(AVR_ENA),
|
||||
.AVR_NEXTADDR_PREV(AVR_NEXTADDR_PREV),
|
||||
.AVR_NEXTADDR_CURR(AVR_NEXTADDR_CURR)
|
||||
);
|
||||
|
||||
parameter MODE_SNES = 1'b0;
|
||||
parameter MODE_AVR = 1'b1;
|
||||
|
||||
parameter STATE_0 = 8'b00000001;
|
||||
parameter STATE_1 = 8'b00000010;
|
||||
parameter STATE_2 = 8'b00000100;
|
||||
parameter STATE_3 = 8'b00001000;
|
||||
parameter STATE_4 = 8'b00010000;
|
||||
parameter STATE_5 = 8'b00100000;
|
||||
parameter STATE_6 = 8'b01000000;
|
||||
parameter STATE_7 = 8'b10000000;
|
||||
|
||||
reg [7:0] STATE;
|
||||
reg [2:0] STATEIDX;
|
||||
|
||||
reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK;
|
||||
reg SRAM_WE_MASK;
|
||||
reg SRAM_OE_MASK;
|
||||
|
||||
reg [7:0] SRAM_WE_ARRAY [3:0];
|
||||
reg [7:0] SRAM_OE_ARRAY [3:0];
|
||||
|
||||
reg [7:0] SNES_DATA_TO_MEM_ARRAY[1:0];
|
||||
reg [7:0] AVR_DATA_TO_MEM_ARRAY[1:0];
|
||||
reg [7:0] SRAM_DATA_TO_SNES_MEM_ARRAY[1:0];
|
||||
reg [7:0] SRAM_DATA_TO_AVR_MEM_ARRAY[1:0];
|
||||
|
||||
reg [7:0] MODE_ARRAY;
|
||||
|
||||
reg SNES_READ_CYCLE;
|
||||
reg SNES_WRITE_CYCLE;
|
||||
reg AVR_READ_CYCLE;
|
||||
reg AVR_WRITE_CYCLE;
|
||||
|
||||
reg SNES_DATABUS_OE_BUF;
|
||||
reg SNES_DATABUS_DIR_BUF;
|
||||
|
||||
reg AVR_NEXTADDR_PREV_BUF;
|
||||
reg AVR_NEXTADDR_CURR_BUF;
|
||||
|
||||
wire SNES_RW;
|
||||
|
||||
assign MODE = !AVR_ENA ? MODE_AVR : MODE_ARRAY[STATEIDX];
|
||||
|
||||
assign SNES_RW = (SNES_READ & SNES_WRITE);
|
||||
|
||||
initial begin
|
||||
CYCLE_RESET = 0;
|
||||
CYCLE_RESET_ACK = 0;
|
||||
|
||||
STATE = STATE_7;
|
||||
STATEIDX = 7;
|
||||
SRAM_WE_MASK = 1'b1;
|
||||
SRAM_OE_MASK = 1'b1;
|
||||
SNES_READ_CYCLE = 1'b1;
|
||||
SNES_WRITE_CYCLE = 1'b1;
|
||||
AVR_READ_CYCLE = 1'b1;
|
||||
AVR_WRITE_CYCLE = 1'b1;
|
||||
|
||||
MODE_ARRAY = 8'b00011111;
|
||||
|
||||
SRAM_WE_ARRAY[2'b00] = 8'b10010011;
|
||||
SRAM_WE_ARRAY[2'b01] = 8'b10011111;
|
||||
SRAM_WE_ARRAY[2'b10] = 8'b11110011;
|
||||
SRAM_WE_ARRAY[2'b11] = 8'b11111111;
|
||||
|
||||
SRAM_OE_ARRAY[2'b00] = 8'b11111111;
|
||||
SRAM_OE_ARRAY[2'b01] = 8'b11100000;
|
||||
SRAM_OE_ARRAY[2'b10] = 8'b00011111;
|
||||
SRAM_OE_ARRAY[2'b11] = 8'b00000000;
|
||||
|
||||
SNES_DATA_TO_MEM_ARRAY[1'b0] = 8'b10000000;
|
||||
SNES_DATA_TO_MEM_ARRAY[1'b1] = 8'b00000000;
|
||||
|
||||
AVR_DATA_TO_MEM_ARRAY[1'b0] = 8'b00010000;
|
||||
AVR_DATA_TO_MEM_ARRAY[1'b1] = 8'b00000000;
|
||||
|
||||
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 8'b00000000;
|
||||
SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 8'b00100000;
|
||||
|
||||
SRAM_DATA_TO_AVR_MEM_ARRAY[1'b0] = 8'b00000000;
|
||||
SRAM_DATA_TO_AVR_MEM_ARRAY[1'b1] = 8'b00000010;
|
||||
|
||||
AVR_NEXTADDR_PREV_BUF = 0;
|
||||
AVR_NEXTADDR_CURR_BUF = 0;
|
||||
end
|
||||
|
||||
// falling edge of SNES /RD or /WR marks the beginning of a new cycle
|
||||
// SNES READ or WRITE always starts @posedge CLK !!
|
||||
// CPU cycle can be 6, 8 or 12 CLK cycles so we must satisfy
|
||||
// the minimum of 6 cycles to get everything done.
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (!SNES_RW) begin
|
||||
if (!CYCLE_RESET_ACK)
|
||||
CYCLE_RESET <= 1;
|
||||
else
|
||||
CYCLE_RESET <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
if (CYCLE_RESET && !CYCLE_RESET_ACK) begin
|
||||
CYCLE_RESET_ACK <= 1;
|
||||
STATE <= STATE_0;
|
||||
end else begin
|
||||
case (STATE)
|
||||
STATE_0:
|
||||
STATE <= STATE_1;
|
||||
STATE_1:
|
||||
STATE <= STATE_2;
|
||||
STATE_2:
|
||||
STATE <= STATE_3;
|
||||
STATE_3:
|
||||
STATE <= STATE_4;
|
||||
STATE_4:
|
||||
STATE <= STATE_5;
|
||||
STATE_5:
|
||||
STATE <= STATE_6;
|
||||
STATE_6:
|
||||
STATE <= STATE_7;
|
||||
STATE_7: begin
|
||||
if (SNES_RW) // check for end of SNES cycle to avoid looping
|
||||
CYCLE_RESET_ACK <= 0; // ready for new cycle
|
||||
STATE <= STATE_7;
|
||||
end
|
||||
default:
|
||||
STATE <= STATE_7;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
case (STATE)
|
||||
|
||||
STATE_7: begin
|
||||
SNES_READ_CYCLE <= SNES_READ;
|
||||
SNES_WRITE_CYCLE <= SNES_WRITE;
|
||||
AVR_READ_CYCLE <= AVR_READ;
|
||||
AVR_WRITE_CYCLE <= AVR_WRITE;
|
||||
STATEIDX <= 7;
|
||||
end
|
||||
STATE_0: begin
|
||||
STATEIDX <= 6;
|
||||
end
|
||||
|
||||
STATE_1: begin
|
||||
STATEIDX <= 5;
|
||||
end
|
||||
|
||||
STATE_2: begin
|
||||
STATEIDX <= 4;
|
||||
end
|
||||
|
||||
STATE_3: begin
|
||||
STATEIDX <= 3;
|
||||
end
|
||||
|
||||
STATE_4: begin
|
||||
STATEIDX <= 2;
|
||||
end
|
||||
|
||||
STATE_5: begin
|
||||
STATEIDX <= 1;
|
||||
end
|
||||
|
||||
STATE_6: begin
|
||||
STATEIDX <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// When in AVR mode, enable SRAM_WE according to AVR programming
|
||||
// else enable SRAM_WE according to state&cycle
|
||||
assign SRAM_WE = !AVR_ENA ? AVR_WRITE
|
||||
: ((!IS_SAVERAM & !MODE) | SRAM_WE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX]);
|
||||
|
||||
// When in AVR mode, enable SRAM_OE whenever not writing
|
||||
// else enable SRAM_OE according to state&cycle
|
||||
assign SRAM_OE = !AVR_ENA ? AVR_READ
|
||||
: SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
|
||||
|
||||
// dumb version
|
||||
//assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READ;
|
||||
//assign SRAM_WE = !AVR_ENA ? AVR_WRITE : 1'b1;
|
||||
|
||||
always @(posedge CLK) begin
|
||||
SNES_DATABUS_OE_BUF <= SNES_CS | (SNES_READ & SNES_WRITE);
|
||||
end
|
||||
|
||||
always @(posedge CLK) begin
|
||||
AVR_NEXTADDR_PREV_BUF <= AVR_NEXTADDR_CURR_BUF;
|
||||
AVR_NEXTADDR_CURR_BUF <= AVR_NEXTADDR;
|
||||
end
|
||||
|
||||
assign AVR_NEXTADDR_PREV = AVR_NEXTADDR_PREV_BUF;
|
||||
assign AVR_NEXTADDR_CURR = AVR_NEXTADDR_CURR_BUF;
|
||||
|
||||
//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
|
||||
assign SNES_DATABUS_OE = (IS_ROM & SNES_CS) | (!IS_ROM & !IS_SAVERAM) | (SNES_READ & SNES_WRITE);
|
||||
assign SNES_DATABUS_DIR = !SNES_WRITE ? 1'b0 : 1'b1;
|
||||
|
||||
assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
|
||||
assign AVR_DATA_TO_MEM = AVR_DATA_TO_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
|
||||
|
||||
assign SRAM_DATA_TO_SNES_MEM = SRAM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
|
||||
assign SRAM_DATA_TO_AVR_MEM = SRAM_DATA_TO_AVR_MEM_ARRAY[AVR_WRITE_CYCLE][STATEIDX];
|
||||
|
||||
endmodule
|
||||
80
verilog/sd2snes/sd2snes.xise
Normal file
80
verilog/sd2snes/sd2snes.xise
Normal file
@@ -0,0 +1,80 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s200"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/>
|
||||
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|main"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf_main"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tq144"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="sd2snes"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|tf_main"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|tf_main"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
|
||||
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<partitions>
|
||||
<partition xil_pn:name="/main"/>
|
||||
</partitions>
|
||||
|
||||
</project>
|
||||
136
verilog/sd2snes/tf_main.v
Normal file
136
verilog/sd2snes/tf_main.v
Normal file
@@ -0,0 +1,136 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 23:11:58 05/13/2009
|
||||
// Design Name: main
|
||||
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/tf_main.v
|
||||
// Project Name: sd2snes
|
||||
// Target Device:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Verilog Test Fixture created by ISE for module: main
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module tf_main;
|
||||
|
||||
// Inputs
|
||||
reg CLK;
|
||||
reg [2:0] MAPPER;
|
||||
reg [23:0] SNES_ADDR;
|
||||
reg SNES_READ;
|
||||
reg SNES_WRITE;
|
||||
reg SNES_CS;
|
||||
reg AVR_ADDR_RESET;
|
||||
reg AVR_WRITE;
|
||||
reg AVR_READ;
|
||||
reg AVR_NEXTADDR;
|
||||
reg AVR_ENA;
|
||||
reg [1:0] AVR_BANK;
|
||||
reg AVR_ADDR_EN;
|
||||
|
||||
// Outputs
|
||||
wire [20:0] SRAM_ADDR;
|
||||
wire [3:0] ROM_SEL;
|
||||
wire SRAM_OE;
|
||||
wire SRAM_WE;
|
||||
wire SNES_DATABUS_OE;
|
||||
wire SNES_DATABUS_DIR;
|
||||
wire MODE;
|
||||
|
||||
// Bidirs
|
||||
wire [7:0] SNES_DATA;
|
||||
wire [7:0] SRAM_DATA;
|
||||
wire [7:0] AVR_DATA;
|
||||
|
||||
reg [7:0] SRAM_DATA_BUF;
|
||||
reg [7:0] SNES_DATA_BUF;
|
||||
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
main uut (
|
||||
.CLKIN(CLK),
|
||||
.MAPPER(MAPPER),
|
||||
.SNES_ADDR(SNES_ADDR),
|
||||
.SNES_READ(SNES_READ),
|
||||
.SNES_WRITE(SNES_WRITE),
|
||||
.SNES_CS(SNES_CS),
|
||||
.SNES_DATA(SNES_DATA),
|
||||
.SRAM_DATA(SRAM_DATA),
|
||||
.AVR_DATA(AVR_DATA),
|
||||
.SRAM_ADDR(SRAM_ADDR),
|
||||
.ROM_SEL(ROM_SEL),
|
||||
.SRAM_OE(SRAM_OE),
|
||||
.SRAM_WE(SRAM_WE),
|
||||
.AVR_ADDR_RESET(AVR_ADDR_RESET),
|
||||
.AVR_WRITE(AVR_WRITE),
|
||||
.AVR_NEXTADDR(AVR_NEXTADDR),
|
||||
.AVR_ENA(AVR_ENA),
|
||||
.AVR_BANK(AVR_BANK),
|
||||
.AVR_READ(AVR_READ),
|
||||
.AVR_ADDR_EN(AVR_ADDR_EN),
|
||||
.SNES_DATABUS_OE(SNES_DATABUS_OE),
|
||||
.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
|
||||
.MODE(MODE)
|
||||
);
|
||||
|
||||
assign SRAM_DATA = SRAM_DATA_BUF;
|
||||
initial begin
|
||||
// Initialize Inputs
|
||||
CLK = 1;
|
||||
MAPPER = 0;
|
||||
SNES_ADDR = 24'h223456;
|
||||
SNES_READ = 1;
|
||||
SNES_WRITE = 1;
|
||||
SNES_CS = 0;
|
||||
AVR_ADDR_RESET = 1;
|
||||
AVR_WRITE = 1;
|
||||
AVR_READ = 0;
|
||||
AVR_NEXTADDR = 0;
|
||||
AVR_ENA = 1;
|
||||
AVR_BANK = 0;
|
||||
AVR_ADDR_EN = 0;
|
||||
SRAM_DATA_BUF = 8'hff;
|
||||
// Wait for global reset to finish
|
||||
#276;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
#276 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
SNES_ADDR <= 24'h123456;
|
||||
SNES_READ <= 0;
|
||||
#176;
|
||||
SNES_READ <= 1;
|
||||
#100;
|
||||
SNES_WRITE <= 0;
|
||||
#176;
|
||||
SNES_WRITE <= 1;
|
||||
#100;
|
||||
AVR_WRITE <= 0;
|
||||
SNES_READ <= 0;
|
||||
#276;
|
||||
// AVR_READ <= 1;
|
||||
// Add stimulus here
|
||||
end
|
||||
|
||||
always
|
||||
#23 CLK <= ~CLK;
|
||||
// always begin
|
||||
// #234 AVR_NEXTADDR <= ~AVR_NEXTADDR;
|
||||
// end
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user