preliminary MSU-1 audio support

2010-12-17 02:58:41 +01:00
parent 6c27daa30b
commit e2e628d6fb
11 changed files with 404 additions and 54 deletions
--- a/src/clock.c
+++ b/src/clock.c
@@ -27,7 +27,7 @@ void clock_init() {
   -> FPGA freq = 11289473.7Hz
   First, disable and disconnect PLL0.
 */
-  clock_disconnect();
+//  clock_disconnect();

 /* PLL is disabled and disconnected. setup PCLK NOW as it cannot be changed
   reliably with PLL0 connected.