From e2f33c28c99c6e243d59e5148a632c1c8494b0dd Mon Sep 17 00:00:00 2001
From: ikari <ikari@micecat.ath.cx>
Date: Mon, 27 Feb 2012 22:12:35 +0100
Subject: [PATCH] FPGA: pull-up SD clock

---
 verilog/sd2snes/main.ucf             | 1 +
 verilog/sd2snes/sd2snes.xise         | 4 ++--
 verilog/sd2snes_cx4/main.ucf         | 1 +
 verilog/sd2snes_cx4/sd2snes_cx4.xise | 4 ++--
 4 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index 4588d4f..67c55ed 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63;
 # PlanAhead Generated IO constraints 
 
 NET "SD_CLK" IOSTANDARD = LVCMOS33;
+NET "SD_CLK" PULLUP;
 NET "SD_CMD" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index 23cc2c5..d3a44ac 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -377,8 +377,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="6" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
diff --git a/verilog/sd2snes_cx4/main.ucf b/verilog/sd2snes_cx4/main.ucf
index d33fb74..4f1df7b 100644
--- a/verilog/sd2snes_cx4/main.ucf
+++ b/verilog/sd2snes_cx4/main.ucf
@@ -535,6 +535,7 @@ NET "SD_DAT[3]" LOC = P63;
 
 # PlanAhead Generated IO constraints 
 NET "SD_CLK" IOSTANDARD = LVCMOS33;
+NET "SD_CLK" PULLUP;
 NET "SD_CMD" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[0]" IOSTANDARD = LVCMOS33;
 NET "SD_DAT[1]" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise
index 683e3fd..b71aa02 100644
--- a/verilog/sd2snes_cx4/sd2snes_cx4.xise
+++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise
@@ -366,8 +366,8 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.updtest" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="4" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="11" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="11" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>