From e35cfe5cc6fd9ba0ca2b1855674b5efa29073d8f Mon Sep 17 00:00:00 2001 From: ikari Date: Mon, 19 Oct 2009 01:18:19 +0200 Subject: [PATCH] begin tab cleanup --- src/fpga.c | 8 ++++---- src/main.c | 50 +++++++++++++++++++++++++------------------------- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/fpga.c b/src/fpga.c index 240ae1d..846f84d 100644 --- a/src/fpga.c +++ b/src/fpga.c @@ -84,9 +84,9 @@ void set_cclk(uint8_t val) { void fpga_init() { DDRB |= _BV(PB3); // PB3 is output - DDRD &= ~_BV(PD7); // PD7 is input + DDRD &= ~_BV(PD7); // PD7 is input - DDRC = _BV(PC7); // for FPGA config, PC7 is output + DDRC = _BV(PC7); // for FPGA config, PC7 is output DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs set_cclk(0); // initial clk=0 @@ -99,7 +99,7 @@ int fpga_get_done(void) { void fpga_postinit() { DDRA |= _BV(PA0) | _BV(PA1) | _BV(PA2) | _BV(PA4) | _BV(PA5) | _BV(PA6); // MAPPER+NEXTADDR output DDRB |= _BV(PB2) | _BV(PB1) | _BV(PB0); // turn PB2 into output, enable AVR_BANK - DDRD |= _BV(PD7); // turn PD7 into output + DDRD |= _BV(PD7); // turn PD7 into output } void fpga_pgm(char* filename) { @@ -128,7 +128,7 @@ void fpga_pgm(char* filename) { for (;;) { // res = f_read(&in, file_buf, sizeof(file_buf), &bytes_read); bytes_read = file_read(); - if (file_res || bytes_read == 0) break; // error or eof + if (file_res || bytes_read == 0) break; // error or eof for(int i=0; i=0x20 && data <= 0x7a) { + if(data>=0x20 && data <= 0x7a) { uart_putc(data); - } else { + } else { // uart_putc('.'); uart_putc("0123456789ABCDEF"[data>>4]); uart_putc("0123456789ABCDEF"[data&15]); uart_putc(' '); - } + } // set_avr_bank(3); - } + } spi_none(); } while(1);