godzil/sd2snes
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

begin tab cleanup

Browse Source
This commit is contained in:
ikari 2009-10-19 01:18:19 +02:00
parent 85f2be9001
commit e35cfe5cc6
2 changed files with 29 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/fpga.c
View File

@ -84,9 +84,9 @@ void set_cclk(uint8_t val) {
void fpga_init() {
DDRB |= _BV(PB3); // PB3 is output
DDRD &= ~_BV(PD7); // PD7 is input
DDRD &= ~_BV(PD7); // PD7 is input
DDRC = _BV(PC7); // for FPGA config, PC7 is output
DDRC = _BV(PC7); // for FPGA config, PC7 is output
DDRD |= _BV(PD3) | _BV(PD4); // PD3, PD4 are outputs
set_cclk(0); // initial clk=0
@ -99,7 +99,7 @@ int fpga_get_done(void) {
void fpga_postinit() {
DDRA |= _BV(PA0) | _BV(PA1) | _BV(PA2) | _BV(PA4) | _BV(PA5) | _BV(PA6); // MAPPER+NEXTADDR output
DDRB |= _BV(PB2) | _BV(PB1) | _BV(PB0); // turn PB2 into output, enable AVR_BANK
DDRD |= _BV(PD7); // turn PD7 into output
DDRD |= _BV(PD7); // turn PD7 into output
}
void fpga_pgm(char* filename) {
@ -128,7 +128,7 @@ void fpga_pgm(char* filename) {
for (;;) {
// res = f_read(&in, file_buf, sizeof(file_buf), &bytes_read);
bytes_read = file_read();
if (file_res || bytes_read == 0) break; // error or eof
if (file_res || bytes_read == 0) break; // error or eof
for(int i=0; i<bytes_read; i++) {
//FPGA_SEND_BYTE(file_buf[i]);
FPGA_SEND_BYTE_SERIAL(file_buf[i]);

50
src/main.c
View File

@ -125,39 +125,39 @@ int main(void) {
#endif
#ifdef CLOCK_PRESCALE
clock_prescale_set(CLOCK_PRESCALE);
clock_prescale_set(CLOCK_PRESCALE);
#endif
spi_none();
snes_reset(1);
uart_init();
sei(); // suspected to reset the AVR when inserting an SD card
_delay_ms(100);
disk_init();
snes_init();
timer_init();
uart_puts_P(PSTR("\nsd2snes " VERSION));
uart_putcrlf();
snes_reset(1);
uart_init();
sei(); // suspected to reset the AVR when inserting an SD card
_delay_ms(100);
disk_init();
snes_init();
timer_init();
uart_puts_P(PSTR("\nsd2snes " VERSION));
uart_putcrlf();
file_init();
FATFS fatfs;
f_mount(0,&fatfs);
set_busy_led(1);
uart_putc('W');
fpga_init();
fpga_pgm("/sd2snes/main.bit");
FATFS fatfs;
f_mount(0,&fatfs);
set_busy_led(1);
uart_putc('W');
fpga_init();
fpga_pgm("/sd2snes/main.bit");
_delay_ms(100);
fpga_spi_init();
uart_putc('!');
uart_putc('!');
_delay_ms(100);
set_avr_ena(0);
set_avr_ena(0);
snes_reset(1);
*fs_path=0;
*fs_path=0;
uint16_t curr_dir_id = scan_dir(fs_path, 0); // generate files footprint
dprintf("curr dir id = %x\n", curr_dir_id);
uint16_t saved_dir_id;
if((get_db_id(&saved_dir_id) != FR_OK) // no database?
|| saved_dir_id != curr_dir_id) { // files changed?
|| saved_dir_id != curr_dir_id) { // files changed?
dprintf("saved dir id = %x\n", saved_dir_id);
_delay_ms(50);
dprintf("rebuilding database...");
@ -200,22 +200,22 @@ while(1) {
uart_putcrlf();
uint8_t buff[21];
for(uint8_t cnt=0; cnt<21; cnt++) {
uint8_t data=spiTransferByte(0x00);
uint8_t data=spiTransferByte(0x00);
buff[cnt]=data;
}
for(uint8_t cnt=0; cnt<21; cnt++) {
uint8_t data = buff[cnt];
_delay_ms(2);
if(data>=0x20 && data <= 0x7a) {
if(data>=0x20 && data <= 0x7a) {
uart_putc(data);
} else {
} else {
// uart_putc('.');
uart_putc("0123456789ABCDEF"[data>>4]);
uart_putc("0123456789ABCDEF"[data&15]);
uart_putc(' ');
}
}
// set_avr_bank(3);
}
}
spi_none();
}
while(1);