diff --git a/pcb/cart/sd2snes17.sch b/pcb/cart/sd2snes17.sch
index 2d8e572..3bd4abd 100644
Binary files a/pcb/cart/sd2snes17.sch and b/pcb/cart/sd2snes17.sch differ
diff --git a/src/memory.c b/src/memory.c
index e43d950..ed27c16 100644
--- a/src/memory.c
+++ b/src/memory.c
@@ -187,10 +187,5 @@ uint32_t calc_sram_crc(uint32_t size) {
uart_putc(hex[(crc>>24)&0xf]);
uart_putc(hex[(crc>>20)&0xf]);
uart_putc(hex[(crc>>16)&0xf]); */
- uart_putc(hex[(crc>>12)&0xf]);
- uart_putc(hex[(crc>>8)&0xf]);
- uart_putc(hex[(crc>>4)&0xf]);
- uart_putc(hex[(crc)&0xf]);
- uart_putcrlf();
return crc;
}
diff --git a/src/snes.c b/src/snes.c
index 89b7a11..9dbc180 100644
--- a/src/snes.c
+++ b/src/snes.c
@@ -53,11 +53,11 @@ void snes_main_loop() {
sram_crc = calc_sram_crc(sram_size);
if(sram_crc != sram_crc_old) {
uart_putc('U');
+ uart_puthexlong(sram_crc);
uart_putcrlf();
set_busy_led(1);
save_sram("/test.srm", sram_size, sram_base_addr);
set_busy_led(0);
}
sram_crc_old = sram_crc;
- uart_putc('.');
}
diff --git a/verilog/sd2snes/dcm.v b/verilog/sd2snes/dcm.v
index df75da1..7916673 100644
--- a/verilog/sd2snes/dcm.v
+++ b/verilog/sd2snes/dcm.v
@@ -23,7 +23,9 @@ module my_dcm (
input CLKFB,
output CLK2X,
output CLKFX,
- output CLK0
+ output CLK0,
+ output LOCKED,
+ input RST
);
// DCM: Digital Clock Manager Circuit
@@ -37,15 +39,16 @@ module my_dcm (
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
- .CLKIN_PERIOD(46000.0), // Specify period of input clock
+ .CLKIN_PERIOD(46.561), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
- .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
+ .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hC080), // FACTORY JF values
+// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
@@ -68,5 +71,4 @@ module my_dcm (
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
- assign RST=0;
endmodule
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index df137f3..0efde38 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -1,7 +1,6 @@
NET "CLKIN" TNM_NET = CLKIN;
-TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 MHz HIGH 50 %;
+TIMESPEC TS_CLKIN = PERIOD "CLKIN" 21.477 MHz HIGH 50 %;
NET "AVR_ENA" IOSTANDARD = LVCMOS33;
-NET "MODE" IOSTANDARD = LVCMOS33;
NET "SNES_ADDR[0]" IOSTANDARD = LVCMOS33;
NET "SNES_ADDR[10]" IOSTANDARD = LVCMOS33;
NET "SNES_ADDR[11]" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 095b86e..dba82ab 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -111,28 +111,64 @@ my_dcm snes_dcm(.CLKIN(CLKIN),
.CLK2X(CLK),
.CLKFB(CLKFB),
.CLKFX(CLK2),
- .CLK0(CLK0)
+ .CLK0(CLK0),
+ .LOCKED(DCM_LOCKED),
+ .RST(DCM_RST)
);
+
+my_dcm2 snes_dcm2(.CLKIN(CLK2),
+ .CLKFB(CLKFB2),
+ .CLKFX(FASTCLK),
+ .CLK0(CLK0_2));
+assign CLKFB2 = CLK0_2;
+/*
+reg DCM_RESET_ACK;
+reg DCM_RST_BUF;
+reg [1:0] DCM_LOCKEDr;
+assign DCM_RST = DCM_RST_BUF;
+assign DCM_FAIL = (DCM_LOCKEDr == 2'b10);
+
+always @(posedge CLKIN) begin
+ DCM_LOCKEDr <= {DCM_LOCKEDr[0], DCM_LOCKED};
+end
+
+always @(posedge CLKIN) begin
+ if (DCM_FAIL) begin
+ DCM_RST_BUF <= 1;
+ end else begin
+ DCM_RST_BUF <= 0;
+ end
+end*/
/*my_dcm snes_dcm2(.CLKIN(CLK),
.CLK2X(CLK2),
.CLKFB(CLKFB2),
.CLKFX(CLKFX2)
);*/
-assign CLKFB = CLK0;
+//assign CLKFB = CLK0;
//assign CLKFB2 = CLK2;
wire SNES_RW;
-reg SNES_READs;
-reg SNES_WRITEs;
-reg SNES_CSs;
+reg [1:0] SNES_READr;
+reg [1:0] SNES_WRITEr;
+reg [1:0] SNES_CSr;
+reg [1:0] SNES_CPU_CLKr;
+reg [3:0] SNES_RWr;
-assign SNES_RW = (SNES_READs & SNES_WRITEs);
+wire SNES_READs = (SNES_READr == 2'b11);
+wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
+wire SNES_CSs = (SNES_CSr == 2'b11);
+wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
+wire SNES_RW_start = (SNES_RWr == 4'b1110); // falling edge marks beginning of cycle
+
+assign SNES_RW = (SNES_READ & SNES_WRITE);
always @(posedge CLK2) begin
- SNES_READs <= SNES_READ;
- SNES_WRITEs <= SNES_WRITE;
- SNES_CSs <= SNES_CS;
+ SNES_READr <= {SNES_READr[0], SNES_READ};
+ SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
+ SNES_CSr <= {SNES_CSr[0], SNES_CS};
+ SNES_CPU_CLKr <= {SNES_CPU_CLKr[0], SNES_CPU_CLK};
+ SNES_RWr <= {SNES_RWr[2:0], SNES_RW};
end
reg ADDR_WRITE;
@@ -186,7 +222,7 @@ parameter STATE_7 = 10'b0010000000;
parameter STATE_8 = 10'b0100000000;
parameter STATE_9 = 10'b1000000000;
-reg [9:0] STATE;
+reg [10:0] STATE;
reg [3:0] STATEIDX;
reg STATE_RESET, CYCLE_RESET, CYCLE_RESET_ACK;
@@ -264,18 +300,25 @@ end
// the minimum of 6 cycles to get everything done.
always @(posedge CLK2) begin
- if (!SNES_RW /* || !AVR_ENA */) begin
- if (!CYCLE_RESET_ACK)
+ if (SNES_RW_start /* || !AVR_ENA */) //begin
+// if (!CYCLE_RESET_ACK)
CYCLE_RESET <= 1;
else
CYCLE_RESET <= 0;
- end
+// end
end
always @(posedge CLK2) begin
- if (CYCLE_RESET && !CYCLE_RESET_ACK) begin
- CYCLE_RESET_ACK <= 1;
+ if (SNES_RW_start/* && !CYCLE_RESET_ACK*/) begin
+// CYCLE_RESET_ACK <= 1;
STATE <= STATE_0;
+ SNES_READ_CYCLE <= SNES_READ;
+ SNES_WRITE_CYCLE <= SNES_WRITE;
+ AVR_READ_CYCLE <= AVR_READ;
+ AVR_WRITE_CYCLE <= AVR_WRITE;
+
+// end else if (!DCM_LOCKED) begin
+// CYCLE_RESET_ACK <= 0; // ready for new cycle
end else begin
case (STATE)
STATE_0:
@@ -311,10 +354,6 @@ always @(posedge CLK2) begin
case (STATE)
STATE_9: begin
- SNES_READ_CYCLE <= SNES_READs;
- SNES_WRITE_CYCLE <= SNES_WRITEs;
- AVR_READ_CYCLE <= AVR_READ;
- AVR_WRITE_CYCLE <= AVR_WRITE;
STATEIDX <= 9;
end
@@ -353,6 +392,8 @@ always @(posedge CLK2) begin
STATE_8: begin
STATEIDX <= 0;
end
+ default:
+ STATEIDX <= 9;
endcase
end
diff --git a/verilog/sd2snes/sd2snes.xise b/verilog/sd2snes/sd2snes.xise
index dbcc7a9..2be8f3d 100644
--- a/verilog/sd2snes/sd2snes.xise
+++ b/verilog/sd2snes/sd2snes.xise
@@ -61,6 +61,10 @@
+
+
+
+