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Firmware/bootloader: reduce bootloader size to 8192 bytes

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This commit is contained in:
ikari 2011-12-10 20:33:52 +01:00
parent 9943eca294
commit e5285f8196
5 changed files with 14 additions and 13 deletions
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6
src/bootldr/config.h
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@ -1,7 +1,7 @@
#ifndef _CONFIG_H #ifndef _CONFIG_H
#define _CONFIG_H #define _CONFIG_H
#define DEBUG_BL //#define DEBUG_BL
// #define DEBUG_SD // #define DEBUG_SD
// #define DEBUG_IRQ // #define DEBUG_IRQ
@ -19,7 +19,7 @@
#define DBG_BL while(0) #define DBG_BL while(0)
#endif #endif
#define FW_START (0x00003000L) #define FW_START (0x00002000L)
#define FLASH_SECTORS (17) #define FLASH_SECTORS (17)
@ -56,7 +56,7 @@
#define CONFIG_UART_PCLKDIV 1 #define CONFIG_UART_PCLKDIV 1
#define CONFIG_UART_TX_BUF_SHIFT 8 #define CONFIG_UART_TX_BUF_SHIFT 8
#define CONFIG_UART_BAUDRATE 921600 #define CONFIG_UART_BAUDRATE 921600
#define CONFIG_UART_DEADLOCKABLE //#define CONFIG_UART_DEADLOCKABLE
#define SSP_CLK_DIVISOR_FAST 2 #define SSP_CLK_DIVISOR_FAST 2
#define SSP_CLK_DIVISOR_SLOW 250 #define SSP_CLK_DIVISOR_SLOW 250

2
src/bootldr/iap.c
View File

@ -183,7 +183,7 @@ FLASH_RES flash_file(uint8_t *filename) {
return ERR_FLASH; return ERR_FLASH;
} }
} }
if(total_read != file_header.size) { if(total_read != (file_header.size + 0x100)) {
DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size); DBG_BL printf("wrote less data than expected! (%08lx vs. %08lx)\n", total_read, file_header.size);
DBG_UART uart_putc('X'); DBG_UART uart_putc('X');
return ERR_FILECHK; return ERR_FILECHK;

2
src/bootldr/lpc1754boot.ld
View File

@ -10,7 +10,7 @@ ENTRY(_start)
MEMORY MEMORY
{ {
flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x03000 flash (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000
ram (rwx) : ORIGIN = 0x10000000, LENGTH = 0x03fe0 /* leave room for IAP */ ram (rwx) : ORIGIN = 0x10000000, LENGTH = 0x03fe0 /* leave room for IAP */
ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000 ahbram (rwx) : ORIGIN = 0x2007C000, LENGTH = 0x04000
} }

7
src/bootldr/main.c
View File

@ -29,7 +29,7 @@ int main(void) {
SNES_CIC_PAIR_REG->FIODIR = BV(SNES_CIC_PAIR_BIT); SNES_CIC_PAIR_REG->FIODIR = BV(SNES_CIC_PAIR_BIT);
BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1; BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
/* LPC_GPIO2->FIODIR = BV(0) | BV(1) | BV(2); */ /* LPC_GPIO2->FIODIR = BV(0) | BV(1) | BV(2); */
LPC_GPIO0->FIODIR = BV(16); // LPC_GPIO0->FIODIR = BV(16);
/* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */ /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */ LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
@ -50,7 +50,7 @@ int main(void) {
writeled(0); writeled(0);
/* do this last because the peripheral init()s change PCLK dividers */ /* do this last because the peripheral init()s change PCLK dividers */
clock_init(); clock_init();
LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */ // LPC_PINCON->PINSEL0 |= BV(20) | BV(21); /* MAT3.0 (FPGA clock) */
sdn_init(); sdn_init();
DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28); DBG_BL printf("chksum=%08lx\n", *(uint32_t*)28);
DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY); DBG_BL printf("\n\nsd2snes mk.2 bootloader\nver.: " VER "\ncpu clock: %ld Hz\n", CONFIG_CPU_FREQUENCY);
@ -61,7 +61,8 @@ DBG_BL printf("PCONP=%lx\n", LPC_SC->PCONP);
LPC_TIM3->MCR=MR0R; LPC_TIM3->MCR=MR0R;
LPC_TIM3->MR0=1; LPC_TIM3->MR0=1;
LPC_TIM3->TCR=1; LPC_TIM3->TCR=1;
NVIC->ICER[0] = 0xffffffff;
NVIC->ICER[1] = 0xffffffff;
FLASH_RES res = flash_file((uint8_t*)"/sd2snes/firmware.img"); FLASH_RES res = flash_file((uint8_t*)"/sd2snes/firmware.img");
if(res == ERR_FLASHPREP || res == ERR_FLASHERASE || res == ERR_FLASH) { if(res == ERR_FLASHPREP || res == ERR_FLASHERASE || res == ERR_FLASH) {
rdyled(0); rdyled(0);

10
src/bootldr/uart.c
View File

@ -10,7 +10,7 @@
#include "uart.h" #include "uart.h"
#include "led.h" #include "led.h"
static uint8_t uart_lookupratio(float f_fr) { /*static uint8_t uart_lookupratio(float f_fr) {
uint16_t errors[72]={0,67,71,77,83,91,100,111,125, uint16_t errors[72]={0,67,71,77,83,91,100,111,125,
133,143,154,167,182,200,214,222,231, 133,143,154,167,182,200,214,222,231,
250,267,273,286,300,308,333,357,364, 250,267,273,286,300,308,333,357,364,
@ -45,8 +45,8 @@ static uint8_t uart_lookupratio(float f_fr) {
} }
return ratios[i_result]; return ratios[i_result];
} }
*/
static uint32_t baud2divisor(unsigned int baudrate) { /*static uint32_t baud2divisor(unsigned int baudrate) {
uint32_t int_ratio; uint32_t int_ratio;
uint32_t error; uint32_t error;
uint32_t dl=0; uint32_t dl=0;
@ -73,7 +73,7 @@ static uint32_t baud2divisor(unsigned int baudrate) {
return ((fract_ratio<<16)&0xff0000) | dl; return ((fract_ratio<<16)&0xff0000) | dl;
} }
} }
*/
static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT]; static char txbuf[1 << CONFIG_UART_TX_BUF_SHIFT];
static volatile unsigned int read_idx,write_idx; static volatile unsigned int read_idx,write_idx;
@ -170,7 +170,7 @@ void uart_init(void) {
/* set baud rate - no fractional stuff for now */ /* set baud rate - no fractional stuff for now */
UART_REGS->LCR = BV(7) | 3; // always 8n1 UART_REGS->LCR = BV(7) | 3; // always 8n1
div = baud2divisor(CONFIG_UART_BAUDRATE); div = 0x850004; // baud2divisor(CONFIG_UART_BAUDRATE);
UART_REGS->DLL = div & 0xff; UART_REGS->DLL = div & 0xff;
UART_REGS->DLM = (div >> 8) & 0xff; UART_REGS->DLM = (div >> 8) & 0xff;