From e57c4aa450ffe2d30ab52af797503c033dfe0b7f Mon Sep 17 00:00:00 2001 From: ikari Date: Sun, 23 Oct 2011 04:10:55 +0200 Subject: [PATCH] FPGA/cx4: initial commit --- verilog/sd2snes_cx4/address.v | 64 + verilog/sd2snes_cx4/cx4.v | 636 +++++ verilog/sd2snes_cx4/dac.v | 160 ++ verilog/sd2snes_cx4/dcm.v | 72 + verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v | 187 ++ verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco | 105 + .../sd2snes_cx4/ipcore_dir/cx4_datram.xise | 72 + verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v | 181 ++ verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco | 105 + .../sd2snes_cx4/ipcore_dir/cx4_datrom.xise | 72 + verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v | 2511 +++++++++++++++++ verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco | 68 + verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise | 378 +++ verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v | 181 ++ verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco | 105 + .../sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise | 72 + verilog/sd2snes_cx4/ipcore_dir/dac_buf.v | 181 ++ verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco | 105 + verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise | 79 + verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v | 181 ++ .../sd2snes_cx4/ipcore_dir/msu_databuf.xco | 105 + .../sd2snes_cx4/ipcore_dir/msu_databuf.xise | 79 + verilog/sd2snes_cx4/main.v | 564 ++++ verilog/sd2snes_cx4/msu.v | 194 ++ verilog/sd2snes_cx4/sd2snes_cx4.xise | 456 +++ verilog/sd2snes_cx4/sd_dma.v | 132 + verilog/sd2snes_cx4/spi.v | 113 + 27 files changed, 7158 insertions(+) create mode 100644 verilog/sd2snes_cx4/address.v create mode 100644 verilog/sd2snes_cx4/cx4.v create mode 100644 verilog/sd2snes_cx4/dac.v create mode 100644 verilog/sd2snes_cx4/dcm.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/dac_buf.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise create mode 100644 verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v create mode 100644 verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco create mode 100644 verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise create mode 100644 verilog/sd2snes_cx4/main.v create mode 100644 verilog/sd2snes_cx4/msu.v create mode 100644 verilog/sd2snes_cx4/sd2snes_cx4.xise create mode 100644 verilog/sd2snes_cx4/sd_dma.v create mode 100644 verilog/sd2snes_cx4/spi.v diff --git a/verilog/sd2snes_cx4/address.v b/verilog/sd2snes_cx4/address.v new file mode 100644 index 0000000..e62071d --- /dev/null +++ b/verilog/sd2snes_cx4/address.v @@ -0,0 +1,64 @@ +`timescale 1 ns / 1 ns +////////////////////////////////////////////////////////////////////////////////// +// Company: Rehkopf +// Engineer: Rehkopf +// +// Create Date: 01:13:46 05/09/2009 +// Design Name: +// Module Name: address +// Project Name: +// Target Devices: +// Tool versions: +// Description: Address logic w/ SaveRAM masking +// +// Dependencies: +// +// Revision: +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module address( + input CLK, + input [2:0] MAPPER, // MCU detected mapper + input [23:0] SNES_ADDR, // requested address from SNES + output [23:0] ROM_ADDR, // Address to request from SRAM0 + output ROM_SEL, // enable SRAM0 (active low) + output IS_SAVERAM, // address/CS mapped as SRAM? + output IS_ROM, // address mapped as ROM? + output IS_WRITABLE, // address somehow mapped as writable area? + input [23:0] SAVERAM_MASK, + input [23:0] ROM_MASK, + input use_msu1, + output msu_enable, + output cx4_enable +); + +wire [23:0] SRAM_SNES_ADDR; + +/* Cx4 mapper: + - LoROM (extended to 00-7d, 80-ff) + - MMIO @ 6000-7fff + */ + +assign IS_ROM = (SNES_ADDR[15]); + +assign SRAM_SNES_ADDR = ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]} + & ROM_MASK); + +assign ROM_ADDR = SRAM_SNES_ADDR; + +assign ROM_SEL = 1'b0; + +wire msu_enable_w = use_msu1 & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000)); +reg [5:0] msu_enable_r; +initial msu_enable_r = 6'b000000; +always @(posedge CLK) msu_enable_r <= {msu_enable_r[4:0], msu_enable_w}; +assign msu_enable = &msu_enable_r[5:2]; + +wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011)); +reg [5:0] cx4_enable_r; +initial cx4_enable_r = 6'b000000; +always @(posedge CLK) cx4_enable_r <= {cx4_enable_r[4:0], cx4_enable_w}; +assign cx4_enable = &cx4_enable_r[5:2]; + +endmodule diff --git a/verilog/sd2snes_cx4/cx4.v b/verilog/sd2snes_cx4/cx4.v new file mode 100644 index 0000000..97286be --- /dev/null +++ b/verilog/sd2snes_cx4/cx4.v @@ -0,0 +1,636 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:14:37 10/13/2011 +// Design Name: +// Module Name: cx4 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module cx4( + input [7:0] DI, + output [7:0] DO, + input [12:0] ADDR, + input CS, + input nRD, + input nWR, + input CLK, + input [23:0] DATROM_DI, + input DATROM_WE, + input [9:0] DATROM_ADDR, + input [7:0] BUS_DI, + output [23:0] BUS_ADDR, + output BUS_RRQ, + input BUS_RDY, + output cx4_active + ); + +reg [2:0] cx4_busy; +parameter BUSY_CACHE = 2'b00; +parameter BUSY_DMA = 2'b01; +parameter BUSY_CPU = 2'b10; + +wire datram_enable = CS & (ADDR[11:0] < 12'hc00); +wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] <= 8'b11000); +wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] > 8'b11000); +wire vector_enable = CS & (ADDR[12:5] == 8'b11111011); +wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11); +wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000); + +wire [7:0] DATRAM_DO; +reg [7:0] MMIO_DOr; +wire [7:0] MMIO_DO; +wire [7:0] STATUS_DO; +wire [7:0] VECTOR_DO; +wire [7:0] GPR_DO; + +assign DO = datram_enable ? DATRAM_DO + : mmio_enable ? MMIO_DO + : status_enable ? STATUS_DO + : vector_enable ? VECTOR_DO + : gpr_enable ? GPR_DO + : 8'h00; + +/* 0x1f40 - 0x1f52: MMIO + SNES: 8 bits / CX4: various */ +reg [23:0] cx4_mmio_dmasrc; +reg [15:0] cx4_mmio_dmalen; +reg [23:0] cx4_mmio_dmatgt; +reg cx4_mmio_cachepage; +reg [23:0] cx4_mmio_pgmoff; +reg [1:0] cx4_mmio_r1f4c; +reg [14:0] cx4_mmio_pgmpage; +reg [7:0] cx4_mmio_pc; +reg [7:0] cx4_mmio_r1f50; +reg cx4_mmio_r1f51; +reg cx4_mmio_r1f52; +/* 0x1f53 - 0x1f5f: status register */ +assign cx4_active = |cx4_busy; +/* 0x1f60 - 0x1f7f: reset vectors */ +reg [7:0] vector [31:0]; +/* 0x1f80 - 0x1faf (0x1fc0 - 0x1fef): general purpose register file + SNES: 8 bits / CX4: 24 bits */ +reg [7:0] gpr [47:0]; +wire [47:0] cpu_mul_result; + +reg [23:0] const [15:0]; + +reg [15:0] cachetag [1:0]; // 15: valid; 14-0: bank number +initial begin + cachetag[0] = 16'h0000; + cachetag[1] = 16'h0000; + cx4_busy = 3'b000; + cx4_mmio_pgmoff = 24'h000000; + cx4_mmio_pgmpage = 15'h0000; + cx4_mmio_dmasrc = 24'h000000; + cx4_mmio_dmalen = 16'h0000; + cx4_mmio_dmatgt = 24'h000000; + const[0] = 24'h000000; + const[1] = 24'hffffff; + const[2] = 24'h00ff00; + const[3] = 24'hff0000; + const[4] = 24'h00ffff; + const[5] = 24'hffff00; + const[6] = 24'h800000; + const[7] = 24'h7fffff; + const[8] = 24'h008000; + const[9] = 24'h007fff; + const[10] = 24'hff7fff; + const[11] = 24'hffff7f; + const[12] = 24'h010000; + const[13] = 24'hfeffff; + const[14] = 24'h000100; + const[15] = 24'h00feff; +end + +assign MMIO_DO = MMIO_DOr; +assign VECTOR_DO = vector [ADDR[4:0]]; +assign GPR_DO = gpr [ADDR[5:0]]; +assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0}; + +reg [7:0] DIr; +always @(posedge CLK) DIr <= DI; + +reg [4:0] datram_enable_sreg; +initial datram_enable_sreg = 5'b11111; +always @(posedge CLK) datram_enable_sreg <= {datram_enable_sreg[3:0], datram_enable}; + +reg [5:0] nWR_sreg; +always @(posedge CLK) nWR_sreg <= {nWR_sreg[4:0], nWR}; +wire WR_EN = (nWR_sreg[5:0] == 6'b000001); +wire DATRAM_WR_EN = datram_enable & WR_EN; +wire MMIO_WR_EN = mmio_enable & WR_EN; +wire VECTOR_WR_EN = vector_enable & WR_EN; +wire GPR_WR_EN = gpr_enable & WR_EN; + +reg [23:0] cpu_idb; // tmp register for reg file read + +/* Need to cache when: + 1f48 is written + AND (selected cache page is invalid + OR selected cache page does not contain requested page already) +*/ +reg CACHE_TRIG_ENr; +reg CACHE_TRIG_EN2r; +initial begin + CACHE_TRIG_ENr = 1'b0; + CACHE_TRIG_EN2r = 1'b0; +end +always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr; +wire CACHE_TRIG_EN = CACHE_TRIG_EN2r; + +reg DMA_TRIG_ENr; +initial DMA_TRIG_ENr = 1'b0; +wire DMA_TRIG_EN = DMA_TRIG_ENr; + +reg CACHE_BUS_RRQr; +reg DMA_BUS_RRQr; +initial begin + CACHE_BUS_RRQr = 1'b0; + DMA_BUS_RRQr = 1'b0; +end +assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr; + +initial begin + cx4_mmio_r1f50 = 8'h33; + cx4_mmio_r1f51 = 1'b0; + cx4_mmio_r1f52 = 1'b1; +end + +always @(posedge CLK) begin + case (ADDR[4:0]) + 5'h00: MMIO_DOr <= cx4_mmio_dmasrc[7:0]; // 1f40 + 5'h01: MMIO_DOr <= cx4_mmio_dmasrc[15:8]; // 1f41 + 5'h02: MMIO_DOr <= cx4_mmio_dmasrc[23:16]; // 1f42 + 5'h03: MMIO_DOr <= cx4_mmio_dmalen[7:0]; // 1f43 + 5'h04: MMIO_DOr <= cx4_mmio_dmalen[15:8]; // 1f44 + 5'h05: MMIO_DOr <= cx4_mmio_dmatgt[7:0]; // 1f45 + 5'h06: MMIO_DOr <= cx4_mmio_dmatgt[15:8]; // 1f46 + 5'h07: MMIO_DOr <= cx4_mmio_dmatgt[23:16]; // 1f47 + 5'h08: MMIO_DOr <= {7'b0, cx4_mmio_cachepage}; + 5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49 + 5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a + 5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b + 5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_r1f4c}; // 1f4c + 5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d + 5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e + 5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f + 5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50 + 5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51 + 5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52 + + 5'h13: MMIO_DOr <= cpu_mul_result[47:40]; // 1f40 + 5'h14: MMIO_DOr <= cpu_mul_result[39:32]; // 1f40 + 5'h15: MMIO_DOr <= cpu_mul_result[31:24]; // 1f40 + 5'h16: MMIO_DOr <= cpu_mul_result[23:16]; // 1f40 + 5'h17: MMIO_DOr <= cpu_mul_result[15:8]; // 1f40 + 5'h18: MMIO_DOr <= cpu_mul_result[7:0]; // 1f40 + + +// 5'h14: MMIO_DOr <= cachetag[0][15:8]; // 1f40 +// 5'h15: MMIO_DOr <= cachetag[0][7:0]; // 1f41 +// 5'h16: MMIO_DOr <= cachetag[1][15:8]; // 1f42 +// 5'h17: MMIO_DOr <= cachetag[1][7:0]; // 1f43 + default: MMIO_DOr <= 8'hff; + endcase +end + +always @(posedge CLK) begin + if(MMIO_WR_EN) begin + case(ADDR[4:0]) + 5'h00: cx4_mmio_dmasrc[7:0] <= DI; // 1f40 + 5'h01: cx4_mmio_dmasrc[15:8] <= DI; // 1f41 + 5'h02: cx4_mmio_dmasrc[23:16] <= DI; // 1f42 + 5'h03: cx4_mmio_dmalen[7:0] <= DI; // 1f43 + 5'h04: cx4_mmio_dmalen[15:8] <= DI; // 1f44 + 5'h05: cx4_mmio_dmatgt[7:0] <= DI; // 1f45 + 5'h06: cx4_mmio_dmatgt[15:8] <= DI; // 1f46 + 5'h07: begin + cx4_mmio_dmatgt[23:16] <= DI; // 1f47 + DMA_TRIG_ENr <= 1'b1; + end + 5'h08: begin + cx4_mmio_cachepage <= DI[0]; // 1f48 + CACHE_TRIG_ENr <= 1'b1; + end + 5'h09: cx4_mmio_pgmoff[7:0] <= DI; // 1f49 + 5'h0a: cx4_mmio_pgmoff[15:8] <= DI; // 1f4a + 5'h0b: cx4_mmio_pgmoff[23:16] <= DI; // 1f4b + 5'h0c: cx4_mmio_r1f4c <= DI[1:0]; // 1f4c + 5'h0d: cx4_mmio_pgmpage[7:0] <= DI; // 1f4d + 5'h0e: cx4_mmio_pgmpage[14:8] <= DI[6:0]; // 1f4e + 5'h0f: cx4_mmio_pc <= DI; // 1f4f + 5'h10: cx4_mmio_r1f50 <= DI & 8'h77; // 1f50 + 5'h11: cx4_mmio_r1f51 <= DI[0]; // 1f51 + 5'h12: cx4_mmio_r1f52 <= DI[0]; // 1f52 + endcase + end else begin + CACHE_TRIG_ENr <= 1'b0; + DMA_TRIG_ENr <= 1'b0; + end +end + +always @(posedge CLK) begin + if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DI; +end + +always @(posedge CLK) begin + if(GPR_WR_EN) gpr[ADDR[5:0]] <= DI; +end + +reg [4:0] CACHE_ST; +parameter ST_CACHE_IDLE = 5'b00001; +parameter ST_CACHE_START = 5'b00010; +parameter ST_CACHE_WAIT = 5'b00100; +parameter ST_CACHE_ADDR = 5'b01000; +parameter ST_CACHE_END = 5'b10000; +initial CACHE_ST = ST_CACHE_IDLE; + +reg [4:0] DMA_ST; +parameter ST_DMA_IDLE = 5'b00001; +parameter ST_DMA_START = 5'b00010; +parameter ST_DMA_WAIT = 5'b00100; +parameter ST_DMA_ADDR = 5'b01000; +parameter ST_DMA_END = 5'b10000; +initial DMA_ST = ST_DMA_IDLE; + +reg [23:0] CACHE_SRC_ADDRr; +wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]}; +reg [23:0] DMA_SRC_ADDRr; +wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]}; + +assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR + : cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR + : 24'h000000 /* XXX cx4_bus_addr */; + +reg cx4_pgmrom_we; +initial cx4_pgmrom_we = 1'b0; +reg [9:0] cx4_pgmrom_addr; +reg [19:0] cache_count; +initial cache_count = 20'b0; + +always @(posedge CLK) begin + case(CACHE_ST) + ST_CACHE_IDLE: begin + if(CACHE_TRIG_EN + & (~cachetag[cx4_mmio_cachepage][15] + | |(cachetag[cx4_mmio_cachepage][14:0] ^ cx4_mmio_pgmpage))) + begin + CACHE_ST <= ST_CACHE_START; + end else CACHE_ST <= ST_CACHE_IDLE; + end + ST_CACHE_START: begin + cx4_busy[BUSY_CACHE] <= 1'b1; + CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cx4_mmio_pgmpage, 9'b0}; + cx4_pgmrom_addr <= {cx4_mmio_cachepage, 9'b0}; + CACHE_ST <= ST_CACHE_WAIT; + cache_count <= 10'b0; + CACHE_BUS_RRQr <= 1'b1; + end + ST_CACHE_WAIT: begin + CACHE_BUS_RRQr <= 1'b0; + if(~CACHE_BUS_RRQr & BUS_RDY) begin + CACHE_ST <= ST_CACHE_ADDR; + cx4_pgmrom_we <= 1'b1; + cache_count <= cache_count + 1; + end else CACHE_ST <= ST_CACHE_WAIT; + end + ST_CACHE_ADDR: begin + cx4_pgmrom_we <= 1'b0; + CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1; + cx4_pgmrom_addr <= cx4_pgmrom_addr + 1; + if(cache_count == 9'h1ff) begin + cx4_busy[BUSY_CACHE] <= 1'b0; + cachetag[cx4_mmio_cachepage] <= {1'b1,cx4_mmio_pgmpage}; + CACHE_ST <= ST_CACHE_IDLE; + end else begin + CACHE_BUS_RRQr <= 1'b1; + CACHE_ST <= ST_CACHE_WAIT; + end + end + endcase +end + +reg cx4_datram_we; +initial cx4_datram_we = 1'b0; +reg [11:0] cx4_datram_addr; +reg [15:0] dma_count; +initial dma_count = 16'b0; + +always @(posedge CLK) begin + case(DMA_ST) + ST_DMA_IDLE: begin + if(DMA_TRIG_EN) begin + DMA_ST <= ST_DMA_START; + end else DMA_ST <= ST_DMA_IDLE; + end + ST_DMA_START: begin + cx4_busy[BUSY_DMA] <= 1'b1; + DMA_SRC_ADDRr <= cx4_mmio_dmasrc; + /* XXX Rename to DMA_TGT_ADDRr and switch */ + cx4_datram_addr <= (cx4_mmio_dmatgt & 24'h000fff); + DMA_ST <= ST_DMA_WAIT; + dma_count <= cx4_mmio_dmalen; + DMA_BUS_RRQr <= 1'b1; + end + ST_DMA_WAIT: begin + DMA_BUS_RRQr <= 1'b0; + if(~DMA_BUS_RRQr & BUS_RDY) begin + DMA_ST <= ST_DMA_ADDR; + /* XXX Rename to DMA_TGT_WEr and switch */ + cx4_datram_we <= 1'b1; + dma_count <= dma_count - 1; + end else DMA_ST <= ST_DMA_WAIT; + end + ST_DMA_ADDR: begin + /* XXX Rename to DMA_TGT_WEr and switch */ + cx4_datram_we <= 1'b0; + DMA_SRC_ADDRr <= DMA_SRC_ADDRr + 1; + cx4_datram_addr <= cx4_datram_addr + 1; + if(dma_count == 16'h0000) begin + cx4_busy[BUSY_DMA] <= 1'b0; + DMA_ST <= ST_DMA_IDLE; + end else begin + DMA_BUS_RRQr <= 1'b1; + DMA_ST <= ST_DMA_WAIT; + end + end + endcase +end + +/*************************** + =========== CPU =========== + ***************************/ +reg [7:0] CPU_STATE; +reg cpu_page; +reg [7:0] cpu_pc; +reg [8:0] cpu_stack [7:0]; +reg [2:0] cpu_sp; +wire [15:0] cpu_op_w; +reg [15:0] cpu_op; +reg [23:0] cpu_a; +reg [23:0] cpu_busdata; +reg [23:0] cpu_romdata; +reg [23:0] cpu_ramdata; +reg [23:0] cpu_busaddr; +reg [23:0] cpu_romaddr; +reg [23:0] cpu_ramaddr; +reg [23:0] cpu_acch; +reg [23:0] cpu_accl; +reg [23:0] cpu_mul_src; + +reg [23:0] cpu_sa; // tmp register for shifted accumulator +reg fl_n; +reg fl_z; +reg fl_c; +reg [15:0] cpu_p; + +reg [9:0] cx4_datrom_addr; +wire [23:0] cx4_datrom_do; +wire [7:0] cx4_datram_do; + +parameter ST_CPU_IDLE = 8'b00000001; +parameter ST_CPU_0 = 8'b00000010; +parameter ST_CPU_1 = 8'b00000100; +parameter ST_CPU_2 = 8'b00001000; +parameter ST_CPU_3 = 8'b00010000; + +initial CPU_STATE <= ST_CPU_IDLE; + +parameter OP_ALU = 4'b0000; +parameter OP_LD = 4'b0001; +parameter OP_ST = 4'b0010; +parameter OP_JP = 4'b0011; +parameter OP_SWP = 4'b0100; +parameter OP_HLT = 4'b0101; +parameter OP_BUS = 4'b0110; +parameter OP_STA = 4'b0111; +parameter OP_NOP = 4'b1111; + + +wire [6:0] op_id = cpu_op_w[15:10]; +reg [7:0] op_param; +reg [2:0] op; +reg [1:0] op_sa; +reg op_imm; +reg op_p; +reg op_call; +reg op_jump; +reg cond_true; +reg cpu_go_rq; +reg cpu_bus_rq; + +always @(posedge CLK) begin + case(CPU_STATE) + ST_CPU_IDLE: begin + if(cpu_go_rq) begin + cpu_pc <= cx4_mmio_pc; + op <= OP_NOP; + CPU_STATE <= ST_CPU_2; + end + else CPU_STATE <= ST_CPU_IDLE; + end + ST_CPU_0: begin // Phase 0: + CPU_STATE <= ST_CPU_1; + case(op) + OP_ALU, OP_LD, OP_SWP: begin + if(cpu_op[15:10] == 6'b111000) cpu_idb <= cpu_a; // reg[imm] <- a + else if(op_imm) cpu_idb <= {16'b0, op_param}; + else casex(op_param) + 8'h00: cpu_idb <= cpu_a; + 8'h01: cpu_idb <= cpu_acch; + 8'h02: cpu_idb <= cpu_accl; + 8'h03: cpu_idb <= cpu_busdata; + 8'h08: cpu_idb <= cpu_romdata; + 8'h0c: cpu_idb <= cpu_ramdata; + 8'h13: cpu_idb <= cpu_busaddr; + 8'h1c: cpu_idb <= cpu_ramaddr; + 8'h5x: cpu_idb <= const[op_param[3:0]]; + 8'h6x: cpu_idb <= {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]}; + default: cpu_idb <= 24'b0; + endcase + if(op==OP_ALU) begin + case(op_sa) + 2'b00: cpu_sa <= cpu_a; + 2'b01: cpu_sa <= cpu_a << 1; + 2'b10: cpu_sa <= cpu_a << 8; + 2'b11: cpu_sa <= cpu_a << 16; + endcase + end + end + OP_JP: begin + casex(cpu_op[12:8]) + 5'b010xx: cond_true <= 1'b1; + 5'b011xx: cond_true <= fl_z; + 5'b100xx: cond_true <= fl_c; + 5'b101xx: cond_true <= fl_n; + 5'b00101: cond_true <= (fl_c == cpu_op[0]); + 5'b00110: cond_true <= (fl_z == cpu_op[0]); + 5'b00111: cond_true <= (fl_n == cpu_op[0]); + default: cond_true <= 1'b1; + endcase + end + OP_BUS: cpu_bus_rq <= 1'b1; + endcase + end + ST_CPU_1: begin + CPU_STATE <= ST_CPU_2; + case(op) + OP_LD: begin + cx4_datram_addr <= op_imm ? op_param : (cpu_ramaddr + cpu_idb); + cx4_datrom_addr <= cpu_a[9:0]; + end + OP_ST: begin + cx4_datram_addr <= op_imm ? op_param : (cpu_ramaddr + cpu_idb); + cx4_datram_we <= 1'b1; + end + OP_JP: begin + if(cond_true) begin + casex(cpu_op[12:11]) + 2'b01, 2'b10: begin + // TODO if(op_p) + if(op_call) begin + cpu_stack[cpu_sp] <= {cpu_page, cpu_pc+1}; + cpu_sp <= cpu_sp - 1; + end + cpu_pc <= op_param; + end + 2'b00: begin + cpu_pc <= cpu_pc + 2; + end + 2'b11: begin + if(cpu_op[13]) begin + {cpu_page, cpu_pc} <= cpu_stack[cpu_sp+1]; + cpu_sp <= cpu_sp + 1; + end else begin + if(BUS_RDY) cpu_pc <= cpu_pc + 1; + end + end + default: cpu_pc <= cpu_pc + 1; + endcase + end + end + OP_BUS: cpu_bus_rq <= 1'b0; + endcase + end + ST_CPU_2: begin + CPU_STATE <= ST_CPU_3; + case(op) + OP_ST: begin + cx4_datram_we <= 1'b0; + end + endcase + end + ST_CPU_3: begin + CPU_STATE <= ST_CPU_0; + case(op) + OP_LD, OP_SWP: begin + casex(cpu_op[15:8]) + 8'b01100x00: cpu_a <= cpu_idb; + 8'b01100x11: cpu_p <= cpu_idb; + 8'b01111100: cpu_p[7:0] <= op_param; + 8'b01111101: cpu_p[15:8] <= op_param; + 8'b01110000: cpu_romdata <= cx4_datrom_do; + 8'b01101x00: cpu_ramdata[7:0] <= cx4_datram_do; + 8'b01101x01: cpu_ramdata[15:8] <= cx4_datram_do; + 8'b01101x10: cpu_ramdata[23:16] <= cx4_datram_do; + 8'b11110000, 8'b11100000: begin + if(cpu_op[12]) cpu_a <= cpu_idb; + casex(op_param) + 8'h00: cpu_a <= cpu_a; + 8'h01: cpu_acch <= cpu_a; + 8'h02: cpu_accl <= cpu_a; + 8'h03: cpu_busdata <= cpu_a; + 8'h08: cpu_romdata <= cpu_a; + 8'h0c: cpu_ramdata <= cpu_a; + 8'h13: cpu_busaddr <= cpu_a; + 8'h1c: cpu_ramaddr <= cpu_a; + 8'h6x: {gpr[op_param[3:0]*3+2], + gpr[op_param[3:0]*3+1], + gpr[op_param[3:0]*3]} <= cpu_a; + endcase + end + endcase + end + endcase + cpu_op <= cpu_op_w; + op_param <= cpu_op_w[7:0]; + op <= &(op_id) ? OP_HLT + :(op_id[5:4] == 2'b00) ? OP_JP + :(op_id[5:2] == 4'b0110 + || op_id[5:2] == 4'b0111 + ) ? OP_LD + :(op_id[5:1] == 5'b11101) ? OP_ST + :(op_id[5:1] == 5'b01000) ? OP_BUS + :(op_id[5:3] == 3'b010 + || op_id[5:3] == 3'b100 + || op_id[5:3] == 3'b101 + || op_id[5:3] == 3'b110) ? OP_ALU + : (op_id == 6'b111100 || op_id == 6'b111000) ? OP_SWP + : OP_NOP; + op_imm <= cpu_op_w[10]; + op_sa <= cpu_op_w[9:8]; + op_p <= cpu_op_w[9]; + op_call <= cpu_op_w[13]; + cond_true <= 1'b0; + end + endcase +end + + +/*************************** + =========== MEM =========== + ***************************/ +cx4_datrom cx4_datrom ( + .clka(CLK), // input clka + .wea(DATROM_WE), // input [0 : 0] wea + .addra(DATROM_ADDR), // input [9 : 0] addra + .dina(DATROM_DI), // input [23 : 0] dina + .clkb(CLK), // input clkb + .addrb(cx4_datrom_addr), // input [9 : 0] addrb + .doutb(cx4_datrom_do) // output [23 : 0] doutb +); + +cx4_datram cx4_datram ( + .clka(CLK), // input clka + .wea(DATRAM_WR_EN), // input [0 : 0] wea + .addra(ADDR[11:0]), // input [11 : 0] addra + .dina(DI), // input [7 : 0] dina + .douta(DATRAM_DO), // output [7 : 0] douta + .clkb(CLK), // input clkb + .web(cx4_datram_we), // input [0 : 0] web + .addrb(cx4_datram_addr), // input [11 : 0] addrb + .dinb(BUS_DI), // input [7 : 0] dinb + .doutb(cx4_datram_do) // output [7 : 0] doutb +); + +cx4_pgmrom cx4_pgmrom ( + .clka(CLK), // input clka + .wea(cx4_pgmrom_we), // input [0 : 0] wea + .addra(cx4_pgmrom_addr), // input [9 : 0] addra + .dina(BUS_DI), // input [7 : 0] dina + .clkb(CLK), // input clkb + .addrb(cpu_pc), // input [8 : 0] addrb + .doutb(cpu_op_w) // output [15 : 0] doutb +); + +cx4_mul cx4_mul ( + .clk(CLK), // input clk + .a(cpu_a), // input [23 : 0] a + .b(cpu_mul_src), // input [23 : 0] b + .p(cpu_mul_result) // output [47 : 0] p +); +endmodule diff --git a/verilog/sd2snes_cx4/dac.v b/verilog/sd2snes_cx4/dac.v new file mode 100644 index 0000000..6eca076 --- /dev/null +++ b/verilog/sd2snes_cx4/dac.v @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:26:11 07/23/2010 +// Design Name: +// Module Name: dac_test +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dac( + input clkin, + input sysclk, + input we, + input[10:0] pgm_address, + input[7:0] pgm_data, + input[7:0] volume, + input vol_latch, + input play, + input reset, + output sdout, + output lrck, + output mclk, + output DAC_STATUS +); + +reg[8:0] dac_address_r; +wire[8:0] dac_address = dac_address_r; + +wire[31:0] dac_data; +assign DAC_STATUS = dac_address_r[8]; +reg[7:0] vol_reg; +reg[7:0] vol_target_reg; +reg[1:0] vol_latch_reg; +reg vol_valid; +reg[2:0] sysclk_sreg; +wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01); + +reg [25:0] interpol_count; + +always @(posedge clkin) begin + sysclk_sreg <= {sysclk_sreg[1:0], sysclk}; +end + +dac_buf snes_dac_buf ( + .clka(clkin), + .wea(~we), // Bus [0 : 0] + .addra(pgm_address), // Bus [10 : 0] + .dina(pgm_data), // Bus [7 : 0] + .clkb(clkin), + .addrb(dac_address), // Bus [8 : 0] + .doutb(dac_data)); // Bus [31 : 0] + +reg [8:0] cnt; +reg [15:0] smpcnt; +reg [1:0] samples; +reg [15:0] smpshift; + +assign mclk = cnt[2]; // mclk = clk/8 +assign lrck = cnt[8]; // lrck = mclk/128 +wire sclk = cnt[3]; // sclk = lrck*32 + +reg [2:0] lrck_sreg; +reg [2:0] sclk_sreg; +wire lrck_rising = ({lrck_sreg[2:1]} == 2'b01); +wire lrck_falling = ({lrck_sreg[2:1]} == 2'b10); + +wire sclk_rising = ({sclk_sreg[2:1]} == 2'b01); + +wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01); +reg sdout_reg; +assign sdout = sdout_reg; + +reg [1:0] reset_sreg; +wire reset_rising = (reset_sreg[1:0] == 2'b01); + +reg play_r; + +initial begin + cnt = 9'h100; + smpcnt = 16'b0; + lrck_sreg = 2'b11; + sclk_sreg = 1'b0; + dac_address_r = 10'b0; + vol_valid = 1'b0; + vol_latch_reg = 1'b0; + vol_reg = 8'h0; + vol_target_reg = 8'hff; + samples <= 2'b00; +end + +always @(posedge clkin) begin + if(reset_rising) begin + dac_address_r <= 0; + interpol_count <= 0; + end else if(sysclk_rising) begin + if(interpol_count > 59378938) begin + interpol_count <= interpol_count + 122500 - 59501439; + dac_address_r <= dac_address_r + play_r; + end else begin + interpol_count <= interpol_count + 122500; + end + end +end + +always @(posedge clkin) begin + cnt <= cnt + 1; + lrck_sreg <= {lrck_sreg[1:0], lrck}; + sclk_sreg <= {sclk_sreg[1:0], sclk}; + vol_latch_reg <= {vol_latch_reg[0], vol_latch}; + play_r <= play; + reset_sreg <= {reset_sreg[0], reset}; +end + +always @(posedge clkin) begin + if (vol_latch_rising) begin + vol_valid <= 1'b1; + end + else if(vol_valid) begin + vol_target_reg <= volume; + vol_valid <= 1'b0; + end +end + +// ramp volume only every 4 samples +always @(posedge clkin) begin + if (lrck_rising && &samples[1:0]) begin + if(vol_reg > vol_target_reg) + vol_reg <= vol_reg - 1; + else if(vol_reg < vol_target_reg) + vol_reg <= vol_reg + 1; + end +end + +always @(posedge clkin) begin + if (lrck_rising) begin // right channel + smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000; + samples <= samples + 1; + end else if (lrck_falling) begin // left channel + smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000; + end else begin + if (sclk_rising) begin + smpcnt <= smpcnt + 1; + sdout_reg <= smpshift[15]; + smpshift <= {smpshift[14:0], 1'b0}; + end + end +end + +endmodule diff --git a/verilog/sd2snes_cx4/dcm.v b/verilog/sd2snes_cx4/dcm.v new file mode 100644 index 0000000..90b516e --- /dev/null +++ b/verilog/sd2snes_cx4/dcm.v @@ -0,0 +1,72 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:06:52 06/28/2009 +// Design Name: +// Module Name: dcm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module my_dcm ( + input CLKIN, + output CLKFX, + output LOCKED, + input RST, + output[7:0] STATUS + ); + + // DCM: Digital Clock Manager Circuit + // Spartan-3 + // Xilinx HDL Language Template, version 11.1 + + DCM #( + .SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details + .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 + // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 + .CLKFX_DIVIDE(1), // Can be any integer from 1 to 32 + .CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32 + .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature + .CLKIN_PERIOD(41.667), // Specify period of input clock + .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE + .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or + // an integer from 0 to 15 + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .FACTORY_JF(16'hFFFF), // FACTORY JF values +// .LOC("DCM_X0Y0"), + .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255 + .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE + ) DCM_inst ( + .CLK0(CLK0), // 0 degree DCM CLK output + .CLK180(CLK180), // 180 degree DCM CLK output + .CLK270(CLK270), // 270 degree DCM CLK output + .CLK2X(CLK2X), // 2X DCM CLK output + .CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out + .CLK90(CLK90), // 90 degree DCM CLK output + .CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE) + .CLKFX(CLKFX), // DCM CLK synthesis out (M/D) + .CLKFX180(CLKFX180), // 180 degree CLK synthesis out + .LOCKED(LOCKED), // DCM LOCK status output + .PSDONE(PSDONE), // Dynamic phase adjust done output + .STATUS(STATUS), // 8-bit DCM status bits output + .CLKFB(CLKFB), // DCM clock feedback + .CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM) + .PSCLK(PSCLK), // Dynamic phase adjust clock input + .PSEN(PSEN), // Dynamic phase adjust enable input + .PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement + .RST(RST) // DCM asynchronous reset input + ); +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v new file mode 100644 index 0000000..329617f --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.v @@ -0,0 +1,187 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file cx4_datram.v when simulating +// the core, cx4_datram. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module cx4_datram( + clka, + wea, + addra, + dina, + douta, + clkb, + web, + addrb, + dinb, + doutb +); + +input clka; +input [0 : 0] wea; +input [11 : 0] addra; +input [7 : 0] dina; +output [7 : 0] douta; +input clkb; +input [0 : 0] web; +input [11 : 0] addrb; +input [7 : 0] dinb; +output [7 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_2 #( + .C_ADDRA_WIDTH(12), + .C_ADDRB_WIDTH(12), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("77"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(2), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(3072), + .C_READ_DEPTH_B(3072), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(8), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(1), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(3072), + .C_WRITE_DEPTH_B(3072), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(8), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .DOUTA(douta), + .CLKB(clkb), + .WEB(web), + .ADDRB(addrb), + .DINB(dinb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .RSTB(), + .ENB(), + .REGCEB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco new file mode 100644 index 0000000..a793578 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Sun Oct 16 18:54:12 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=cx4_datram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=true +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=True_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=50 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=77 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=3072 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: a7d60fbd diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise new file mode 100644 index 0000000..511d066 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datram.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v new file mode 100644 index 0000000..3825bab --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file cx4_datrom.v when simulating +// the core, cx4_datrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module cx4_datrom( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [9 : 0] addra; +input [23 : 0] dina; +input clkb; +input [9 : 0] addrb; +output [23 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_2 #( + .C_ADDRA_WIDTH(10), + .C_ADDRB_WIDTH(10), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(1024), + .C_READ_DEPTH_B(1024), + .C_READ_WIDTH_A(24), + .C_READ_WIDTH_B(24), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(1024), + .C_WRITE_DEPTH_B(1024), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(24), + .C_WRITE_WIDTH_B(24), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco new file mode 100644 index 0000000..83d9d34 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Sun Oct 16 12:57:23 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=cx4_datrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=24 +CSET read_width_b=24 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=1024 +CSET write_width_a=24 +CSET write_width_b=24 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: a25bf9a3 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise new file mode 100644 index 0000000..ded48b2 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_datrom.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v new file mode 100644 index 0000000..32e9bad --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.v @@ -0,0 +1,2511 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: O.61xd +// \ \ Application: netgen +// / / Filename: cx4_mul.v +// /___/ /\ Timestamp: Fri Oct 21 22:38:27 2011 +// \ \ / \ +// \___\/\___\ +// +// Command : -w -sim -ofmt verilog /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.ngc /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.v +// Device : 3s400pq208-4 +// Input file : /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.ngc +// Output file : /home/ikari/prj/sd2snes/verilog/sd2snes_cx4/ipcore_dir/tmp/_cg/cx4_mul.v +// # of Modules : 1 +// Design Name : cx4_mul +// Xilinx : /mnt/store/bin/Xilinx/13.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module cx4_mul ( + clk, p, a, b +)/* synthesis syn_black_box syn_noprune=1 */; + input clk; + output [47 : 0] p; + input [23 : 0] a; + input [23 : 0] b; + + // synthesis translate_off + + wire sig00000001; + wire sig00000002; + wire sig00000003; + wire sig00000004; + wire sig00000005; + wire sig00000006; + wire sig00000007; + wire sig00000008; + wire sig00000009; + wire sig0000000a; + wire sig0000000b; + wire sig0000000c; + wire sig0000000d; + wire sig0000000e; + wire sig0000000f; + wire sig00000010; + wire sig00000011; + wire sig00000012; + wire sig00000013; + wire sig00000014; + wire sig00000015; + wire sig00000016; + wire sig00000017; + wire sig00000018; + wire sig00000019; + wire sig0000001a; + wire sig0000001b; + wire sig0000001c; + wire sig0000001d; + wire sig0000001e; + wire sig0000001f; + wire sig00000020; + wire sig00000021; + wire sig00000022; + wire sig00000023; + wire sig00000024; + wire sig00000025; + wire sig00000026; + wire sig00000027; + wire sig00000028; + wire sig00000029; + wire sig0000002a; + wire sig0000002b; + wire sig0000002c; + wire sig0000002d; + wire sig0000002e; + wire sig0000002f; + wire sig00000030; + wire sig00000031; + wire sig00000032; + wire sig00000033; + wire sig00000034; + wire sig00000035; + wire sig00000036; + wire sig00000037; + wire sig00000038; + wire sig00000039; + wire sig0000003a; + wire sig0000003b; + wire sig0000003c; + wire sig0000003d; + wire sig0000003e; + wire sig0000003f; + wire sig00000040; + wire sig00000041; + wire sig00000042; + wire sig00000043; + wire sig00000044; + wire sig00000045; + wire sig00000046; + wire sig00000047; + wire sig00000048; + wire sig00000049; + wire sig0000004a; + wire sig0000004b; + wire sig0000004c; + wire sig0000004d; + wire sig0000004e; + wire sig0000004f; + wire sig00000050; + wire sig00000051; + wire sig00000052; + wire sig00000053; + wire sig00000054; + wire sig00000055; + wire sig00000056; + wire sig00000057; + wire sig00000058; + wire sig00000059; + wire sig0000005a; + wire sig0000005b; + wire sig0000005c; + wire sig0000005d; + wire sig0000005e; + wire sig0000005f; + wire sig00000060; + wire sig00000061; + wire sig00000062; + wire sig00000063; + wire sig00000064; + wire sig00000065; + wire sig00000066; + wire sig00000067; + wire sig00000068; + wire sig00000069; + wire sig0000006a; + wire sig0000006b; + wire sig0000006c; + wire sig0000006d; + wire sig0000006e; + wire sig0000006f; + wire sig00000070; + wire sig00000071; + wire sig00000072; + wire sig00000073; + wire sig00000074; + wire sig00000075; + wire sig00000076; + wire sig00000077; + wire sig00000078; + wire sig00000079; + wire sig0000007a; + wire sig0000007b; + wire sig0000007c; + wire sig0000007d; + wire sig0000007e; + wire sig0000007f; + wire sig00000080; + wire sig00000081; + wire sig00000082; + wire sig00000083; + wire sig00000084; + wire sig00000085; + wire sig00000086; + wire sig00000087; + wire sig00000088; + wire sig00000089; + wire sig0000008a; + wire sig0000008b; + wire sig0000008c; + wire sig0000008d; + wire sig0000008e; + wire sig0000008f; + wire sig00000090; + wire sig00000091; + wire sig00000092; + wire sig00000093; + wire sig00000094; + wire sig00000095; + wire sig00000096; + wire sig00000097; + wire sig00000098; + wire sig00000099; + wire sig0000009a; + wire sig0000009b; + wire sig0000009c; + wire sig0000009d; + wire sig0000009e; + wire sig0000009f; + wire sig000000a0; + wire sig000000a1; + wire sig000000a2; + wire sig000000a3; + wire sig000000a4; + wire sig000000a5; + wire sig000000a6; + wire sig000000a7; + wire sig000000a8; + wire sig000000a9; + wire sig000000aa; + wire sig000000ab; + wire sig000000ac; + wire sig000000ad; + wire sig000000ae; + wire sig000000af; + wire sig000000b0; + wire sig000000b1; + wire sig000000b2; + wire sig000000b3; + wire sig000000b4; + wire sig000000b5; + wire sig000000b6; + wire sig000000b7; + wire sig000000b8; + wire sig000000b9; + wire sig000000ba; + wire sig000000bb; + wire sig000000bc; + wire sig000000bd; + wire sig000000be; + wire sig000000bf; + wire sig000000c0; + wire sig000000c1; + wire sig000000c2; + wire sig000000c3; + wire sig000000c4; + wire sig000000c5; + wire sig000000c6; + wire sig000000c7; + wire sig000000c8; + wire sig000000c9; + wire sig000000ca; + wire sig000000cb; + wire sig000000cc; + wire sig000000cd; + wire sig000000ce; + wire sig000000cf; + wire sig000000d0; + wire sig000000d1; + wire sig000000d2; + wire sig000000d3; + wire sig000000d4; + wire sig000000d5; + wire sig000000d6; + wire sig000000d7; + wire sig000000d8; + wire sig000000d9; + wire sig000000da; + wire sig000000db; + wire sig000000dc; + wire sig000000dd; + wire sig000000de; + wire sig000000df; + wire sig000000e0; + wire sig000000e1; + wire sig000000e2; + wire sig000000e3; + wire sig000000e4; + wire sig000000e5; + wire sig000000e6; + wire sig000000e7; + wire sig000000e8; + wire sig000000e9; + wire sig000000ea; + wire sig000000eb; + wire sig000000ec; + wire sig000000ed; + wire sig000000ee; + wire sig000000ef; + wire sig000000f0; + wire sig000000f1; + wire sig000000f2; + wire sig000000f3; + wire sig000000f4; + wire sig000000f5; + wire sig000000f6; + wire sig000000f7; + wire sig000000f8; + wire sig000000f9; + wire sig000000fa; + wire sig000000fb; + wire sig000000fc; + wire sig000000fd; + wire sig000000fe; + wire sig000000ff; + wire sig00000100; + wire sig00000101; + wire sig00000102; + wire sig00000103; + wire sig00000104; + wire sig00000105; + wire sig00000106; + wire sig00000107; + wire sig00000108; + wire sig00000109; + wire sig0000010a; + wire sig0000010b; + wire sig0000010c; + wire sig0000010d; + wire sig0000010e; + wire sig0000010f; + wire sig00000110; + wire sig00000111; + wire sig00000112; + wire sig00000113; + wire sig00000114; + wire sig00000115; + wire sig00000116; + wire sig00000117; + wire sig00000118; + wire sig00000119; + wire sig0000011a; + wire sig0000011b; + wire sig0000011c; + wire sig0000011d; + wire sig0000011e; + wire sig0000011f; + wire sig00000120; + wire sig00000121; + wire sig00000122; + wire sig00000123; + wire sig00000124; + wire sig00000125; + wire sig00000126; + wire sig00000127; + wire sig00000128; + wire sig00000129; + wire sig0000012a; + wire sig0000012b; + wire sig0000012c; + wire sig0000012d; + wire sig0000012e; + wire sig0000012f; + wire sig00000130; + wire sig00000131; + wire sig00000132; + wire sig00000133; + wire sig00000134; + wire sig00000135; + wire sig00000136; + wire sig00000137; + wire sig00000138; + wire sig00000139; + wire sig0000013a; + wire sig0000013b; + wire sig0000013c; + wire sig0000013d; + wire sig0000013e; + wire sig0000013f; + wire sig00000140; + wire sig00000141; + wire sig00000142; + wire sig00000143; + wire sig00000144; + wire sig00000145; + wire sig00000146; + wire sig00000147; + wire sig00000148; + wire sig00000149; + wire sig0000014a; + wire sig0000014b; + wire sig0000014c; + wire sig0000014d; + wire sig0000014e; + wire sig0000014f; + wire sig00000150; + wire sig00000151; + wire sig00000152; + wire sig00000153; + wire sig00000154; + wire sig00000155; + wire sig00000156; + wire sig00000157; + wire sig00000158; + wire sig00000159; + wire sig0000015a; + wire sig0000015b; + wire sig0000015c; + wire sig0000015d; + wire sig0000015e; + wire sig0000015f; + wire sig00000160; + wire sig00000161; + wire sig00000162; + wire sig00000163; + wire sig00000164; + wire \NLW_blk00000003_P<35>_UNCONNECTED ; + wire \NLW_blk00000003_P<34>_UNCONNECTED ; + wire \NLW_blk00000003_P<33>_UNCONNECTED ; + wire \NLW_blk00000003_P<32>_UNCONNECTED ; + wire \NLW_blk00000003_P<31>_UNCONNECTED ; + wire \NLW_blk00000003_P<30>_UNCONNECTED ; + wire \NLW_blk00000003_P<29>_UNCONNECTED ; + wire \NLW_blk00000003_P<28>_UNCONNECTED ; + wire \NLW_blk00000003_P<27>_UNCONNECTED ; + wire \NLW_blk00000003_P<26>_UNCONNECTED ; + wire \NLW_blk00000003_P<25>_UNCONNECTED ; + wire \NLW_blk00000003_P<24>_UNCONNECTED ; + wire \NLW_blk00000003_P<23>_UNCONNECTED ; + wire \NLW_blk00000003_P<22>_UNCONNECTED ; + wire \NLW_blk00000003_P<21>_UNCONNECTED ; + wire \NLW_blk00000003_P<20>_UNCONNECTED ; + wire \NLW_blk00000003_P<19>_UNCONNECTED ; + wire \NLW_blk00000003_P<18>_UNCONNECTED ; + wire \NLW_blk00000003_P<17>_UNCONNECTED ; + wire \NLW_blk00000003_P<16>_UNCONNECTED ; + wire \NLW_blk00000003_P<15>_UNCONNECTED ; + wire \NLW_blk00000003_P<14>_UNCONNECTED ; + wire \NLW_blk00000004_P<35>_UNCONNECTED ; + wire \NLW_blk00000004_P<34>_UNCONNECTED ; + wire \NLW_blk00000004_P<33>_UNCONNECTED ; + wire \NLW_blk00000004_P<32>_UNCONNECTED ; + wire \NLW_blk00000004_P<31>_UNCONNECTED ; + wire \NLW_blk00000004_P<30>_UNCONNECTED ; + wire \NLW_blk00000004_P<29>_UNCONNECTED ; + wire \NLW_blk00000004_P<28>_UNCONNECTED ; + wire \NLW_blk00000004_P<27>_UNCONNECTED ; + wire \NLW_blk00000004_P<26>_UNCONNECTED ; + wire \NLW_blk00000004_P<25>_UNCONNECTED ; + wire \NLW_blk00000004_P<24>_UNCONNECTED ; + wire \NLW_blk00000005_P<35>_UNCONNECTED ; + wire \NLW_blk00000005_P<34>_UNCONNECTED ; + wire \NLW_blk00000005_P<33>_UNCONNECTED ; + wire \NLW_blk00000005_P<32>_UNCONNECTED ; + wire \NLW_blk00000005_P<31>_UNCONNECTED ; + wire \NLW_blk00000005_P<30>_UNCONNECTED ; + wire \NLW_blk00000005_P<29>_UNCONNECTED ; + wire \NLW_blk00000005_P<28>_UNCONNECTED ; + wire \NLW_blk00000005_P<27>_UNCONNECTED ; + wire \NLW_blk00000005_P<26>_UNCONNECTED ; + wire \NLW_blk00000005_P<25>_UNCONNECTED ; + wire \NLW_blk00000005_P<24>_UNCONNECTED ; + wire \NLW_blk00000006_P<35>_UNCONNECTED ; + GND blk00000001 ( + .G(sig00000001) + ); + VCC blk00000002 ( + .P(sig00000002) + ); + MULT18X18S blk00000003 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), + .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), + .P({\NLW_blk00000003_P<35>_UNCONNECTED , \NLW_blk00000003_P<34>_UNCONNECTED , \NLW_blk00000003_P<33>_UNCONNECTED , +\NLW_blk00000003_P<32>_UNCONNECTED , \NLW_blk00000003_P<31>_UNCONNECTED , \NLW_blk00000003_P<30>_UNCONNECTED , \NLW_blk00000003_P<29>_UNCONNECTED , +\NLW_blk00000003_P<28>_UNCONNECTED , \NLW_blk00000003_P<27>_UNCONNECTED , \NLW_blk00000003_P<26>_UNCONNECTED , \NLW_blk00000003_P<25>_UNCONNECTED , +\NLW_blk00000003_P<24>_UNCONNECTED , \NLW_blk00000003_P<23>_UNCONNECTED , \NLW_blk00000003_P<22>_UNCONNECTED , \NLW_blk00000003_P<21>_UNCONNECTED , +\NLW_blk00000003_P<20>_UNCONNECTED , \NLW_blk00000003_P<19>_UNCONNECTED , \NLW_blk00000003_P<18>_UNCONNECTED , \NLW_blk00000003_P<17>_UNCONNECTED , +\NLW_blk00000003_P<16>_UNCONNECTED , \NLW_blk00000003_P<15>_UNCONNECTED , \NLW_blk00000003_P<14>_UNCONNECTED , sig000000e5, sig000000e4, sig000000e3, +sig000000e2, sig000000ee, sig000000ed, sig000000ec, sig000000eb, sig000000ea, sig000000e9, sig000000e8, sig000000e7, sig000000e6, sig000000e1}) + ); + MULT18X18S blk00000004 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .P({\NLW_blk00000004_P<35>_UNCONNECTED , \NLW_blk00000004_P<34>_UNCONNECTED , \NLW_blk00000004_P<33>_UNCONNECTED , +\NLW_blk00000004_P<32>_UNCONNECTED , \NLW_blk00000004_P<31>_UNCONNECTED , \NLW_blk00000004_P<30>_UNCONNECTED , \NLW_blk00000004_P<29>_UNCONNECTED , +\NLW_blk00000004_P<28>_UNCONNECTED , \NLW_blk00000004_P<27>_UNCONNECTED , \NLW_blk00000004_P<26>_UNCONNECTED , \NLW_blk00000004_P<25>_UNCONNECTED , +\NLW_blk00000004_P<24>_UNCONNECTED , sig000000d8, sig000000d7, sig000000d6, sig000000d5, sig000000d3, sig000000d2, sig000000d1, sig000000d0, +sig000000cf, sig000000ce, sig000000cd, sig000000cc, sig000000cb, sig000000ca, sig000000e0, sig000000df, sig000000de, sig000000dd, sig000000dc, +sig000000db, sig000000da, sig000000d9, sig000000d4, sig000000c9}) + ); + MULT18X18S blk00000005 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}), + .P({\NLW_blk00000005_P<35>_UNCONNECTED , \NLW_blk00000005_P<34>_UNCONNECTED , \NLW_blk00000005_P<33>_UNCONNECTED , +\NLW_blk00000005_P<32>_UNCONNECTED , \NLW_blk00000005_P<31>_UNCONNECTED , \NLW_blk00000005_P<30>_UNCONNECTED , \NLW_blk00000005_P<29>_UNCONNECTED , +\NLW_blk00000005_P<28>_UNCONNECTED , \NLW_blk00000005_P<27>_UNCONNECTED , \NLW_blk00000005_P<26>_UNCONNECTED , \NLW_blk00000005_P<25>_UNCONNECTED , +\NLW_blk00000005_P<24>_UNCONNECTED , sig000000c0, sig000000bf, sig000000be, sig000000bd, sig000000bb, sig000000ba, sig000000b9, sig000000b8, +sig000000b7, sig000000b6, sig000000b5, sig000000b4, sig000000b3, sig000000b2, sig000000c8, sig000000c7, sig000000c6, sig000000c5, sig000000c4, +sig000000c3, sig000000c2, sig000000c1, sig000000bc, sig000000b1}) + ); + MULT18X18S blk00000006 ( + .C(clk), + .CE(sig00000002), + .R(sig00000001), + .A({sig00000001, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}), + .B({sig00000001, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}), + .P({\NLW_blk00000006_P<35>_UNCONNECTED , sig000000a9, sig000000a8, sig000000a7, sig000000a6, sig000000a5, sig000000a3, sig000000a2, sig000000a1, +sig000000a0, sig0000009f, sig0000009e, sig0000009d, sig0000009c, sig0000009b, sig0000009a, sig00000098, sig00000097, sig00000096, sig00000095, +sig00000094, sig00000093, sig00000092, sig00000091, sig00000090, sig0000008f, sig000000b0, sig000000af, sig000000ae, sig000000ad, sig000000ac, +sig000000ab, sig000000aa, sig000000a4, sig00000099, sig0000008e}) + ); + XORCY blk00000007 ( + .CI(sig00000065), + .LI(sig00000086), + .O(p[47]) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000008 ( + .I0(sig0000014e), + .I1(sig0000015b), + .O(sig00000086) + ); + MUXCY blk00000009 ( + .CI(sig00000064), + .DI(sig0000014e), + .S(sig00000085), + .O(sig00000065) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000a ( + .I0(sig0000014e), + .I1(sig0000015b), + .O(sig00000085) + ); + MUXCY blk0000000b ( + .CI(sig00000062), + .DI(sig0000014e), + .S(sig00000084), + .O(sig00000064) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000c ( + .I0(sig0000014e), + .I1(sig0000015b), + .O(sig00000084) + ); + XORCY blk0000000d ( + .CI(sig00000061), + .LI(sig00000082), + .O(p[46]) + ); + MUXCY blk0000000e ( + .CI(sig00000061), + .DI(sig0000014e), + .S(sig00000082), + .O(sig00000062) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000000f ( + .I0(sig0000014e), + .I1(sig0000015a), + .O(sig00000082) + ); + XORCY blk00000010 ( + .CI(sig00000060), + .LI(sig00000081), + .O(p[45]) + ); + MUXCY blk00000011 ( + .CI(sig00000060), + .DI(sig0000014e), + .S(sig00000081), + .O(sig00000061) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000012 ( + .I0(sig0000014e), + .I1(sig00000159), + .O(sig00000081) + ); + XORCY blk00000013 ( + .CI(sig0000005f), + .LI(sig00000080), + .O(p[44]) + ); + MUXCY blk00000014 ( + .CI(sig0000005f), + .DI(sig0000014e), + .S(sig00000080), + .O(sig00000060) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000015 ( + .I0(sig0000014e), + .I1(sig00000158), + .O(sig00000080) + ); + XORCY blk00000016 ( + .CI(sig0000005e), + .LI(sig0000007f), + .O(p[43]) + ); + MUXCY blk00000017 ( + .CI(sig0000005e), + .DI(sig0000014e), + .S(sig0000007f), + .O(sig0000005f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000018 ( + .I0(sig0000014e), + .I1(sig00000164), + .O(sig0000007f) + ); + XORCY blk00000019 ( + .CI(sig0000005d), + .LI(sig0000007e), + .O(p[42]) + ); + MUXCY blk0000001a ( + .CI(sig0000005d), + .DI(sig0000014e), + .S(sig0000007e), + .O(sig0000005e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000001b ( + .I0(sig0000014e), + .I1(sig00000163), + .O(sig0000007e) + ); + XORCY blk0000001c ( + .CI(sig0000005c), + .LI(sig0000007d), + .O(p[41]) + ); + MUXCY blk0000001d ( + .CI(sig0000005c), + .DI(sig0000014e), + .S(sig0000007d), + .O(sig0000005d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000001e ( + .I0(sig0000014e), + .I1(sig00000162), + .O(sig0000007d) + ); + XORCY blk0000001f ( + .CI(sig0000005b), + .LI(sig0000007c), + .O(p[40]) + ); + MUXCY blk00000020 ( + .CI(sig0000005b), + .DI(sig0000014e), + .S(sig0000007c), + .O(sig0000005c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000021 ( + .I0(sig0000014e), + .I1(sig00000161), + .O(sig0000007c) + ); + XORCY blk00000022 ( + .CI(sig0000005a), + .LI(sig0000007b), + .O(p[39]) + ); + MUXCY blk00000023 ( + .CI(sig0000005a), + .DI(sig0000014d), + .S(sig0000007b), + .O(sig0000005b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000024 ( + .I0(sig0000014d), + .I1(sig00000160), + .O(sig0000007b) + ); + XORCY blk00000025 ( + .CI(sig00000059), + .LI(sig0000007a), + .O(p[38]) + ); + MUXCY blk00000026 ( + .CI(sig00000059), + .DI(sig0000014c), + .S(sig0000007a), + .O(sig0000005a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000027 ( + .I0(sig0000014c), + .I1(sig0000015f), + .O(sig0000007a) + ); + XORCY blk00000028 ( + .CI(sig00000057), + .LI(sig00000079), + .O(p[37]) + ); + MUXCY blk00000029 ( + .CI(sig00000057), + .DI(sig0000014b), + .S(sig00000079), + .O(sig00000059) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000002a ( + .I0(sig0000014b), + .I1(sig0000015e), + .O(sig00000079) + ); + XORCY blk0000002b ( + .CI(sig00000056), + .LI(sig00000077), + .O(p[36]) + ); + MUXCY blk0000002c ( + .CI(sig00000056), + .DI(sig00000149), + .S(sig00000077), + .O(sig00000057) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000002d ( + .I0(sig00000149), + .I1(sig0000015d), + .O(sig00000077) + ); + XORCY blk0000002e ( + .CI(sig00000055), + .LI(sig00000076), + .O(p[35]) + ); + MUXCY blk0000002f ( + .CI(sig00000055), + .DI(sig00000148), + .S(sig00000076), + .O(sig00000056) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000030 ( + .I0(sig00000148), + .I1(sig0000015c), + .O(sig00000076) + ); + XORCY blk00000031 ( + .CI(sig00000054), + .LI(sig00000075), + .O(p[34]) + ); + MUXCY blk00000032 ( + .CI(sig00000054), + .DI(sig00000147), + .S(sig00000075), + .O(sig00000055) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000033 ( + .I0(sig00000147), + .I1(sig00000157), + .O(sig00000075) + ); + XORCY blk00000034 ( + .CI(sig00000053), + .LI(sig00000074), + .O(p[33]) + ); + MUXCY blk00000035 ( + .CI(sig00000053), + .DI(sig00000146), + .S(sig00000074), + .O(sig00000054) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000036 ( + .I0(sig00000146), + .I1(sig00000121), + .O(sig00000074) + ); + XORCY blk00000037 ( + .CI(sig00000052), + .LI(sig00000073), + .O(p[32]) + ); + MUXCY blk00000038 ( + .CI(sig00000052), + .DI(sig00000145), + .S(sig00000073), + .O(sig00000053) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000039 ( + .I0(sig00000145), + .I1(sig00000120), + .O(sig00000073) + ); + XORCY blk0000003a ( + .CI(sig00000051), + .LI(sig00000072), + .O(p[31]) + ); + MUXCY blk0000003b ( + .CI(sig00000051), + .DI(sig00000144), + .S(sig00000072), + .O(sig00000052) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000003c ( + .I0(sig00000144), + .I1(sig0000011f), + .O(sig00000072) + ); + XORCY blk0000003d ( + .CI(sig00000050), + .LI(sig00000071), + .O(p[30]) + ); + MUXCY blk0000003e ( + .CI(sig00000050), + .DI(sig00000143), + .S(sig00000071), + .O(sig00000051) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000003f ( + .I0(sig00000143), + .I1(sig0000011e), + .O(sig00000071) + ); + XORCY blk00000040 ( + .CI(sig0000004f), + .LI(sig00000070), + .O(p[29]) + ); + MUXCY blk00000041 ( + .CI(sig0000004f), + .DI(sig00000142), + .S(sig00000070), + .O(sig00000050) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000042 ( + .I0(sig00000142), + .I1(sig0000011d), + .O(sig00000070) + ); + XORCY blk00000043 ( + .CI(sig0000004e), + .LI(sig0000006f), + .O(p[28]) + ); + MUXCY blk00000044 ( + .CI(sig0000004e), + .DI(sig00000141), + .S(sig0000006f), + .O(sig0000004f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000045 ( + .I0(sig00000141), + .I1(sig0000011c), + .O(sig0000006f) + ); + XORCY blk00000046 ( + .CI(sig0000006c), + .LI(sig0000006e), + .O(p[27]) + ); + MUXCY blk00000047 ( + .CI(sig0000006c), + .DI(sig00000140), + .S(sig0000006e), + .O(sig0000004e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000048 ( + .I0(sig00000140), + .I1(sig0000011b), + .O(sig0000006e) + ); + XORCY blk00000049 ( + .CI(sig0000006b), + .LI(sig0000008d), + .O(p[26]) + ); + MUXCY blk0000004a ( + .CI(sig0000006b), + .DI(sig00000156), + .S(sig0000008d), + .O(sig0000006c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004b ( + .I0(sig00000156), + .I1(sig00000130), + .O(sig0000008d) + ); + XORCY blk0000004c ( + .CI(sig0000006a), + .LI(sig0000008c), + .O(p[25]) + ); + MUXCY blk0000004d ( + .CI(sig0000006a), + .DI(sig00000155), + .S(sig0000008c), + .O(sig0000006b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000004e ( + .I0(sig00000155), + .I1(sig0000012f), + .O(sig0000008c) + ); + XORCY blk0000004f ( + .CI(sig00000069), + .LI(sig0000008b), + .O(p[24]) + ); + MUXCY blk00000050 ( + .CI(sig00000069), + .DI(sig00000154), + .S(sig0000008b), + .O(sig0000006a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000051 ( + .I0(sig00000154), + .I1(sig0000012e), + .O(sig0000008b) + ); + XORCY blk00000052 ( + .CI(sig00000068), + .LI(sig0000008a), + .O(p[23]) + ); + MUXCY blk00000053 ( + .CI(sig00000068), + .DI(sig00000153), + .S(sig0000008a), + .O(sig00000069) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000054 ( + .I0(sig00000153), + .I1(sig0000012d), + .O(sig0000008a) + ); + XORCY blk00000055 ( + .CI(sig00000067), + .LI(sig00000089), + .O(p[22]) + ); + MUXCY blk00000056 ( + .CI(sig00000067), + .DI(sig00000152), + .S(sig00000089), + .O(sig00000068) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000057 ( + .I0(sig00000152), + .I1(sig0000012c), + .O(sig00000089) + ); + XORCY blk00000058 ( + .CI(sig00000066), + .LI(sig00000088), + .O(p[21]) + ); + MUXCY blk00000059 ( + .CI(sig00000066), + .DI(sig00000151), + .S(sig00000088), + .O(sig00000067) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005a ( + .I0(sig00000151), + .I1(sig0000012b), + .O(sig00000088) + ); + XORCY blk0000005b ( + .CI(sig00000063), + .LI(sig00000087), + .O(p[20]) + ); + MUXCY blk0000005c ( + .CI(sig00000063), + .DI(sig00000150), + .S(sig00000087), + .O(sig00000066) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000005d ( + .I0(sig00000150), + .I1(sig0000012a), + .O(sig00000087) + ); + XORCY blk0000005e ( + .CI(sig00000058), + .LI(sig00000083), + .O(p[19]) + ); + MUXCY blk0000005f ( + .CI(sig00000058), + .DI(sig0000014f), + .S(sig00000083), + .O(sig00000063) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000060 ( + .I0(sig0000014f), + .I1(sig00000125), + .O(sig00000083) + ); + XORCY blk00000061 ( + .CI(sig0000004d), + .LI(sig00000078), + .O(p[18]) + ); + MUXCY blk00000062 ( + .CI(sig0000004d), + .DI(sig0000014a), + .S(sig00000078), + .O(sig00000058) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000063 ( + .I0(sig0000014a), + .I1(sig0000011a), + .O(sig00000078) + ); + XORCY blk00000064 ( + .CI(sig00000001), + .LI(sig0000006d), + .O(p[17]) + ); + MUXCY blk00000065 ( + .CI(sig00000001), + .DI(sig0000013f), + .S(sig0000006d), + .O(sig0000004d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000066 ( + .I0(sig0000013f), + .I1(sig00000119), + .O(sig0000006d) + ); + XORCY blk00000067 ( + .CI(sig00000011), + .LI(sig00000029), + .O(sig0000014e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000068 ( + .I0(sig00000100), + .I1(sig00000111), + .O(sig00000029) + ); + XORCY blk00000069 ( + .CI(sig00000010), + .LI(sig00000028), + .O(sig0000014d) + ); + MUXCY blk0000006a ( + .CI(sig00000010), + .DI(sig00000100), + .S(sig00000028), + .O(sig00000011) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000006b ( + .I0(sig00000100), + .I1(sig00000110), + .O(sig00000028) + ); + XORCY blk0000006c ( + .CI(sig0000000f), + .LI(sig00000027), + .O(sig0000014c) + ); + MUXCY blk0000006d ( + .CI(sig0000000f), + .DI(sig00000100), + .S(sig00000027), + .O(sig00000010) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000006e ( + .I0(sig00000100), + .I1(sig0000010f), + .O(sig00000027) + ); + XORCY blk0000006f ( + .CI(sig0000000d), + .LI(sig00000026), + .O(sig0000014b) + ); + MUXCY blk00000070 ( + .CI(sig0000000d), + .DI(sig00000100), + .S(sig00000026), + .O(sig0000000f) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000071 ( + .I0(sig00000100), + .I1(sig0000010e), + .O(sig00000026) + ); + XORCY blk00000072 ( + .CI(sig0000000c), + .LI(sig00000024), + .O(sig00000149) + ); + MUXCY blk00000073 ( + .CI(sig0000000c), + .DI(sig00000100), + .S(sig00000024), + .O(sig0000000d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000074 ( + .I0(sig00000100), + .I1(sig0000010c), + .O(sig00000024) + ); + XORCY blk00000075 ( + .CI(sig0000000b), + .LI(sig00000023), + .O(sig00000148) + ); + MUXCY blk00000076 ( + .CI(sig0000000b), + .DI(sig00000100), + .S(sig00000023), + .O(sig0000000c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000077 ( + .I0(sig00000100), + .I1(sig0000010b), + .O(sig00000023) + ); + XORCY blk00000078 ( + .CI(sig0000000a), + .LI(sig00000022), + .O(sig00000147) + ); + MUXCY blk00000079 ( + .CI(sig0000000a), + .DI(sig00000100), + .S(sig00000022), + .O(sig0000000b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000007a ( + .I0(sig00000100), + .I1(sig0000010a), + .O(sig00000022) + ); + XORCY blk0000007b ( + .CI(sig00000009), + .LI(sig00000021), + .O(sig00000146) + ); + MUXCY blk0000007c ( + .CI(sig00000009), + .DI(sig000000ff), + .S(sig00000021), + .O(sig0000000a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000007d ( + .I0(sig000000ff), + .I1(sig00000109), + .O(sig00000021) + ); + XORCY blk0000007e ( + .CI(sig00000008), + .LI(sig00000020), + .O(sig00000145) + ); + MUXCY blk0000007f ( + .CI(sig00000008), + .DI(sig000000fe), + .S(sig00000020), + .O(sig00000009) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000080 ( + .I0(sig000000fe), + .I1(sig00000108), + .O(sig00000020) + ); + XORCY blk00000081 ( + .CI(sig00000007), + .LI(sig0000001f), + .O(sig00000144) + ); + MUXCY blk00000082 ( + .CI(sig00000007), + .DI(sig000000fd), + .S(sig0000001f), + .O(sig00000008) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000083 ( + .I0(sig000000fd), + .I1(sig00000107), + .O(sig0000001f) + ); + XORCY blk00000084 ( + .CI(sig00000006), + .LI(sig0000001e), + .O(sig00000143) + ); + MUXCY blk00000085 ( + .CI(sig00000006), + .DI(sig000000fc), + .S(sig0000001e), + .O(sig00000007) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000086 ( + .I0(sig000000fc), + .I1(sig00000106), + .O(sig0000001e) + ); + XORCY blk00000087 ( + .CI(sig00000005), + .LI(sig0000001d), + .O(sig00000142) + ); + MUXCY blk00000088 ( + .CI(sig00000005), + .DI(sig000000fb), + .S(sig0000001d), + .O(sig00000006) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000089 ( + .I0(sig000000fb), + .I1(sig00000105), + .O(sig0000001d) + ); + XORCY blk0000008a ( + .CI(sig00000004), + .LI(sig0000001c), + .O(sig00000141) + ); + MUXCY blk0000008b ( + .CI(sig00000004), + .DI(sig000000fa), + .S(sig0000001c), + .O(sig00000005) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000008c ( + .I0(sig000000fa), + .I1(sig00000104), + .O(sig0000001c) + ); + XORCY blk0000008d ( + .CI(sig00000019), + .LI(sig0000001b), + .O(sig00000140) + ); + MUXCY blk0000008e ( + .CI(sig00000019), + .DI(sig000000f9), + .S(sig0000001b), + .O(sig00000004) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000008f ( + .I0(sig000000f9), + .I1(sig00000103), + .O(sig0000001b) + ); + XORCY blk00000090 ( + .CI(sig00000018), + .LI(sig00000031), + .O(sig00000156) + ); + MUXCY blk00000091 ( + .CI(sig00000018), + .DI(sig000000f8), + .S(sig00000031), + .O(sig00000019) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000092 ( + .I0(sig000000f8), + .I1(sig00000118), + .O(sig00000031) + ); + XORCY blk00000093 ( + .CI(sig00000017), + .LI(sig00000030), + .O(sig00000155) + ); + MUXCY blk00000094 ( + .CI(sig00000017), + .DI(sig000000f7), + .S(sig00000030), + .O(sig00000018) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000095 ( + .I0(sig000000f7), + .I1(sig00000117), + .O(sig00000030) + ); + XORCY blk00000096 ( + .CI(sig00000016), + .LI(sig0000002f), + .O(sig00000154) + ); + MUXCY blk00000097 ( + .CI(sig00000016), + .DI(sig000000f6), + .S(sig0000002f), + .O(sig00000017) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk00000098 ( + .I0(sig000000f6), + .I1(sig00000116), + .O(sig0000002f) + ); + XORCY blk00000099 ( + .CI(sig00000015), + .LI(sig0000002e), + .O(sig00000153) + ); + MUXCY blk0000009a ( + .CI(sig00000015), + .DI(sig000000f5), + .S(sig0000002e), + .O(sig00000016) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009b ( + .I0(sig000000f5), + .I1(sig00000115), + .O(sig0000002e) + ); + XORCY blk0000009c ( + .CI(sig00000014), + .LI(sig0000002d), + .O(sig00000152) + ); + MUXCY blk0000009d ( + .CI(sig00000014), + .DI(sig000000f4), + .S(sig0000002d), + .O(sig00000015) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk0000009e ( + .I0(sig000000f4), + .I1(sig00000114), + .O(sig0000002d) + ); + XORCY blk0000009f ( + .CI(sig00000013), + .LI(sig0000002c), + .O(sig00000151) + ); + MUXCY blk000000a0 ( + .CI(sig00000013), + .DI(sig000000f3), + .S(sig0000002c), + .O(sig00000014) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a1 ( + .I0(sig000000f3), + .I1(sig00000113), + .O(sig0000002c) + ); + XORCY blk000000a2 ( + .CI(sig00000012), + .LI(sig0000002b), + .O(sig00000150) + ); + MUXCY blk000000a3 ( + .CI(sig00000012), + .DI(sig000000f2), + .S(sig0000002b), + .O(sig00000013) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a4 ( + .I0(sig000000f2), + .I1(sig00000112), + .O(sig0000002b) + ); + XORCY blk000000a5 ( + .CI(sig0000000e), + .LI(sig0000002a), + .O(sig0000014f) + ); + MUXCY blk000000a6 ( + .CI(sig0000000e), + .DI(sig000000f1), + .S(sig0000002a), + .O(sig00000012) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000a7 ( + .I0(sig000000f1), + .I1(sig0000010d), + .O(sig0000002a) + ); + XORCY blk000000a8 ( + .CI(sig00000003), + .LI(sig00000025), + .O(sig0000014a) + ); + MUXCY blk000000a9 ( + .CI(sig00000003), + .DI(sig000000f0), + .S(sig00000025), + .O(sig0000000e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000aa ( + .I0(sig000000f0), + .I1(sig00000102), + .O(sig00000025) + ); + XORCY blk000000ab ( + .CI(sig00000001), + .LI(sig0000001a), + .O(sig0000013f) + ); + MUXCY blk000000ac ( + .CI(sig00000001), + .DI(sig000000ef), + .S(sig0000001a), + .O(sig00000003) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000ad ( + .I0(sig000000ef), + .I1(sig00000101), + .O(sig0000001a) + ); + XORCY blk000000ae ( + .CI(sig00000035), + .LI(sig00000043), + .O(sig0000015b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000af ( + .I0(sig00000129), + .I1(sig00000136), + .O(sig00000043) + ); + XORCY blk000000b0 ( + .CI(sig00000034), + .LI(sig00000042), + .O(sig0000015a) + ); + MUXCY blk000000b1 ( + .CI(sig00000034), + .DI(sig00000129), + .S(sig00000042), + .O(sig00000035) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b2 ( + .I0(sig00000129), + .I1(sig00000135), + .O(sig00000042) + ); + XORCY blk000000b3 ( + .CI(sig00000033), + .LI(sig00000041), + .O(sig00000159) + ); + MUXCY blk000000b4 ( + .CI(sig00000033), + .DI(sig00000129), + .S(sig00000041), + .O(sig00000034) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b5 ( + .I0(sig00000129), + .I1(sig00000134), + .O(sig00000041) + ); + XORCY blk000000b6 ( + .CI(sig0000003e), + .LI(sig00000040), + .O(sig00000158) + ); + MUXCY blk000000b7 ( + .CI(sig0000003e), + .DI(sig00000129), + .S(sig00000040), + .O(sig00000033) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000b8 ( + .I0(sig00000129), + .I1(sig00000133), + .O(sig00000040) + ); + XORCY blk000000b9 ( + .CI(sig0000003d), + .LI(sig0000004c), + .O(sig00000164) + ); + MUXCY blk000000ba ( + .CI(sig0000003d), + .DI(sig00000129), + .S(sig0000004c), + .O(sig0000003e) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000bb ( + .I0(sig00000129), + .I1(sig0000013e), + .O(sig0000004c) + ); + XORCY blk000000bc ( + .CI(sig0000003c), + .LI(sig0000004b), + .O(sig00000163) + ); + MUXCY blk000000bd ( + .CI(sig0000003c), + .DI(sig00000129), + .S(sig0000004b), + .O(sig0000003d) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000be ( + .I0(sig00000129), + .I1(sig0000013d), + .O(sig0000004b) + ); + XORCY blk000000bf ( + .CI(sig0000003b), + .LI(sig0000004a), + .O(sig00000162) + ); + MUXCY blk000000c0 ( + .CI(sig0000003b), + .DI(sig00000129), + .S(sig0000004a), + .O(sig0000003c) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000c1 ( + .I0(sig00000129), + .I1(sig0000013c), + .O(sig0000004a) + ); + XORCY blk000000c2 ( + .CI(sig0000003a), + .LI(sig00000049), + .O(sig00000161) + ); + MUXCY blk000000c3 ( + .CI(sig0000003a), + .DI(sig00000129), + .S(sig00000049), + .O(sig0000003b) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000c4 ( + .I0(sig00000129), + .I1(sig0000013b), + .O(sig00000049) + ); + XORCY blk000000c5 ( + .CI(sig00000039), + .LI(sig00000048), + .O(sig00000160) + ); + MUXCY blk000000c6 ( + .CI(sig00000039), + .DI(sig00000128), + .S(sig00000048), + .O(sig0000003a) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000c7 ( + .I0(sig00000128), + .I1(sig0000013a), + .O(sig00000048) + ); + XORCY blk000000c8 ( + .CI(sig00000038), + .LI(sig00000047), + .O(sig0000015f) + ); + MUXCY blk000000c9 ( + .CI(sig00000038), + .DI(sig00000127), + .S(sig00000047), + .O(sig00000039) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000ca ( + .I0(sig00000127), + .I1(sig00000139), + .O(sig00000047) + ); + XORCY blk000000cb ( + .CI(sig00000037), + .LI(sig00000046), + .O(sig0000015e) + ); + MUXCY blk000000cc ( + .CI(sig00000037), + .DI(sig00000126), + .S(sig00000046), + .O(sig00000038) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000cd ( + .I0(sig00000126), + .I1(sig00000138), + .O(sig00000046) + ); + XORCY blk000000ce ( + .CI(sig00000036), + .LI(sig00000045), + .O(sig0000015d) + ); + MUXCY blk000000cf ( + .CI(sig00000036), + .DI(sig00000124), + .S(sig00000045), + .O(sig00000037) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d0 ( + .I0(sig00000124), + .I1(sig00000137), + .O(sig00000045) + ); + XORCY blk000000d1 ( + .CI(sig00000032), + .LI(sig00000044), + .O(sig0000015c) + ); + MUXCY blk000000d2 ( + .CI(sig00000032), + .DI(sig00000123), + .S(sig00000044), + .O(sig00000036) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d3 ( + .I0(sig00000123), + .I1(sig00000132), + .O(sig00000044) + ); + XORCY blk000000d4 ( + .CI(sig00000001), + .LI(sig0000003f), + .O(sig00000157) + ); + MUXCY blk000000d5 ( + .CI(sig00000001), + .DI(sig00000122), + .S(sig0000003f), + .O(sig00000032) + ); + LUT2 #( + .INIT ( 4'h6 )) + blk000000d6 ( + .I0(sig00000122), + .I1(sig00000131), + .O(sig0000003f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000d7 ( + .C(clk), + .D(sig000000d8), + .Q(sig00000129) + ); + FD #( + .INIT ( 1'b0 )) + blk000000d8 ( + .C(clk), + .D(sig000000d7), + .Q(sig00000128) + ); + FD #( + .INIT ( 1'b0 )) + blk000000d9 ( + .C(clk), + .D(sig000000d6), + .Q(sig00000127) + ); + FD #( + .INIT ( 1'b0 )) + blk000000da ( + .C(clk), + .D(sig000000d5), + .Q(sig00000126) + ); + FD #( + .INIT ( 1'b0 )) + blk000000db ( + .C(clk), + .D(sig000000d3), + .Q(sig00000124) + ); + FD #( + .INIT ( 1'b0 )) + blk000000dc ( + .C(clk), + .D(sig000000d2), + .Q(sig00000123) + ); + FD #( + .INIT ( 1'b0 )) + blk000000dd ( + .C(clk), + .D(sig000000d1), + .Q(sig00000122) + ); + FD #( + .INIT ( 1'b0 )) + blk000000de ( + .C(clk), + .D(sig000000d0), + .Q(sig00000121) + ); + FD #( + .INIT ( 1'b0 )) + blk000000df ( + .C(clk), + .D(sig000000cf), + .Q(sig00000120) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e0 ( + .C(clk), + .D(sig000000ce), + .Q(sig0000011f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e1 ( + .C(clk), + .D(sig000000cd), + .Q(sig0000011e) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e2 ( + .C(clk), + .D(sig000000cc), + .Q(sig0000011d) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e3 ( + .C(clk), + .D(sig000000cb), + .Q(sig0000011c) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e4 ( + .C(clk), + .D(sig000000ca), + .Q(sig0000011b) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e5 ( + .C(clk), + .D(sig000000e0), + .Q(sig00000130) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e6 ( + .C(clk), + .D(sig000000df), + .Q(sig0000012f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e7 ( + .C(clk), + .D(sig000000de), + .Q(sig0000012e) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e8 ( + .C(clk), + .D(sig000000dd), + .Q(sig0000012d) + ); + FD #( + .INIT ( 1'b0 )) + blk000000e9 ( + .C(clk), + .D(sig000000dc), + .Q(sig0000012c) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ea ( + .C(clk), + .D(sig000000db), + .Q(sig0000012b) + ); + FD #( + .INIT ( 1'b0 )) + blk000000eb ( + .C(clk), + .D(sig000000da), + .Q(sig0000012a) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ec ( + .C(clk), + .D(sig000000d9), + .Q(sig00000125) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ed ( + .C(clk), + .D(sig000000d4), + .Q(sig0000011a) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ee ( + .C(clk), + .D(sig000000c9), + .Q(sig00000119) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ef ( + .C(clk), + .D(sig000000c0), + .Q(sig00000111) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f0 ( + .C(clk), + .D(sig000000bf), + .Q(sig00000110) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f1 ( + .C(clk), + .D(sig000000be), + .Q(sig0000010f) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f2 ( + .C(clk), + .D(sig000000bd), + .Q(sig0000010e) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f3 ( + .C(clk), + .D(sig000000bb), + .Q(sig0000010c) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f4 ( + .C(clk), + .D(sig000000ba), + .Q(sig0000010b) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f5 ( + .C(clk), + .D(sig000000b9), + .Q(sig0000010a) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f6 ( + .C(clk), + .D(sig000000b8), + .Q(sig00000109) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f7 ( + .C(clk), + .D(sig000000b7), + .Q(sig00000108) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f8 ( + .C(clk), + .D(sig000000b6), + .Q(sig00000107) + ); + FD #( + .INIT ( 1'b0 )) + blk000000f9 ( + .C(clk), + .D(sig000000b5), + .Q(sig00000106) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fa ( + .C(clk), + .D(sig000000b4), + .Q(sig00000105) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fb ( + .C(clk), + .D(sig000000b3), + .Q(sig00000104) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fc ( + .C(clk), + .D(sig000000b2), + .Q(sig00000103) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fd ( + .C(clk), + .D(sig000000c8), + .Q(sig00000118) + ); + FD #( + .INIT ( 1'b0 )) + blk000000fe ( + .C(clk), + .D(sig000000c7), + .Q(sig00000117) + ); + FD #( + .INIT ( 1'b0 )) + blk000000ff ( + .C(clk), + .D(sig000000c6), + .Q(sig00000116) + ); + FD #( + .INIT ( 1'b0 )) + blk00000100 ( + .C(clk), + .D(sig000000c5), + .Q(sig00000115) + ); + FD #( + .INIT ( 1'b0 )) + blk00000101 ( + .C(clk), + .D(sig000000c4), + .Q(sig00000114) + ); + FD #( + .INIT ( 1'b0 )) + blk00000102 ( + .C(clk), + .D(sig000000c3), + .Q(sig00000113) + ); + FD #( + .INIT ( 1'b0 )) + blk00000103 ( + .C(clk), + .D(sig000000c2), + .Q(sig00000112) + ); + FD #( + .INIT ( 1'b0 )) + blk00000104 ( + .C(clk), + .D(sig000000c1), + .Q(sig0000010d) + ); + FD #( + .INIT ( 1'b0 )) + blk00000105 ( + .C(clk), + .D(sig000000bc), + .Q(sig00000102) + ); + FD #( + .INIT ( 1'b0 )) + blk00000106 ( + .C(clk), + .D(sig000000b1), + .Q(sig00000101) + ); + FD #( + .INIT ( 1'b0 )) + blk00000107 ( + .C(clk), + .D(sig000000e5), + .Q(sig00000136) + ); + FD #( + .INIT ( 1'b0 )) + blk00000108 ( + .C(clk), + .D(sig000000e4), + .Q(sig00000135) + ); + FD #( + .INIT ( 1'b0 )) + blk00000109 ( + .C(clk), + .D(sig000000e3), + .Q(sig00000134) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010a ( + .C(clk), + .D(sig000000e2), + .Q(sig00000133) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010b ( + .C(clk), + .D(sig000000ee), + .Q(sig0000013e) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010c ( + .C(clk), + .D(sig000000ed), + .Q(sig0000013d) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010d ( + .C(clk), + .D(sig000000ec), + .Q(sig0000013c) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010e ( + .C(clk), + .D(sig000000eb), + .Q(sig0000013b) + ); + FD #( + .INIT ( 1'b0 )) + blk0000010f ( + .C(clk), + .D(sig000000ea), + .Q(sig0000013a) + ); + FD #( + .INIT ( 1'b0 )) + blk00000110 ( + .C(clk), + .D(sig000000e9), + .Q(sig00000139) + ); + FD #( + .INIT ( 1'b0 )) + blk00000111 ( + .C(clk), + .D(sig000000e8), + .Q(sig00000138) + ); + FD #( + .INIT ( 1'b0 )) + blk00000112 ( + .C(clk), + .D(sig000000e7), + .Q(sig00000137) + ); + FD #( + .INIT ( 1'b0 )) + blk00000113 ( + .C(clk), + .D(sig000000e6), + .Q(sig00000132) + ); + FD #( + .INIT ( 1'b0 )) + blk00000114 ( + .C(clk), + .D(sig000000e1), + .Q(sig00000131) + ); + FD #( + .INIT ( 1'b0 )) + blk00000115 ( + .C(clk), + .D(sig000000a9), + .Q(sig00000100) + ); + FD #( + .INIT ( 1'b0 )) + blk00000116 ( + .C(clk), + .D(sig000000a8), + .Q(sig000000ff) + ); + FD #( + .INIT ( 1'b0 )) + blk00000117 ( + .C(clk), + .D(sig000000a7), + .Q(sig000000fe) + ); + FD #( + .INIT ( 1'b0 )) + blk00000118 ( + .C(clk), + .D(sig000000a6), + .Q(sig000000fd) + ); + FD #( + .INIT ( 1'b0 )) + blk00000119 ( + .C(clk), + .D(sig000000a5), + .Q(sig000000fc) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011a ( + .C(clk), + .D(sig000000a3), + .Q(sig000000fb) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011b ( + .C(clk), + .D(sig000000a2), + .Q(sig000000fa) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011c ( + .C(clk), + .D(sig000000a1), + .Q(sig000000f9) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011d ( + .C(clk), + .D(sig000000a0), + .Q(sig000000f8) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011e ( + .C(clk), + .D(sig0000009f), + .Q(sig000000f7) + ); + FD #( + .INIT ( 1'b0 )) + blk0000011f ( + .C(clk), + .D(sig0000009e), + .Q(sig000000f6) + ); + FD #( + .INIT ( 1'b0 )) + blk00000120 ( + .C(clk), + .D(sig0000009d), + .Q(sig000000f5) + ); + FD #( + .INIT ( 1'b0 )) + blk00000121 ( + .C(clk), + .D(sig0000009c), + .Q(sig000000f4) + ); + FD #( + .INIT ( 1'b0 )) + blk00000122 ( + .C(clk), + .D(sig0000009b), + .Q(sig000000f3) + ); + FD #( + .INIT ( 1'b0 )) + blk00000123 ( + .C(clk), + .D(sig0000009a), + .Q(sig000000f2) + ); + FD #( + .INIT ( 1'b0 )) + blk00000124 ( + .C(clk), + .D(sig00000098), + .Q(sig000000f1) + ); + FD #( + .INIT ( 1'b0 )) + blk00000125 ( + .C(clk), + .D(sig00000097), + .Q(sig000000f0) + ); + FD #( + .INIT ( 1'b0 )) + blk00000126 ( + .C(clk), + .D(sig00000096), + .Q(sig000000ef) + ); + FD #( + .INIT ( 1'b0 )) + blk00000127 ( + .C(clk), + .D(sig00000095), + .Q(p[16]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000128 ( + .C(clk), + .D(sig00000094), + .Q(p[15]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000129 ( + .C(clk), + .D(sig00000093), + .Q(p[14]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012a ( + .C(clk), + .D(sig00000092), + .Q(p[13]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012b ( + .C(clk), + .D(sig00000091), + .Q(p[12]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012c ( + .C(clk), + .D(sig00000090), + .Q(p[11]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012d ( + .C(clk), + .D(sig0000008f), + .Q(p[10]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012e ( + .C(clk), + .D(sig000000b0), + .Q(p[9]) + ); + FD #( + .INIT ( 1'b0 )) + blk0000012f ( + .C(clk), + .D(sig000000af), + .Q(p[8]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000130 ( + .C(clk), + .D(sig000000ae), + .Q(p[7]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000131 ( + .C(clk), + .D(sig000000ad), + .Q(p[6]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000132 ( + .C(clk), + .D(sig000000ac), + .Q(p[5]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000133 ( + .C(clk), + .D(sig000000ab), + .Q(p[4]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000134 ( + .C(clk), + .D(sig000000aa), + .Q(p[3]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000135 ( + .C(clk), + .D(sig000000a4), + .Q(p[2]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000136 ( + .C(clk), + .D(sig00000099), + .Q(p[1]) + ); + FD #( + .INIT ( 1'b0 )) + blk00000137 ( + .C(clk), + .D(sig0000008e), + .Q(p[0]) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco new file mode 100644 index 0000000..89401df --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xco @@ -0,0 +1,68 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Fri Oct 21 20:38:07 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:mult_gen:11.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Multiplier xilinx.com:ip:mult_gen:11.2 +# END Select +# BEGIN Parameters +CSET ccmimp=Distributed_Memory +CSET clockenable=false +CSET component_name=cx4_mul +CSET constvalue=129 +CSET internaluser=0 +CSET multiplier_construction=Use_Mults +CSET multtype=Parallel_Multiplier +CSET optgoal=Speed +CSET outputwidthhigh=47 +CSET outputwidthlow=0 +CSET pipestages=2 +CSET portatype=Signed +CSET portawidth=24 +CSET portbtype=Signed +CSET portbwidth=24 +CSET roundpoint=0 +CSET sclrcepriority=SCLR_Overrides_CE +CSET syncclear=false +CSET use_custom_output_width=false +CSET userounding=false +CSET zerodetect=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:26:54.000Z +# END Extra information +GENERATE +# CRC: efe4d30e diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise new file mode 100644 index 0000000..12daee6 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_mul.xise @@ -0,0 +1,378 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v new file mode 100644 index 0000000..88379dd --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file cx4_pgmrom.v when simulating +// the core, cx4_pgmrom. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module cx4_pgmrom( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [9 : 0] addra; +input [7 : 0] dina; +input clkb; +input [8 : 0] addrb; +output [15 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_2 #( + .C_ADDRA_WIDTH(10), + .C_ADDRB_WIDTH(9), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(1024), + .C_READ_DEPTH_B(512), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(16), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(1024), + .C_WRITE_DEPTH_B(512), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(16), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco new file mode 100644 index 0000000..59cb743 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Tue Oct 18 18:45:53 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=cx4_pgmrom +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=16 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=1024 +CSET write_width_a=8 +CSET write_width_b=16 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-03-11T08:24:14.000Z +# END Extra information +GENERATE +# CRC: 30264765 diff --git a/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise new file mode 100644 index 0000000..72cb4ec --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/cx4_pgmrom.xise @@ -0,0 +1,72 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/dac_buf.v b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.v new file mode 100644 index 0000000..8e2574d --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file dac_buf.v when simulating +// the core, dac_buf. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module dac_buf( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [10 : 0] addra; +input [7 : 0] dina; +input clkb; +input [8 : 0] addrb; +output [31 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_1 #( + .C_ADDRA_WIDTH(11), + .C_ADDRB_WIDTH(9), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(2048), + .C_READ_DEPTH_B(512), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(32), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(2048), + .C_WRITE_DEPTH_B(512), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(32), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco new file mode 100644 index 0000000..24fdf34 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Mon Oct 10 19:47:34 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=dac_buf +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=32 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=2048 +CSET write_width_a=8 +CSET write_width_b=32 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:43:52.000Z +# END Extra information +GENERATE +# CRC: 60863d15 diff --git a/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise new file mode 100644 index 0000000..e094ff8 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/dac_buf.xise @@ -0,0 +1,79 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v new file mode 100644 index 0000000..4528b98 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.v @@ -0,0 +1,181 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2011 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file msu_databuf.v when simulating +// the core, msu_databuf. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module msu_databuf( + clka, + wea, + addra, + dina, + clkb, + addrb, + doutb +); + +input clka; +input [0 : 0] wea; +input [13 : 0] addra; +input [7 : 0] dina; +input clkb; +input [13 : 0] addrb; +output [7 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V6_1 #( + .C_ADDRA_WIDTH(14), + .C_ADDRB_WIDTH(14), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(16384), + .C_READ_DEPTH_B(16384), + .C_READ_WIDTH_A(8), + .C_READ_WIDTH_B(8), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(16384), + .C_WRITE_DEPTH_B(16384), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(8), + .C_WRITE_WIDTH_B(8), + .C_XDEVICEFAMILY("spartan3") + ) + inst ( + .CLKA(clka), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco new file mode 100644 index 0000000..61a41b5 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xco @@ -0,0 +1,105 @@ +############################################################## +# +# Xilinx Core Generator version 13.2 +# Date: Mon Oct 10 19:48:38 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:6.1 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc3s400 +SET devicefamily = spartan3 +SET flowvendor = Foundation_ISE +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = pq208 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -4 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=9 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=msu_databuf +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_a=Always_Enabled +CSET enable_b=Always_Enabled +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=WRITE_FIRST +CSET operating_mode_b=WRITE_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=8 +CSET read_width_b=8 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_byte_write_enable=false +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=16384 +CSET write_width_a=8 +CSET write_width_b=8 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2011-06-21T06:43:52.000Z +# END Extra information +GENERATE +# CRC: bebc21bb diff --git a/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise new file mode 100644 index 0000000..4d2c480 --- /dev/null +++ b/verilog/sd2snes_cx4/ipcore_dir/msu_databuf.xise @@ -0,0 +1,79 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/main.v b/verilog/sd2snes_cx4/main.v new file mode 100644 index 0000000..b8fcf11 --- /dev/null +++ b/verilog/sd2snes_cx4/main.v @@ -0,0 +1,564 @@ +`timescale 1 ns / 1 ns +////////////////////////////////////////////////////////////////////////////////// +// Company: Rehkopf +// Engineer: Rehkopf +// +// Create Date: 01:13:46 05/09/2009 +// Design Name: +// Module Name: main +// Project Name: +// Target Devices: +// Tool versions: +// Description: Master Control FSM +// +// Dependencies: address +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module main( + /* input clock */ + input CLKIN, + + /* SNES signals */ + input [23:0] SNES_ADDR, + input SNES_READ, + input SNES_WRITE, + input SNES_CS, + inout [7:0] SNES_DATA, + input SNES_CPU_CLK, + input SNES_REFRESH, + output SNES_IRQ, + output SNES_DATABUS_OE, + output SNES_DATABUS_DIR, + input SNES_SYSCLK, + + /* SRAM signals */ + /* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */ + inout [15:0] ROM_DATA, + output [22:0] ROM_ADDR, + output ROM_CE, + output ROM_OE, + output ROM_WE, + output ROM_BHE, + output ROM_BLE, + + /* Bus 2: SRAM, 4Mbit, 8bit, 45ns */ + inout [7:0] RAM_DATA, + output [18:0] RAM_ADDR, + output RAM_CE, + output RAM_OE, + output RAM_WE, + + /* MCU signals */ + input SPI_MOSI, + inout SPI_MISO, + input SPI_SS, + inout SPI_SCK, + input MCU_OVR, + output MCU_RDY, + + output DAC_MCLK, + output DAC_LRCK, + output DAC_SDOUT, + + /* SD signals */ + input [3:0] SD_DAT, + inout SD_CMD, + inout SD_CLK, + + /* debug */ + output p113_out +); + +wire [7:0] spi_cmd_data; +wire [7:0] spi_param_data; +wire [7:0] spi_input_data; +wire [31:0] spi_byte_cnt; +wire [2:0] spi_bit_cnt; +wire [23:0] MCU_ADDR; +wire [2:0] MAPPER; +wire [23:0] SAVERAM_MASK; +wire [23:0] ROM_MASK; +wire [7:0] SD_DMA_SRAM_DATA; +wire [1:0] SD_DMA_TGT; +wire [10:0] SD_DMA_PARTIAL_START; +wire [10:0] SD_DMA_PARTIAL_END; + +wire [10:0] dac_addr; +//wire [7:0] dac_volume; +wire [7:0] msu_volumerq_out; +wire [6:0] msu_status_out; +wire [31:0] msu_addressrq_out; +wire [15:0] msu_trackrq_out; +wire [13:0] msu_write_addr; +wire [13:0] msu_ptr_addr; +wire [7:0] MSU_SNES_DATA_IN; +wire [7:0] MSU_SNES_DATA_OUT; +wire [5:0] msu_status_reset_bits; +wire [5:0] msu_status_set_bits; + +wire [7:0] CX4_SNES_DATA_IN; +wire [7:0] CX4_SNES_DATA_OUT; + +wire [23:0] MAPPED_SNES_ADDR; +wire ROM_ADDR0; + +sd_dma snes_sd_dma( + .CLK(CLK2), + .SD_DAT(SD_DAT), + .SD_CLK(SD_CLK), + .SD_DMA_EN(SD_DMA_EN), + .SD_DMA_STATUS(SD_DMA_STATUS), + .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), + .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), + .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), + .SD_DMA_PARTIAL(SD_DMA_PARTIAL), + .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END) +); + +wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00)); + +dac snes_dac( + .clkin(CLK2), + .sysclk(SNES_SYSCLK), + .mclk(DAC_MCLK), + .lrck(DAC_LRCK), + .sdout(DAC_SDOUT), + .we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1), + .pgm_address(dac_addr), + .pgm_data(SD_DMA_SRAM_DATA), + .DAC_STATUS(DAC_STATUS), + .volume(msu_volumerq_out), + .vol_latch(msu_volume_latch_out), + .play(dac_play), + .reset(dac_reset) +); + +msu snes_msu ( + .clkin(CLK2), + .enable(msu_enable), + .pgm_address(msu_write_addr), + .pgm_data(SD_DMA_SRAM_DATA), + .pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1), + .reg_addr(SNES_ADDR[2:0]), + .reg_data_in(MSU_SNES_DATA_IN), + .reg_data_out(MSU_SNES_DATA_OUT), + .reg_oe(SNES_READ), + .reg_we(SNES_WRITE), + .status_out(msu_status_out), + .volume_out(msu_volumerq_out), + .volume_latch_out(msu_volume_latch_out), + .addr_out(msu_addressrq_out), + .track_out(msu_trackrq_out), + .status_reset_bits(msu_status_reset_bits), + .status_set_bits(msu_status_set_bits), + .status_reset_we(msu_status_reset_we), + .msu_address_ext(msu_ptr_addr), + .msu_address_ext_write(msu_addr_reset) +); + +spi snes_spi( + .clk(CLK2), + .MOSI(SPI_MOSI), + .MISO(SPI_MISO), + .SSEL(SPI_SS), + .SCK(SPI_SCK), + .cmd_ready(spi_cmd_ready), + .param_ready(spi_param_ready), + .cmd_data(spi_cmd_data), + .param_data(spi_param_data), + .endmessage(spi_endmessage), + .startmessage(spi_startmessage), + .input_data(spi_input_data), + .byte_cnt(spi_byte_cnt), + .bit_cnt(spi_bit_cnt) +); + +reg [7:0] MCU_DINr; +wire [7:0] MCU_DOUT; + +mcu_cmd snes_mcu_cmd( + .clk(CLK2), + .snes_sysclk(SNES_SYSCLK), + .cmd_ready(spi_cmd_ready), + .param_ready(spi_param_ready), + .cmd_data(spi_cmd_data), + .param_data(spi_param_data), + .mcu_mapper(MAPPER), + .mcu_write(MCU_WRITE), + .mcu_data_in(MCU_DINr), + .mcu_data_out(MCU_DOUT), + .spi_byte_cnt(spi_byte_cnt), + .spi_bit_cnt(spi_bit_cnt), + .spi_data_out(spi_input_data), + .addr_out(MCU_ADDR), + .saveram_mask_out(SAVERAM_MASK), + .rom_mask_out(ROM_MASK), + .SD_DMA_EN(SD_DMA_EN), + .SD_DMA_STATUS(SD_DMA_STATUS), + .SD_DMA_NEXTADDR(SD_DMA_NEXTADDR), + .SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA), + .SD_DMA_SRAM_WE(SD_DMA_SRAM_WE), + .SD_DMA_TGT(SD_DMA_TGT), + .SD_DMA_PARTIAL(SD_DMA_PARTIAL), + .SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START), + .SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END), + .dac_addr_out(dac_addr), + .DAC_STATUS(DAC_STATUS), +// .dac_volume_out(dac_volume), +// .dac_volume_latch_out(dac_vol_latch), + .dac_play_out(dac_play), + .dac_reset_out(dac_reset), + .msu_addr_out(msu_write_addr), + .MSU_STATUS(msu_status_out), + .msu_status_reset_out(msu_status_reset_bits), + .msu_status_set_out(msu_status_set_bits), + .msu_status_reset_we(msu_status_reset_we), + .msu_volumerq(msu_volumerq_out), + .msu_addressrq(msu_addressrq_out), + .msu_trackrq(msu_trackrq_out), + .msu_ptr_out(msu_ptr_addr), + .msu_reset_out(msu_addr_reset), + .mcu_rrq(MCU_RRQ), + .mcu_wrq(MCU_WRQ), + .mcu_rq_rdy(MCU_RDY), + .use_msu1(use_msu1) +); + +wire [7:0] DCM_STATUS; +// dcm1: dfs 4x +my_dcm snes_dcm( + .CLKIN(CLKIN), + .CLKFX(CLK2), + .LOCKED(DCM_LOCKED), + .RST(DCM_RST), + .STATUS(DCM_STATUS) +); + +assign DCM_RST=0; + +reg [5:0] SNES_READr; +reg [5:0] SNES_WRITEr; +reg [5:0] SNES_CPU_CLKr; + +wire SNES_RD_start = (SNES_READr == 6'b111110); +wire SNES_WR_start = (SNES_WRITEr == 6'b111110); +wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001); +wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110); + +always @(posedge CLK2) begin + SNES_READr <= {SNES_READr[4:0], SNES_READ}; + SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE}; + SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK}; +end + +address snes_addr( + .CLK(CLK2), + .MAPPER(MAPPER), + .SNES_ADDR(SNES_ADDR), // requested address from SNES + .ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low) + .ROM_SEL(ROM_SEL), // which SRAM unit to access + .IS_SAVERAM(IS_SAVERAM), + .IS_ROM(IS_ROM), + .IS_WRITABLE(IS_WRITABLE), + .SAVERAM_MASK(SAVERAM_MASK), + .ROM_MASK(ROM_MASK), + .use_msu1(use_msu1), + //MSU-1 + .msu_enable(msu_enable), + //CX4 + .cx4_enable(cx4_enable) +); + +reg [7:0] CX4_DINr; +wire [23:0] CX4_ADDR; + +cx4 snes_cx4 ( + .DI(CX4_SNES_DATA_IN), + .DO(CX4_SNES_DATA_OUT), + .ADDR(SNES_ADDR[12:0]), + .CS(cx4_enable), + .nRD(SNES_READ), + .nWR(SNES_WRITE), + .CLK(CLK2), + .DATROM_DI(DATROM_DI), + .DATROM_WE(DATROM_WE), + .DATROM_ADDR(DATROM_ADDR), + .BUS_DI(CX4_DINr), + .BUS_ADDR(CX4_ADDR), + .BUS_RRQ(CX4_RRQ), + .BUS_RDY(CX4_RDY) + ); + +parameter MODE_SNES = 1'b0; +parameter MODE_MCU = 1'b1; + +parameter ST_IDLE = 21'b000000000000000000001; +parameter ST_SNES_RD_ADDR = 21'b000000000000000000010; +parameter ST_SNES_RD_WAIT = 21'b000000000000000000100; +parameter ST_SNES_RD_END = 21'b000000000000000001000; +parameter ST_SNES_WR_ADDR = 21'b000000000000000010000; +parameter ST_SNES_WR_WAIT1= 21'b000000000000000100000; +parameter ST_SNES_WR_DATA = 21'b000000000000001000000; +parameter ST_SNES_WR_WAIT2= 21'b000000000000010000000; +parameter ST_SNES_WR_END = 21'b000000000000100000000; +parameter ST_MCU_RD_ADDR = 21'b000000000001000000000; +parameter ST_MCU_RD_WAIT = 21'b000000000010000000000; +parameter ST_MCU_RD_WAIT2 = 21'b000000000100000000000; +parameter ST_MCU_RD_END = 21'b000000001000000000000; +parameter ST_MCU_WR_ADDR = 21'b000000010000000000000; +parameter ST_MCU_WR_WAIT = 21'b000000100000000000000; +parameter ST_MCU_WR_WAIT2 = 21'b000001000000000000000; +parameter ST_MCU_WR_END = 21'b000010000000000000000; +parameter ST_CX4_RD_ADDR = 21'b000100000000000000000; +parameter ST_CX4_RD_WAIT = 21'b001000000000000000000; +parameter ST_CX4_RD_WAIT2 = 21'b010000000000000000000; +parameter ST_CX4_RD_END = 21'b100000000000000000000; + +parameter ROM_RD_WAIT = 4'h4; +parameter ROM_RD_WAIT_MCU = 4'h6; +parameter ROM_WR_WAIT1 = 4'h2; +parameter ROM_WR_WAIT2 = 4'h3; +parameter ROM_WR_WAIT_MCU = 4'h6; +parameter ROM_RD_WAIT_CX4 = 4'h6; + +reg [20:0] STATE; +initial STATE = ST_IDLE; + +assign MSU_SNES_DATA_IN = SNES_DATA; +assign CX4_SNES_DATA_IN = SNES_DATA; + +reg [7:0] SNES_DINr; +reg [7:0] ROM_DOUTr; + +assign SNES_DATA = (!SNES_READ) ? (msu_enable ? MSU_SNES_DATA_OUT + :cx4_enable ? CX4_SNES_DATA_OUT + :SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ; + +reg [3:0] ST_MEM_DELAYr; +reg MCU_RD_PENDr; +reg MCU_WR_PENDr; +reg CX4_RD_PENDr; +reg [23:0] ROM_ADDRr; +reg NEED_SNES_ADDRr; +always @(posedge CLK2) begin + if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1; + else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0; +end + +wire IS_CART = IS_ROM | IS_SAVERAM | IS_WRITABLE; +wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr & IS_CART; + +assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1]; +assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0]; + +reg ROM_WEr; +initial ROM_WEr = 1'b1; + +reg RQ_MCU_RDYr; +initial RQ_MCU_RDYr = 1'b1; +assign MCU_RDY = RQ_MCU_RDYr; + +always @(posedge CLK2) begin + if(MCU_RRQ) begin + MCU_RD_PENDr <= 1'b1; + RQ_MCU_RDYr <= 1'b0; + end else if(MCU_WRQ) begin + MCU_WR_PENDr <= 1'b1; + RQ_MCU_RDYr <= 1'b0; + end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin + MCU_RD_PENDr <= 1'b0; + MCU_WR_PENDr <= 1'b0; + RQ_MCU_RDYr <= 1'b1; + end +end + +reg RQ_CX4_RDYr; +initial RQ_CX4_RDYr = 1'b1; +assign CX4_RDY = RQ_CX4_RDYr; + +always @(posedge CLK2) begin + if(CX4_RRQ) begin + CX4_RD_PENDr <= 1'b1; + RQ_CX4_RDYr <= 1'b0; + end else if(STATE == ST_CX4_RD_WAIT && ST_MEM_DELAYr == 4'h0) begin + CX4_RD_PENDr <= 1'b0; + RQ_CX4_RDYr <= 1'b1; + end +end + +reg snes_wr_cycle; + +always @(posedge CLK2) begin + if(SNES_cycle_start & IS_CART) begin + STATE <= ST_SNES_RD_ADDR; + end else if(SNES_WR_start & IS_CART) begin + STATE <= ST_SNES_WR_ADDR; + end else begin + case(STATE) + ST_IDLE: begin + ROM_ADDRr <= MAPPED_SNES_ADDR; + if(CX4_RRQ | CX4_RD_PENDr) begin + ROM_ADDRr <= CX4_ADDR; + STATE <= ST_CX4_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + else if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR; + else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR; + else STATE <= ST_IDLE; + end + ST_SNES_RD_ADDR: begin + STATE <= ST_SNES_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT; + end + ST_SNES_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END; + else STATE <= ST_SNES_RD_WAIT; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end + ST_SNES_RD_END: begin + STATE <= ST_IDLE; + if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0]; + else SNES_DINr <= ROM_DATA[15:8]; + end + ST_SNES_WR_ADDR: begin + ROM_WEr <= (!IS_WRITABLE); + snes_wr_cycle <= 1'b1; + STATE <= ST_SNES_WR_WAIT1; + ST_MEM_DELAYr <= ROM_WR_WAIT1; + end + ST_SNES_WR_WAIT1: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA; + else STATE <= ST_SNES_WR_WAIT1; + end + ST_SNES_WR_DATA: begin + ROM_DOUTr <= SNES_DATA; + ST_MEM_DELAYr <= ROM_WR_WAIT2; + STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END; + else STATE <= ST_SNES_WR_WAIT2; + end + ST_SNES_WR_END: begin + STATE <= ST_IDLE; + ROM_WEr <= 1'b1; + snes_wr_cycle <= 1'b0; + end + ST_MCU_RD_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_MCU; + end + ST_MCU_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_RD_WAIT; + if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0]; + else MCU_DINr <= ROM_DATA[15:8]; + end + ST_MCU_RD_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_RD_END; + end else STATE <= ST_MCU_RD_WAIT2; + end + ST_MCU_RD_END: begin + STATE <= ST_IDLE; + end + ST_MCU_WR_ADDR: begin + ROM_ADDRr <= MCU_ADDR; + STATE <= ST_MCU_WR_WAIT; + ST_MEM_DELAYr <= ROM_WR_WAIT_MCU; + ROM_DOUTr <= MCU_DOUT; + ROM_WEr <= 1'b0; + end + ST_MCU_WR_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + ROM_WEr <= 1'b1; + STATE <= ST_MCU_WR_WAIT2; + ST_MEM_DELAYr <= 4'h2; + end + else STATE <= ST_MCU_WR_WAIT; + end + ST_MCU_WR_WAIT2: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_MCU_WR_END; + end else STATE <= ST_MCU_WR_WAIT2; + end + ST_MCU_WR_END: begin + STATE <= ST_IDLE; + end + + ST_CX4_RD_ADDR: begin + ROM_ADDRr <= CX4_ADDR; + STATE <= ST_CX4_RD_WAIT; + ST_MEM_DELAYr <= ROM_RD_WAIT_CX4; + end + ST_CX4_RD_WAIT: begin + ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1; + if(ST_MEM_DELAYr == 4'h0) begin + STATE <= ST_IDLE; + end + else STATE <= ST_CX4_RD_WAIT; + if(ROM_ADDR0) CX4_DINr <= ROM_DATA[7:0]; + else CX4_DINr <= ROM_DATA[15:8]; + end + ST_CX4_RD_END: begin + STATE <= ST_IDLE; + end + endcase + end +end + +assign ROM_DATA[7:0] = ROM_ADDR0 + ?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) + : (!ROM_WE ? ROM_DOUTr : 8'bZ) + ) + :8'bZ; + +assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ + :(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ) + : (!ROM_WE ? ROM_DOUTr : 8'bZ) + ); + +assign ROM_WE = SD_DMA_TO_ROM + ?MCU_WRITE + :ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle); + +// OE always active. Overridden by WE when needed. +assign ROM_OE = 1'b0; + +assign ROM_CE = 1'b0; + +assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0; +assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0; + +assign SNES_DATABUS_OE = msu_enable ? 1'b0 : + cx4_enable ? 1'b0 : + ((IS_ROM & SNES_CS) + |(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE) + |(SNES_READ & SNES_WRITE) + ); + +assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0; + +assign IRQ_DIR = 1'b0; +assign SNES_IRQ = 1'bZ; + +assign p113_out = 1'b0; + +endmodule diff --git a/verilog/sd2snes_cx4/msu.v b/verilog/sd2snes_cx4/msu.v new file mode 100644 index 0000000..32b106a --- /dev/null +++ b/verilog/sd2snes_cx4/msu.v @@ -0,0 +1,194 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:55:04 12/14/2010 +// Design Name: +// Module Name: msu +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module msu( + input clkin, + input enable, + input [13:0] pgm_address, + input [7:0] pgm_data, + input pgm_we, + input [2:0] reg_addr, + input [7:0] reg_data_in, + output [7:0] reg_data_out, + input reg_oe, + input reg_we, + output [6:0] status_out, + output [7:0] volume_out, + output volume_latch_out, + output [31:0] addr_out, + output [15:0] track_out, + input [5:0] status_reset_bits, + input [5:0] status_set_bits, + input status_reset_we, + input [13:0] msu_address_ext, + input msu_address_ext_write +); + +reg [2:0] reg_addr_r [3:0]; +always @(posedge clkin) begin + reg_addr_r[3] <= reg_addr_r[2]; + reg_addr_r[2] <= reg_addr_r[1]; + reg_addr_r[1] <= reg_addr_r[0]; + reg_addr_r[0] <= reg_addr; +end + + +reg [1:0] status_reset_we_r; +always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we}; +wire status_reset_en = (status_reset_we_r == 2'b01); + +reg [13:0] msu_address_r; +wire [13:0] msu_address = msu_address_r; + +wire [7:0] msu_data; + +reg [1:0] msu_address_ext_write_sreg; +always @(posedge clkin) + msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[0], msu_address_ext_write}; +wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[1:0] == 2'b01); + +reg [4:0] reg_enable_sreg; +initial reg_enable_sreg = 5'b11111; +always @(posedge clkin) reg_enable_sreg <= {reg_enable_sreg[3:0], enable}; + +reg [5:0] reg_oe_sreg; +always @(posedge clkin) reg_oe_sreg <= {reg_oe_sreg[4:0], reg_oe}; +wire reg_oe_rising = reg_enable_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001); + +reg [5:0] reg_we_sreg; +always @(posedge clkin) reg_we_sreg <= {reg_we_sreg[4:0], reg_we}; +wire reg_we_rising = reg_enable_sreg[4] && (reg_we_sreg[5:0] == 6'b000001); + +reg [31:0] addr_out_r; +assign addr_out = addr_out_r; + +reg [15:0] track_out_r; +assign track_out = track_out_r; + +reg [7:0] volume_r; +assign volume_out = volume_r; + +reg volume_start_r; +assign volume_latch_out = volume_start_r; + +reg audio_start_r; +reg audio_busy_r; +reg data_start_r; +reg data_busy_r; +reg ctrl_start_r; +reg [1:0] audio_ctrl_r; +reg [1:0] audio_status_r; + +initial begin + audio_busy_r <= 1'b1; + data_busy_r <= 1'b1; +end + +assign status_out = {msu_address_r[13], // 6 + audio_start_r, // 5 + data_start_r, // 4 + volume_start_r, // 3 + audio_ctrl_r, // 2:1 + ctrl_start_r}; // 0 + +initial msu_address_r = 14'h1234; + +msu_databuf snes_msu_databuf ( + .clka(clkin), + .wea(~pgm_we), // Bus [0 : 0] + .addra(pgm_address), // Bus [13 : 0] + .dina(pgm_data), // Bus [7 : 0] + .clkb(clkin), + .addrb(msu_address), // Bus [13 : 0] + .doutb(msu_data) +); // Bus [7 : 0] + +reg [7:0] data_out_r; +assign reg_data_out = data_out_r; + +always @(posedge clkin) begin + case(reg_addr_r[3]) + 3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, 4'b0001}; + 3'h1: data_out_r <= msu_data; + 3'h2: data_out_r <= 8'h53; + 3'h3: data_out_r <= 8'h2d; + 3'h4: data_out_r <= 8'h4d; + 3'h5: data_out_r <= 8'h53; + 3'h6: data_out_r <= 8'h55; + 3'h7: data_out_r <= 8'h31; + endcase +end + +always @(posedge clkin) begin + if(reg_we_rising) begin + case(reg_addr_r[3]) + 3'h0: addr_out_r[7:0] <= reg_data_in; + 3'h1: addr_out_r[15:8] <= reg_data_in; + 3'h2: addr_out_r[23:16] <= reg_data_in; + 3'h3: begin + addr_out_r[31:24] <= reg_data_in; + data_start_r <= 1'b1; + data_busy_r <= 1'b1; + end + 3'h4: begin + track_out_r[7:0] <= reg_data_in; + end + 3'h5: begin + track_out_r[15:8] <= reg_data_in; + audio_start_r <= 1'b1; + audio_busy_r <= 1'b1; + end + 3'h6: begin + volume_r <= reg_data_in; + volume_start_r <= 1'b1; + end + 3'h7: begin + if(!audio_busy_r) begin + audio_ctrl_r <= reg_data_in[1:0]; + ctrl_start_r <= 1'b1; + end + end + endcase + end else if (status_reset_en) begin + audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5]; + if(status_reset_bits[5]) audio_start_r <= 1'b0; + + data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4]; + if(status_reset_bits[4]) data_start_r <= 1'b0; + +// volume_start_r <= (volume_start_r | status_set_bits[3]) & ~status_reset_bits[3]; + + audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1]; + + ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0]; + end else begin + volume_start_r <= 1'b0; + end +end + +always @(posedge clkin) begin + if(msu_address_ext_write_rising) + msu_address_r <= msu_address_ext; + else if(reg_addr_r[3] == 3'h1 && reg_oe_rising) begin + msu_address_r <= msu_address_r + 1; + end +end + +endmodule diff --git a/verilog/sd2snes_cx4/sd2snes_cx4.xise b/verilog/sd2snes_cx4/sd2snes_cx4.xise new file mode 100644 index 0000000..0c67fd3 --- /dev/null +++ b/verilog/sd2snes_cx4/sd2snes_cx4.xise @@ -0,0 +1,456 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/sd2snes_cx4/sd_dma.v b/verilog/sd2snes_cx4/sd_dma.v new file mode 100644 index 0000000..0d7d2c8 --- /dev/null +++ b/verilog/sd2snes_cx4/sd_dma.v @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 19:19:08 12/01/2010 +// Design Name: +// Module Name: sd_dma +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module sd_dma( + input [3:0] SD_DAT, + inout SD_CLK, + input CLK, + input SD_DMA_EN, + output SD_DMA_STATUS, + output SD_DMA_SRAM_WE, + output SD_DMA_NEXTADDR, + output [7:0] SD_DMA_SRAM_DATA, + input SD_DMA_PARTIAL, + input [10:0] SD_DMA_PARTIAL_START, + input [10:0] SD_DMA_PARTIAL_END +); + +reg [10:0] SD_DMA_STARTr; +reg [10:0] SD_DMA_ENDr; +reg SD_DMA_PARTIALr; +always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL; + +reg SD_DMA_DONEr; +reg[1:0] SD_DMA_DONEr2; +initial begin + SD_DMA_DONEr2 = 2'b00; + SD_DMA_DONEr = 1'b0; +end +always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr}; +wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01); + +reg [1:0] SD_DMA_ENr; +initial SD_DMA_ENr = 2'b00; +always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN}; +wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01); + +reg SD_DMA_STATUSr; +assign SD_DMA_STATUS = SD_DMA_STATUSr; + +// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit) +reg [10:0] cyclecnt; +initial cyclecnt = 11'd0; + +reg SD_DMA_SRAM_WEr; +initial SD_DMA_SRAM_WEr = 1'b1; +assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1; + +reg SD_DMA_NEXTADDRr; +assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0; + +reg[7:0] SD_DMA_SRAM_DATAr; +assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr; + +// we have 4 internal cycles per SD clock, 8 per RAM byte write +reg [2:0] clkcnt; +initial clkcnt = 3'b000; +reg SD_CLKr; +always @(posedge CLK) SD_CLKr <= clkcnt[1]; +assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr : 1'bZ; + +always @(posedge CLK) begin + if(SD_DMA_EN_rising) begin + SD_DMA_STATUSr <= 1'b1; + SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0); + SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024); + end + else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0; +end + +always @(posedge CLK) begin + if(cyclecnt == 1042) SD_DMA_DONEr <= 1; + else SD_DMA_DONEr <= 0; +end + +always @(posedge CLK) begin + if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin + clkcnt <= 0; + end else begin + if(SD_DMA_STATUSr) begin + clkcnt <= clkcnt + 1; + end + end +end + +always @(posedge CLK) begin + if(SD_DMA_EN_rising || !SD_DMA_STATUSr) cyclecnt <= 0; + else if(clkcnt[1:0] == 2'b11) cyclecnt <= cyclecnt + 1; +end + +// we have 8 clk cycles to complete one RAM write +// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte) +always @(posedge CLK) begin + if(SD_DMA_STATUSr) begin + case(clkcnt[2:0]) + 3'h0: begin + SD_DMA_SRAM_WEr <= 1'b1; + SD_DMA_SRAM_DATAr[7:4] <= SD_DAT; + if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1; + end + 3'h1: + SD_DMA_NEXTADDRr <= 1'b0; +// 3'h2: + 3'h3: + if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0; + 3'h4: + SD_DMA_SRAM_DATAr[3:0] <= SD_DAT; +// 3'h5: +// 3'h6: +// 3'h7: + endcase + end +end + +endmodule + diff --git a/verilog/sd2snes_cx4/spi.v b/verilog/sd2snes_cx4/spi.v new file mode 100644 index 0000000..cb6bf79 --- /dev/null +++ b/verilog/sd2snes_cx4/spi.v @@ -0,0 +1,113 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 21:16:09 07/10/2009 +// Design Name: +// Module Name: spi +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// + +////////////////////////////////////////////////////////////////////////////////// +module spi( + input clk, + input SCK, + input MOSI, + inout MISO, + input SSEL, + output cmd_ready, + output param_ready, + output [7:0] cmd_data, + output [7:0] param_data, + output endmessage, + output startmessage, + input [7:0] input_data, + output [31:0] byte_cnt, + output [2:0] bit_cnt +); + +reg [7:0] cmd_data_r; +reg [7:0] param_data_r; + +reg [1:0] SSELr; always @(posedge clk) SSELr <= {SSELr[0], SSEL}; +wire SSEL_active = ~SSELr[1]; // SSEL is active low +wire SSEL_startmessage = (SSELr[1:0]==2'b10); // message starts at falling edge +wire SSEL_endmessage = (SSELr[1:0]==2'b01); // message stops at rising edge +assign endmessage = SSEL_endmessage; +assign startmessage = SSEL_startmessage; + +// bit count for one SPI byte + byte count for the message +reg [2:0] bitcnt; +reg [31:0] byte_cnt_r; + +reg byte_received; // high when a byte has been received +reg [7:0] byte_data_received; + +assign bit_cnt = bitcnt; + +always @(posedge SCK) begin + if(SSEL) bitcnt <= 3'b000; + else begin + bitcnt <= bitcnt + 3'b001; + byte_data_received <= {byte_data_received[6:0], MOSI}; + end + if(~SSEL && bitcnt==3'b111) byte_received <= 1'b1; + else byte_received <= 1'b0; +end + +reg [1:0] byte_received_r; +always @(posedge clk) byte_received_r <= {byte_received_r[0], byte_received}; +wire byte_received_sync = (byte_received_r == 2'b01); + +always @(posedge clk) begin + if(~SSEL_active) + byte_cnt_r <= 16'h0000; + else if(byte_received_sync) begin + byte_cnt_r <= byte_cnt_r + 16'h0001; + end +end + +reg [7:0] byte_data_sent; + +assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first + +reg cmd_ready_r; +reg param_ready_r; +reg cmd_ready_r2; +reg param_ready_r2; +assign cmd_ready = cmd_ready_r; +assign param_ready = param_ready_r; +assign cmd_data = cmd_data_r; +assign param_data = param_data_r; +assign byte_cnt = byte_cnt_r; + +always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0; +always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0; + +// fill registers +always @(posedge clk) begin + if (SSEL_startmessage) + cmd_data_r <= 8'h00; + else if(cmd_ready_r2) + cmd_data_r <= byte_data_received; + else if(param_ready_r2) + param_data_r <= byte_data_received; +end + +// delay ready signals by one clock +always @(posedge clk) begin + cmd_ready_r <= cmd_ready_r2; + param_ready_r <= param_ready_r2; +end + +endmodule