Rev.B; dir structure
This commit is contained in:
parent
677233c0d7
commit
e999d052f0
@ -79,12 +79,8 @@ hdma_math_src .byt 1
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.byt $00, $e0
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.byt $00, $e0
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.byt 1
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.byt 1
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.byt $00, $e0
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.byt $00, $e0
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.byt 1
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.byt 10
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.byt $60, $bf
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.byt $20, $f0
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.byt 8
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.byt $60, $b0
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.byt 1
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.byt $60, $bf
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.byt 1
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.byt 1
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.byt $00, $e0
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.byt $00, $e0
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.byt 0
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.byt 0
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@ -35,9 +35,24 @@ dma_len .word 0
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dma_mode .byt 0
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dma_mode .byt 0
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;----------state information----------
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;----------state information----------
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bar_pos .byt 0 ; y position of select bar
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bar_xl .byt 0 ; logical x position of select bar
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bar_yl .byt 0 ; logical y position of select bar
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bar_x .byt 0 ; pixel x position of select bar
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bar_y .byt 0 ; pixel y position of select bar
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bar_w .byt 0 ; bar width
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fd_addr .word 0 ; address of current "file descriptor"
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fd_bank .byt 0 ; bank of current "file descriptor"
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file_path ; assembled current path
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.word 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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;----------hdma values in RAM
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;----------hdma tables in WRAM (must be stable when cartridge is cut off)
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hdma_pal .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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hdma_pal .byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.byt 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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@ -35,7 +35,7 @@ CONFIG_UART_BAUDRATE=38400
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CONFIG_UART_BUF_SHIFT=7
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CONFIG_UART_BUF_SHIFT=7
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CONFIG_HARDWARE_NAME=sd2snes
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CONFIG_HARDWARE_NAME=sd2snes
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CONFIG_SD_AUTO_RETRIES=10
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CONFIG_SD_AUTO_RETRIES=10
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CONFIG_SD_DATACRC=y
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#CONFIG_SD_DATACRC=y
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CONFIG_EEPROM_SIZE=512
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CONFIG_EEPROM_SIZE=512
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CONFIG_EEPROM_OFFSET=512
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CONFIG_EEPROM_OFFSET=512
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CONFIG_MAX_PARTITIONS=1
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CONFIG_MAX_PARTITIONS=1
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176
src/filetypes.c
176
src/filetypes.c
@ -13,84 +13,144 @@
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#include "crc16.h"
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#include "crc16.h"
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#include "memory.h"
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#include "memory.h"
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uint16_t scan_flat(const char* path) {
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DIR dir;
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FRESULT res;
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FILINFO fno;
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fno.lfn = NULL;
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res = f_opendir(&dir, (unsigned char*)path);
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uint16_t numentries = 0;
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if (res == FR_OK) {
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for (;;) {
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res = f_readdir(&dir, &fno);
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if(res != FR_OK || fno.fname[0] == 0)break;
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numentries++;
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}
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}
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return numentries;
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}
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uint16_t scan_dir(char* path, char mkdb) {
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uint16_t scan_dir(char* path, char mkdb) {
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DIR dir;
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DIR dir;
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FILINFO fno;
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FILINFO fno;
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FRESULT res;
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FRESULT res;
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int len;
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int len;
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unsigned char* fn;
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unsigned char* fn;
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static unsigned char lfn[256];
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static unsigned char lfn[256];
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static unsigned char depth = 0;
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static unsigned char depth = 0;
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static uint16_t crc;
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static uint16_t crc;
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static uint32_t db_tgt;
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static uint32_t db_tgt;
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static uint32_t dir_tgt;
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uint32_t dir_tgt_save, dir_tgt_next;
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uint16_t numentries;
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uint32_t dirsize;
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uint8_t pass = 0;
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if(depth==0) {
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if(depth==0) {
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crc = 0;
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crc = 0;
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db_tgt = SRAM_WORK_ADDR+0x10;
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db_tgt = SRAM_WORK_ADDR+0x200;
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dir_tgt = SRAM_WORK_ADDR+0x100000;
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dprintf("root dir @%lx\n", dir_tgt);
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}
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}
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// dprintf("path=%s depth=%d ptr=%lx\n", path, depth, db_tgt);
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// _delay_ms(50);
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fno.lfn = lfn;
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fno.lfn = lfn;
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res = f_opendir(&dir, (unsigned char*)path);
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numentries=0;
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if (res == FR_OK) {
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for(pass = 0; pass < 2; pass++) {
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len = strlen((char*)path);
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if(pass) {
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for (;;) {
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dprintf("path=%s depth=%d ptr=%lx entries=%d next subdir @%lx\n", path, depth, db_tgt, numentries, numentries*4+dir_tgt);
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res = f_readdir(&dir, &fno);
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_delay_ms(50);
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if (res != FR_OK || fno.fname[0] == 0) break;
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}
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fn = *fno.lfn ? fno.lfn : fno.fname;
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dirsize = 4*(numentries+1);
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// dprintf("%s\n", fn);
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dir_tgt_next = dir_tgt + dirsize;
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// _delay_ms(100);
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res = f_opendir(&dir, (unsigned char*)path);
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if (*fn == '.') continue;
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if (res == FR_OK) {
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if (fno.fattrib & AM_DIR) {
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len = strlen((char*)path);
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path[len]='/';
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for (;;) {
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strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
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res = f_readdir(&dir, &fno);
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depth++;
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if (res != FR_OK || fno.fname[0] == 0) break;
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scan_dir(path, mkdb);
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fn = *fno.lfn ? fno.lfn : fno.fname;
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depth--;
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// dprintf("%s\n", fn);
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path[len]=0;
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// _delay_ms(100);
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// if (res != FR_OK) {
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if (*fn == '.') continue;
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// break;
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if (fno.fattrib & AM_DIR) {
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// }
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numentries++;
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} else {
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if(pass) {
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SNES_FTYPE type = determine_filetype((char*)fn);
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if(type != TYPE_UNKNOWN) {
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if(mkdb) {
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snes_romprops_t romprops;
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path[len]='/';
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path[len]='/';
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strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
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strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
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switch(type) {
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depth++;
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case TYPE_SMC:
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dir_tgt_save = dir_tgt;
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file_open_by_filinfo(&fno);
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dir_tgt = dir_tgt_next;
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if(file_res){
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if(mkdb) {
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dprintf("ZOMG NOOOO %d\n", file_res);
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// write element pointer to current dir structure
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_delay_ms(30);
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dprintf("d=%d Saving %lX to Address %lX [dir]\n", depth, db_tgt, dir_tgt_save);
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}
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_delay_ms(50);
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smc_id(&romprops);
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sram_writeblock((uint8_t*)&db_tgt, dir_tgt_save, sizeof(dir_tgt_save));
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file_close();
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dprintf("%lx\n", db_tgt);
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// save element:
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// _delay_ms(30);
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// - path name
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sram_writeblock((uint8_t*)&romprops, db_tgt, sizeof(romprops));
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// - pointer to sub dir structure
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sram_writeblock(path, db_tgt + sizeof(romprops), 256);
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sram_writeblock(path, db_tgt, 256);
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db_tgt += 0x140;
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sram_writeblock((uint8_t*)&dir_tgt, db_tgt+256, sizeof(dir_tgt));
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break;
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db_tgt += 0x200;
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case TYPE_UNKNOWN:
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default:
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break;
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}
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}
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scan_dir(path, mkdb);
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dir_tgt = dir_tgt_save;
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dir_tgt += 4;
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depth--;
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path[len]=0;
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path[len]=0;
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// dprintf("%s ", path);
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// _delay_ms(30);
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}
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}
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unsigned char* sfn = fno.fname;
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} else {
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while(*sfn != 0) {
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SNES_FTYPE type = determine_filetype((char*)fn);
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crc += crc16_update(crc, sfn++, 1);
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if(type != TYPE_UNKNOWN) {
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numentries++;
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if(pass) {
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if(mkdb) {
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snes_romprops_t romprops;
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path[len]='/';
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strncpy(path+len+1, (char*)fn, sizeof(fs_path)-len);
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switch(type) {
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case TYPE_SMC:
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file_open_by_filinfo(&fno);
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if(file_res){
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dprintf("ZOMG NOOOO %d\n", file_res);
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_delay_ms(30);
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}
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smc_id(&romprops);
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file_close();
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// _delay_ms(30);
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// write element pointer to current dir structure
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dprintf("d=%d Saving %lX to Address %lX [file]\n", depth, db_tgt, dir_tgt);
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_delay_ms(50);
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sram_writeblock((uint8_t*)&db_tgt, dir_tgt, sizeof(db_tgt));
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dir_tgt += 4;
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// save element:
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// - SNES header information
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// - file name
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sram_writeblock((uint8_t*)&romprops, db_tgt, sizeof(romprops));
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sram_writeblock(path, db_tgt + sizeof(romprops), 256);
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db_tgt += 0x200;
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break;
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case TYPE_UNKNOWN:
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default:
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break;
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}
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path[len]=0;
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// dprintf("%s ", path);
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// _delay_ms(30);
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}
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} else {
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unsigned char* sfn = fno.fname;
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while(*sfn != 0) {
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crc += crc16_update(crc, sfn++, 1);
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}
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}
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}
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}
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// dprintf("%s/%s\n", path, fn);
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// _delay_ms(50);
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}
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}
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// dprintf("%s/%s\n", path, fn);
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}
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// _delay_ms(50);
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} else uart_putc(0x30+res);
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// _delay_ms(10);
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}
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}
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}
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} else uart_putc(0x30+res);
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// dprintf("%x\n", crc);
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// dprintf("%x\n", crc);
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// _delay_ms(50);
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// _delay_ms(50);
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sram_writeblock(&db_tgt, SRAM_WORK_ADDR+4, sizeof(db_tgt));
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sram_writeblock(&db_tgt, SRAM_WORK_ADDR+4, sizeof(db_tgt));
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90
src/fpga.c
90
src/fpga.c
@ -6,27 +6,6 @@
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FPGA pin mapping
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FPGA pin mapping
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================
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================
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PSM:
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====
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FPGA AVR dir
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------------------------
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PROG_B PD3 OUT
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CCLK PD4 OUT
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CS_B PD7 OUT
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INIT_B PB2 IN
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RDWR_B PB3 OUT
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D7 PC0 OUT
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D6 PC1 OUT
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D5 PC2 OUT
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D4 PC3 OUT
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D3 PC4 OUT
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D2 PC5 OUT
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D1 PC6 OUT
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D0 PC7 OUT
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SSM:
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====
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PROG_B PD3 OUT
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PROG_B PD3 OUT
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CCLK PD4 OUT
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CCLK PD4 OUT
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INIT_B PD7 IN
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INIT_B PD7 IN
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@ -59,22 +38,6 @@ void set_prog_b(uint8_t val) {
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}
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}
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}
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}
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void set_cs_b(uint8_t val) {
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if(val) {
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PORTD |= _BV(PD7);
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} else {
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PORTD &= ~_BV(PD7);
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}
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}
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void set_rdwr_b(uint8_t val) {
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if(val) {
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PORTB |= _BV(PB3);
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} else {
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PORTB &= ~_BV(PB3);
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}
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}
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void set_cclk(uint8_t val) {
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void set_cclk(uint8_t val) {
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if(val) {
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if(val) {
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PORTD |= _BV(PD4);
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PORTD |= _BV(PD4);
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@ -84,8 +47,6 @@ void set_cclk(uint8_t val) {
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}
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}
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void fpga_init() {
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void fpga_init() {
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DDRB |= _BV(PB3); // PB3 is output
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DDRD &= ~_BV(PD7); // PD7 is input
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DDRD &= ~_BV(PD7); // PD7 is input
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DDRC = _BV(PC7); // for FPGA config, PC7 is output
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DDRC = _BV(PC7); // for FPGA config, PC7 is output
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@ -108,7 +69,7 @@ void fpga_postinit() {
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void fpga_pgm(char* filename) {
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void fpga_pgm(char* filename) {
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int MAXRETRIES = 10;
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int MAXRETRIES = 10;
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// int retries = MAXRETRIES;
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int retries = MAXRETRIES;
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do {
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do {
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set_prog_b(0);
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set_prog_b(0);
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uart_putc('P');
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uart_putc('P');
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@ -125,9 +86,6 @@ void fpga_pgm(char* filename) {
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uart_putc(0x30+file_res);
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uart_putc(0x30+file_res);
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return;
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return;
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}
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}
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// file open successful
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set_cs_b(0);
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set_rdwr_b(0);
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for (;;) {
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for (;;) {
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bytes_read = file_read();
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bytes_read = file_read();
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@ -138,7 +96,7 @@ void fpga_pgm(char* filename) {
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}
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}
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file_close();
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file_close();
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_delay_ms(10);
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_delay_ms(10);
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} while (0); //(!fpga_get_done() && retries--);
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} while (!fpga_get_done() && retries--);
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if(!fpga_get_done()) {
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if(!fpga_get_done()) {
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dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
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dprintf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
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_delay_ms(50);
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_delay_ms(50);
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@ -146,22 +104,6 @@ void fpga_pgm(char* filename) {
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fpga_postinit();
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fpga_postinit();
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}
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}
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void set_avr_read(uint8_t val) {
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if(val) {
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PORTB |= _BV(PB3);
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} else {
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PORTB &= ~_BV(PB3);
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}
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}
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void set_avr_write(uint8_t val) {
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if(val) {
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PORTB |= _BV(PB2);
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||||||
} else {
|
|
||||||
PORTB &= ~_BV(PB2);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void set_avr_ena(uint8_t val) {
|
void set_avr_ena(uint8_t val) {
|
||||||
if(val) {
|
if(val) {
|
||||||
PORTD |= _BV(PD7);
|
PORTD |= _BV(PD7);
|
||||||
@ -170,34 +112,6 @@ void set_avr_ena(uint8_t val) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void set_avr_nextaddr(uint8_t val) {
|
|
||||||
if(val) {
|
|
||||||
PORTA |= _BV(PA4);
|
|
||||||
} else {
|
|
||||||
PORTA &= ~_BV(PA4);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void set_avr_addr_reset(uint8_t val) {
|
|
||||||
if(val) {
|
|
||||||
PORTA |= _BV(PA5);
|
|
||||||
} else {
|
|
||||||
PORTA &= ~_BV(PA5);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void set_avr_data(uint8_t data) {
|
|
||||||
PORTC = data;
|
|
||||||
}
|
|
||||||
|
|
||||||
void set_avr_addr_en(uint8_t val) {
|
|
||||||
if(val) {
|
|
||||||
PORTA |= _BV(PA6);
|
|
||||||
} else {
|
|
||||||
PORTA &= ~_BV(PA6);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void set_avr_mapper(uint8_t val) {
|
void set_avr_mapper(uint8_t val) {
|
||||||
SPI_SS_HIGH();
|
SPI_SS_HIGH();
|
||||||
FPGA_SS_LOW();
|
FPGA_SS_LOW();
|
||||||
|
|||||||
@ -127,11 +127,12 @@ int main(void) {
|
|||||||
#ifdef CLOCK_PRESCALE
|
#ifdef CLOCK_PRESCALE
|
||||||
clock_prescale_set(CLOCK_PRESCALE);
|
clock_prescale_set(CLOCK_PRESCALE);
|
||||||
#endif
|
#endif
|
||||||
|
set_pwr_led(0);
|
||||||
|
set_busy_led(1);
|
||||||
spi_none();
|
spi_none();
|
||||||
snes_reset(1);
|
snes_reset(1);
|
||||||
uart_init();
|
uart_init();
|
||||||
sei(); // suspected to reset the AVR when inserting an SD card
|
sei(); // suspected to reset the AVR when inserting an SD card
|
||||||
set_busy_led(0);
|
|
||||||
_delay_ms(100);
|
_delay_ms(100);
|
||||||
disk_init();
|
disk_init();
|
||||||
snes_init();
|
snes_init();
|
||||||
@ -158,7 +159,7 @@ int main(void) {
|
|||||||
dprintf("curr dir id = %x\n", curr_dir_id);
|
dprintf("curr dir id = %x\n", curr_dir_id);
|
||||||
uint16_t saved_dir_id;
|
uint16_t saved_dir_id;
|
||||||
if((get_db_id(&saved_dir_id) != FR_OK) // no database?
|
if((get_db_id(&saved_dir_id) != FR_OK) // no database?
|
||||||
|| saved_dir_id != curr_dir_id) { // files changed?
|
|| 1 /*saved_dir_id != curr_dir_id*/) { // files changed? // XXX
|
||||||
dprintf("saved dir id = %x\n", saved_dir_id);
|
dprintf("saved dir id = %x\n", saved_dir_id);
|
||||||
_delay_ms(50);
|
_delay_ms(50);
|
||||||
dprintf("rebuilding database...");
|
dprintf("rebuilding database...");
|
||||||
|
|||||||
@ -73,7 +73,7 @@
|
|||||||
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
|
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
|
||||||
<property xil_pn:name="Device" xil_pn:value="xc3s200"/>
|
<property xil_pn:name="Device" xil_pn:value="xc3s200"/>
|
||||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
|
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
|
||||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true"/>
|
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true"/>
|
||||||
<property xil_pn:name="Extra Effort" xil_pn:value="Normal"/>
|
<property xil_pn:name="Extra Effort" xil_pn:value="Normal"/>
|
||||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/>
|
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal"/>
|
||||||
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
|
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user