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FPGA: add RAM1 pinout to user constraints

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ikari 2012-01-14 01:21:40 +01:00
parent 5a3e935a3e
commit eefcc712ca
1 changed files with 92 additions and 0 deletions
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92
verilog/sd2snes/main.ucf
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@ -543,3 +543,95 @@ NET "SD_DAT[3]" IOSTANDARD = LVCMOS33;
NET "SNES_SYSCLK" LOC = P180; NET "SNES_SYSCLK" LOC = P180;
NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33; NET "SNES_SYSCLK" IOSTANDARD = LVCMOS33;
NET "SNES_SYSCLK" TNM_NET = "SNES_SYSCLK";
TIMESPEC TS_SNES_SYSCLK = PERIOD "SNES_SYSCLK" 21.5 MHz HIGH 50 %;
#NET "RAM_DATA[0]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[0]" DRIVE = 8;
#NET "RAM_DATA[0]" LOC = P26;
#NET "RAM_DATA[1]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[1]" DRIVE = 8;
#NET "RAM_DATA[1]" LOC = P22;
#NET "RAM_DATA[2]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[2]" DRIVE = 8;
#NET "RAM_DATA[2]" LOC = P20;
#NET "RAM_DATA[3]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[3]" DRIVE = 8;
#NET "RAM_DATA[3]" LOC = P19;
#NET "RAM_DATA[4]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[4]" DRIVE = 8;
#NET "RAM_DATA[4]" LOC = P21;
#NET "RAM_DATA[5]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[5]" DRIVE = 8;
#NET "RAM_DATA[5]" LOC = P24;
#NET "RAM_DATA[6]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[6]" DRIVE = 8;
#NET "RAM_DATA[6]" LOC = P27;
#NET "RAM_DATA[7]" IOSTANDARD = LVCMOS33;
#NET "RAM_DATA[7]" DRIVE = 8;
#NET "RAM_DATA[7]" LOC = P29;
#
#NET "RAM_OE" IOSTANDARD = LVCMOS33;
#NET "RAM_OE" DRIVE = 8;
#NET "RAM_OE" LOC = P36;
#NET "RAM_WE" IOSTANDARD = LVCMOS33;
#NET "RAM_WE" DRIVE = 8;
#NET "RAM_WE" LOC = P50;
#
#NET "RAM_ADDR[0]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[0]" DRIVE = 8;
#NET "RAM_ADDR[0]" LOC = P28;
#NET "RAM_ADDR[1]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[1]" DRIVE = 8;
#NET "RAM_ADDR[1]" LOC = P31;
#NET "RAM_ADDR[2]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[2]" DRIVE = 8;
#NET "RAM_ADDR[2]" LOC = P33;
#NET "RAM_ADDR[3]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[3]" DRIVE = 8;
#NET "RAM_ADDR[3]" LOC = P35;
#NET "RAM_ADDR[4]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[4]" DRIVE = 8;
#NET "RAM_ADDR[4]" LOC = P37;
#NET "RAM_ADDR[5]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[5]" DRIVE = 8;
#NET "RAM_ADDR[5]" LOC = P40;
#NET "RAM_ADDR[6]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[6]" DRIVE = 8;
#NET "RAM_ADDR[6]" LOC = P43;
#NET "RAM_ADDR[7]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[7]" DRIVE = 8;
#NET "RAM_ADDR[7]" LOC = P45;
#NET "RAM_ADDR[8]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[8]" DRIVE = 8;
#NET "RAM_ADDR[8]" LOC = P44;
#NET "RAM_ADDR[9]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[9]" DRIVE = 8;
#NET "RAM_ADDR[9]" LOC = P42;
#NET "RAM_ADDR[10]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[10]" DRIVE = 8;
#NET "RAM_ADDR[10]" LOC = P34;
#NET "RAM_ADDR[11]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[11]" DRIVE = 8;
#NET "RAM_ADDR[11]" LOC = P39;
#NET "RAM_ADDR[12]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[12]" DRIVE = 8;
#NET "RAM_ADDR[12]" LOC = P48;
#NET "RAM_ADDR[13]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[13]" DRIVE = 8;
#NET "RAM_ADDR[13]" LOC = P46;
#NET "RAM_ADDR[14]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[14]" DRIVE = 8;
#NET "RAM_ADDR[14]" LOC = P51;
#NET "RAM_ADDR[15]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[15]" DRIVE = 8;
#NET "RAM_ADDR[15]" LOC = P58;
#NET "RAM_ADDR[16]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[16]" DRIVE = 8;
#NET "RAM_ADDR[16]" LOC = P57;
#NET "RAM_ADDR[17]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[17]" DRIVE = 8;
#NET "RAM_ADDR[17]" LOC = P61;
#NET "RAM_ADDR[18]" IOSTANDARD = LVCMOS33;
#NET "RAM_ADDR[18]" DRIVE = 8;
#NET "RAM_ADDR[18]" LOC = P52;