diff --git a/pcb/cart/sd2snes19.sch b/pcb/cart/sd2snes19.sch
index e3a9bf3..37ef349 100644
Binary files a/pcb/cart/sd2snes19.sch and b/pcb/cart/sd2snes19.sch differ
diff --git a/pcb/cart/sd2snes20.brd b/pcb/cart/sd2snes20.brd
new file mode 100644
index 0000000..6deda64
Binary files /dev/null and b/pcb/cart/sd2snes20.brd differ
diff --git a/pcb/cart/sd2snes20.sch b/pcb/cart/sd2snes20.sch
new file mode 100644
index 0000000..afdbc1d
Binary files /dev/null and b/pcb/cart/sd2snes20.sch differ
diff --git a/pcb/vfbga48breakout.brd b/pcb/vfbga48breakout.brd
new file mode 100644
index 0000000..03ed412
Binary files /dev/null and b/pcb/vfbga48breakout.brd differ
diff --git a/pcb/vfbga48breakout.sch b/pcb/vfbga48breakout.sch
new file mode 100644
index 0000000..2c3147d
Binary files /dev/null and b/pcb/vfbga48breakout.sch differ
diff --git a/snes/header.a65 b/snes/header.a65
index f3c93b9..72f2d6d 100644
--- a/snes/header.a65
+++ b/snes/header.a65
@@ -33,7 +33,7 @@ BRK_8bit: BRK_16bit:
 COP_8bit: COP_16bit:
 IRQ_8bit:
 NMI_8bit:
-        - lda $ABCDEF : bra -
+        - wai: lda $ABCDEF : bra -
 
 *= $C0FFB0
         ; Zero the area from $FFB0 - $FFFF
diff --git a/snes/main.a65 b/snes/main.a65
index 4da8453..0952e76 100644
--- a/snes/main.a65
+++ b/snes/main.a65
@@ -2,6 +2,9 @@
 #include "dma.i65"
 
 GAME_MAIN:
+	sep #$20 : .as
+	lda #$01
+	sta $420d ; fast cpu
 	sep #$20 : .as
 	jsr snes_init
 	jsr setup_gfx
@@ -17,6 +20,16 @@ GAME_MAIN:
 	sta @AVR_PARAM+2
 	jsr menu_init
 	sep #$20 : .as
+	sep #$20 : .as
+-	lda @$C00000
+	lda @$D00000
+	lda @$E00000
+	lda @$F00000
+	lda @$400000
+	lda @$500000
+	lda @$600000
+	lda @$700000
+;	bra -
 	jsr menuloop
 	cli
 	stz $4200
diff --git a/snes/pad.a65 b/snes/pad.a65
index 672b9c8..e254ea2 100644
--- a/snes/pad.a65
+++ b/snes/pad.a65
@@ -13,11 +13,13 @@ read_pad1_cont1
 	eor pad1mem
 	and pad1mem
 	sta pad1trig
-	lda #$0010
+	lda #$0001
+;	lda #$0010
 	cmp pad1delay
 	bne read_pad1_cont2
 	stz pad1mem
-	lda #$000d
+	lda #$0000
+;	lda #$000d
 	sta pad1delay
 read_pad1_cont2
 ;lda $4218
diff --git a/src/main.c b/src/main.c
index 07df1c4..cbfae76 100644
--- a/src/main.c
+++ b/src/main.c
@@ -264,7 +264,7 @@ restart:
 	uart_putc('(');
 	load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR);
 	set_rom_mask(0x3fffff); // force mirroring off
-	set_avr_mapper(0x7); // menu mapper
+ 	set_avr_mapper(0x7); // menu mapper XXX
 	uart_putc(')');
 	uart_putcrlf();
 //	sram_hexdump(0x7ffff0, 0x10);
@@ -279,8 +279,17 @@ restart:
 	_delay_ms(100);
 	uart_puts_P(PSTR("SNES GO!\r\n"));
 	snes_reset(0);
-
-
+// writetest();
+// XXX
+	uart_putc(uart_getc());
+/*	snes_reset(1);
+	set_avr_ena(0);
+	led_std();
+	set_busy_led(1);
+	save_sram((uint8_t*)"/sd2snes/dump", 65536, SRAM_MENU_ADDR);
+	set_busy_led(0);
+	set_avr_ena(1);
+	snes_reset(0); */
 	uint8_t cmd = 0;
 
 	while(!sram_reliable());
diff --git a/verilog/sd2snes/main.ucf b/verilog/sd2snes/main.ucf
index d943775..c0d5d59 100644
--- a/verilog/sd2snes/main.ucf
+++ b/verilog/sd2snes/main.ucf
@@ -192,3 +192,13 @@ NET "SPI_DMA_CTRL" PULLUP;
 NET "SPI_SCK" IOSTANDARD = LVCMOS33;
 NET "SPI_SCK" DRIVE = 16;
 NET "SPI_SCK" PULLUP;
+NET "DBG_P44" LOC = P44;
+NET "DBG_P44" IOSTANDARD = LVCMOS33;
+NET "DBG_P46" LOC = P46;
+NET "DBG_P46" IOSTANDARD = LVCMOS33;
+NET "DBG_P47" LOC = P47;
+NET "DBG_P47" IOSTANDARD = LVCMOS33;
+NET "DBG_P52" LOC = P52;
+NET "DBG_P52" IOSTANDARD = LVCMOS33;
+NET "DBG_P53" LOC = P53;
+NET "DBG_P53" IOSTANDARD = LVCMOS33;
diff --git a/verilog/sd2snes/main.v b/verilog/sd2snes/main.v
index 107bf4e..20a9878 100644
--- a/verilog/sd2snes/main.v
+++ b/verilog/sd2snes/main.v
@@ -56,7 +56,14 @@ module main(
    //output DCM_IN_STOPPED,
    //output DCM_FX_STOPPED
    //input DCM_RST
+   ,
+   output DBG_P44,
+   output DBG_P46,
+   output DBG_P47,
+   output DBG_P52,
+   output DBG_P53
     );
+   
 wire [7:0] spi_cmd_data;
 wire [7:0] spi_param_data;
 wire [7:0] spi_input_data;
@@ -197,7 +204,7 @@ wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
 wire SNES_CSs = (SNES_CSr == 2'b11);
 wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
 wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
-wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000001);
+wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000011); // slight delay, RD/WR comes after CLK
 wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
 wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
 
@@ -326,21 +333,34 @@ initial begin
    SRAM_WE_ARRAY[2'b10] = 13'b1_111111_000000;
    SRAM_WE_ARRAY[2'b11] = 13'b1_111111_111111;
 
-   SRAM_OE_ARRAY[2'b00] = 13'b1_111111_111111;
-   SRAM_OE_ARRAY[2'b01] = 13'b1_111111_000000;
+   SRAM_OE_ARRAY[2'b00] = 13'b0_111111_111111;
+   SRAM_OE_ARRAY[2'b01] = 13'b0_111111_000000;
    SRAM_OE_ARRAY[2'b10] = 13'b0_000000_111111;
    SRAM_OE_ARRAY[2'b11] = 13'b0_000000_000000;
    
-   SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_001000_000000;  // SNES write
-   /* 13'b0001000000000 */
-   SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;  // SNES read
    
-   AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111;  // AVR write
-//   AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b0000000001000;  // AVR write
+   // *************************************************************
+   // enable sequences for data path related operations. These
+   // control when to take a data value from SNES or AVR to the
+   // SRAM bus and vice versa.
+   // *************************************************************
+   // SNES write. Data cannot be latched earlier because data from
+   // the SNES is not valid before ~50ns after falling edge of /WR.
+   // This timing is *just* enough to satisfy SRAM's t_SD (Data Setup to
+   // write end) _and_ SNES's data valid delay.
+   SNES_DATA_TO_MEM_ARRAY[1'b0] = 13'b0_000100_000000;
+   // SNES read. No transfers to SRAM.
+   SNES_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;
 
+   // AVR write. Data is buffered via the SPI module and has to be
+   // used at any given point.
+   AVR_DATA_TO_MEM_ARRAY[1'b0] = 13'b1_111111_111111;  // AVR write
+   // AVR read. No transfers to SRAM.
    AVR_DATA_TO_MEM_ARRAY[1'b1] = 13'b0_000000_000000;  // AVR read
    
+   // SNES write. No transfers from SRAM.
    SRAM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 13'b0_000000_000000;  // SNES write
+   // SNES read. 000001 _should_ work but might get too close to the next edge of CE/BHE/ADDR???
    SRAM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 13'b0_000100_000000;  // SNES read
    /* 13'b0000100000000; */
    
@@ -363,7 +383,7 @@ end
 always @(posedge CLK2) begin
        AVR_READ_CYCLE <= AVR_READ;
        AVR_WRITE_CYCLE <= AVR_WRITE;
-       if (SNES_RW_start) begin
+       if (SNES_cycle_start) begin
            SNES_READ_CYCLE <= SNES_READ;
            SNES_WRITE_CYCLE <= SNES_WRITE;
            STATE <= STATE_0;
@@ -473,11 +493,14 @@ assign SRAM_WE = !AVR_ENA ? AVR_WRITE
 assign SRAM_OE = !AVR_ENA ? AVR_READ 
                           : SRAM_OE_ARRAY[{SNES_WRITE_CYCLE, AVR_WRITE_CYCLE}][STATEIDX];
 
-assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
-assign SRAM_BLE = !SRAM_WE ? !SRAM_ADDR0 : 1'b0;
 
+// This crashes after a couple million instructions under rare
+// circumstances. I don't have the slightest.
 //assign SRAM_BHE = SRAM_ADDR0;
 //assign SRAM_BLE = ~SRAM_ADDR0;
+// This works
+assign SRAM_BHE = !SRAM_WE ? SRAM_ADDR0 : 1'b0;
+assign SRAM_BLE = !SRAM_WE ? ~SRAM_ADDR0 : 1'b0;
 
 // dumb version
 //assign SRAM_OE = !AVR_ENA ? AVR_READ : SNES_READs;
@@ -498,4 +521,15 @@ assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
 assign IRQ_DIR = 1'b0;
 assign SNES_IRQ = 1'bZ;
 
+
+// DEBUG
+
+    assign DBG_P44 = SRAM_DATA[0];
+    assign DBG_P46 = SRAM_DATA[1];
+    assign DBG_P47 = SRAM_DATA[2];
+    assign DBG_P52 = SRAM_OE;
+    assign DBG_P53 = SRAM_DATA_TO_SNES_MEM;
+    //SNES_ADDR==24'hC0F000 || SNES_ADDR==24'h40F000 || SNES_ADDR==24'h80F000 || SNES_ADDR==24'h00F000;
+
+
 endmodule