menu: SPC player (necronomfive, blargg)
This commit is contained in:
Maximilian Rehkopf
parent
c07b8f42c2
commit
f9c8e62f10
@ -1,4 +1,4 @@
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OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 # gfx.o65 # vars.o65
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OBJS = header.ips reset.o65 main.o65 font.o65 palette.o65 data.o65 const.o65 logo.o65 logospr.o65 text.o65 dma.o65 menu.o65 pad.o65 time.o65 mainmenu.o65 sysinfo.o65 spc700.o65 spcplay.o65 # gfx.o65 # vars.o65
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all: clean menu.bin map
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@ -168,4 +168,24 @@ text_mm_vmode_game .byt "Game video mode", 0
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text_mm_sysinfo .byt "System Information", 0
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text_statusbar_keys .byt "A:Select B:Back X:Menu", 0
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text_last .byt "Run previous ROM: Press Start again to confirm", 0
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text_system .byt "PPU1 Rev.: x PPU2 Rev.: y CPU Rev.: z",0
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text_spcplay .byt "SPC Music Player", 0
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spcplay_win_x .byt 15
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spcplay_win_y .byt 15
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spcplay_win_w .byt 33
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spcplay_win_h .byt 5
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text_spcload .byt "Loading SPC data to SPC700...", 0
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text_spcstarta .byt "**** Now playing SPC tune ****", 0
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text_spcstartb .byt "Name: ",0
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text_spcstartc .byt "Song: ",0
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text_spcstartd .byt "Artist:",0
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spcstart_win_x .byt 10
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spcstart_win_y .byt 13
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spcstart_win_w .byt 44
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spcstart_win_h .byt 9
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text_spcid .byt "SNES-SPC700"
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@ -183,5 +183,10 @@ direntry_xscroll
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.word 0
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direntry_xscroll_wait
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.word 0
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infloop .byt 0,0 ; to be filled w/ 80 FE
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infloop .byt 0,0 ; to be filled w/ 80 FE
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;------------------------
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saved_sp
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.word 0
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warm_signature
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.word 0
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wram_fadeloop .byt 0
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@ -11,6 +11,35 @@ GAME_MAIN:
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sta @AVR_PARAM+2
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sep #$20 : .as
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stz $4200 ; inhibit VBlank NMI
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rep #$20 : .al
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lda @warm_signature ; Was CMD_RESET issued before reset?
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cmp #$fa50 ; If yes, then perform warm boot procedure
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bne coldboot
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lda #$0000
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sta @warm_signature
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lda @saved_sp ; Restore previous stack pointer
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tcs
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sep #$20 : .as
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jsr killdma ; The following initialization processes must not touch memory
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jsr waitblank ; structures used by the main menu !
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jsr snes_init
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lda #$01
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sta $420d ; fast cpu
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jsr setup_gfx
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jsr colortest
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jsr setup_hdma
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jsr tests
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jmp @set_bank ; Set bios bank, just to be sure
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set_bank:
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plp ; Restore processor state
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rts ; Jump to the routine which called the sub-routine issuing CMD_RESET
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coldboot: ; Regular, cold-start init
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sep #$20 : .as
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jsr killdma
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jsr waitblank
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jsr snes_init
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@ -70,12 +99,15 @@ killdma:
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waitblank:
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php
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sep #$30 : .as : .xs
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- lda $4212
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and #$80
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bne -
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- lda $4212
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and #$80
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beq -
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plp
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rts
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colortest:
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@ -225,6 +257,7 @@ tests:
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sta $212e
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sta $212f
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stz $2121
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jsr waitblank
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lda #$0f
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sta $2100 ;screen on, full brightness
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lda #9
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@ -6,6 +6,11 @@
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/* These must be defined as constants, because they're used
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* in calculation that is sent to PPU as parameters */
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#define APUIO0 $2140
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#define APUIO1 $2141
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#define APUIO2 $2142
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#define APUIO3 $2143
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#define BG1_TILE_BASE $5800
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#define BG2_TILE_BASE $5000
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@ -27,3 +32,9 @@
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#define ROOT_DIR $C10000
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#define CMD_SYSINFO $03
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#define CMD_LOADSPC $05
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#define CMD_RESET $06
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#define SPC_DATA $DD0000
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#define SPC_HEADER $DE0000
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#define SPC_DSP_REGS $DE0100
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@ -272,6 +272,10 @@ dirent_is_file
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lda #$0000
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bra dirent_type_cont
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+
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cmp #$0003 ;SPC -> palette 2
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bne +
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lda #$0002
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bra dirent_type_cont
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cmp #$0004 ;IPS -> palette 2 (green)
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bne +
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lda #$0002
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@ -502,6 +506,8 @@ select_item:
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lda [dirptr_addr], y
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cmp #$01
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beq sel_is_file
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cmp #$03
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beq sel_is_spc
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cmp #$04
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beq sel_is_file
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cmp #$80
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@ -519,6 +525,9 @@ sel_is_parent
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sel_is_dir
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jsr select_dir
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bra select_item_cont
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sel_is_spc
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jsr select_spc
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bra select_item_cont
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select_file:
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; have avr load the rom
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@ -635,6 +644,27 @@ select_parent:
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sta @menu_dirty
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rts
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select_spc:
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dey
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rep #$20 : .al
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lda [dirptr_addr], y
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and #$00ff
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sta @AVR_PARAM+2
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dey
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dey
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lda [dirptr_addr], y
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sta @AVR_PARAM
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sep #$20 : .as
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lda #CMD_LOADSPC
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sta @AVR_CMD
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wait_spc:
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lda @AVR_CMD
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cmp #$00
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bne wait_spc
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jsr spcplayer
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jsr restore_screen
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rts
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menu_key_x:
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jsr mainmenu
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rts
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61
snes/spc700.a65
Normal file
61
snes/spc700.a65
Normal file
@ -0,0 +1,61 @@
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; All SPC700 routines in SPC700 machine code
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; SPC loader & transfer routines by Shay Green <gblargg@gmail.com>
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loader ; .org $0002
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.byt $F8,$21 ; mov x,@loader_data
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.byt $BD ; mov sp,x
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.byt $CD,$22 ; mov x,#@loader_data+1
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; Push PC and PSW from SPC header
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.byt $BF ; mov a,(x)+
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.byt $2D ; push a
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.byt $BF ; mov a,(x)+
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.byt $2D ; push a
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.byt $BF ; mov a,(x)+
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.byt $2D ; push a
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; Set FLG to $60 rather than value from SPC
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.byt $E8,$60 ; mov a,#$60
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.byt $D4,$6C ; mov FLG+x,a
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; Restore DSP registers
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.byt $8D,$00 ; mov y,#0
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.byt $BF ; next: mov a,(x)+
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.byt $CB,$F2 ; mov $F2,y
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.byt $C4,$F3 ; mov $F3,a
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.byt $FC ; inc y
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.byt $10,-8 ; bpl next
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.byt $8F,$6C,$F2 ; mov $F2,#FLG ; set for later
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; Rerun loader
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.byt $5F,$C0,$FF ; jmp $FFC0
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;---------------------------------------
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transfer ; .org $0002
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.byt $CD,$FE ; mov x,#$FE ; transfer 254 pages
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; Transfer four-byte chunks
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.byt $8D,$3F ; page: mov y,#$3F
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.byt $E4,$F4 ; quad: mov a,$F4
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.byt $D6,$00,$02 ; mov0: mov !$0200+y,a
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.byt $E4,$F5 ; mov a,$F5
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.byt $D6,$40,$02 ; mov1: mov !$0240+y,a
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.byt $E4,$F6 ; mov a,$F6
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.byt $D6,$80,$02 ; mov2: mov !$0280+y,a
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.byt $E4,$F7 ; mov a,$F7 ; tell S-CPU we're ready for more
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.byt $CB,$F7 ; mov $F7,Y
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.byt $D6,$C0,$02 ; mov3: mov !$02C0+y,a
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.byt $DC ; dec y
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.byt $10,-25 ; bpl quad
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; Increment MSBs of addresses
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.byt $AB,$0A ; inc mov0+2
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.byt $AB,$0F ; inc mov1+2
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.byt $AB,$14 ; inc mov2+2
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.byt $AB,$1B ; inc mov3+2
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.byt $1D ; dec x
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.byt $D0,-38 ; bne page
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; Rerun loader
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.byt $5F,$C0,$FF ; jmp $FFC0
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648
snes/spcplay.a65
Normal file
648
snes/spcplay.a65
Normal file
@ -0,0 +1,648 @@
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#include "memmap.i65"
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; SPC Player
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; SPC700 transfer and IO routines by Shay Green <gblargg@gmail.com>
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spcplayer:
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php
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sep #$30 : .as : .xs
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ldx #$0a ; Check if SPC header is present
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-
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lda @SPC_HEADER,x
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cmp @text_spcid,x
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beq +
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jmp spc_exit
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+
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dey
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bne -
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rep #$10 : .xl ; Now draw lots of stuff
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stz bar_wl
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dec bar_wl
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stz bar_xl
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dec bar_xl
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stz bar_yl
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dec bar_yl
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jsr backup_screen
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lda #^text_spcplay ; Loading window
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sta window_tbank
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ldx #!text_spcplay
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stx window_taddr
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lda @spcplay_win_x
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sta window_x
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lda @spcplay_win_y
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sta window_y
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lda @spcplay_win_w
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sta window_w
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lda @spcplay_win_h
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sta window_h
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jsr draw_window
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lda #^text_spcload ; Loading text
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ldx #!text_spcload
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sta print_bank
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stx print_src
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stz print_pal
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lda #29
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sta print_count
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lda #17
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sta print_y
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lda #17
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sta print_x
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jsr hiprint
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stz isr_done
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-
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lda isr_done ; Wait until text is being printed...
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beq -
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jsr spc700_load ; Load SPC into SPC700
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lda #^text_spcplay
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sta window_tbank
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ldx #!text_spcplay
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stx window_taddr
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lda @spcstart_win_x
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sta window_x
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lda @spcstart_win_y
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sta window_y
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lda @spcstart_win_w
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sta window_w
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lda @spcstart_win_h
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sta window_h
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jsr draw_window
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lda #^text_spcstarta
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ldx #!text_spcstarta
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #30
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sta print_count
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lda #15
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sta print_y
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lda #17
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sta print_x
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jsr hiprint
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lda #^text_spcstartb
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ldx #!text_spcstartb
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #07
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sta print_count
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lda #17
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sta print_y
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lda #12
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sta print_x
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jsr hiprint
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lda #$de
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ldx #$004e
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sta print_bank
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stx print_src
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stz print_pal
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lda #32
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sta print_count
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lda #17
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sta print_y
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lda #20
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sta print_x
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jsr hiprint
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lda #^text_spcstartc
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ldx #!text_spcstartc
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #07
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sta print_count
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lda #18
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sta print_y
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lda #12
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sta print_x
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jsr hiprint
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lda #$de
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ldx #$002e
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sta print_bank
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stx print_src
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stz print_pal
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lda #32
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sta print_count
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lda #18
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sta print_y
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lda #20
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sta print_x
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jsr hiprint
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lda #^text_spcstartd
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ldx #!text_spcstartd
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sta print_bank
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stx print_src
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lda #$01
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sta print_pal
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lda #07
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sta print_count
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lda #19
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sta print_y
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lda #12
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sta print_x
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jsr hiprint
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lda #$de
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ldx #$00b1
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sta print_bank
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stx print_src
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stz print_pal
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lda #32
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sta print_count
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lda #19
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sta print_y
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lda #20
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sta print_x
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jsr hiprint
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spc_playloop:
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lda isr_done ; SPC player loop
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lsr
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bcc spc_playloop
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jsr printtime
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stz isr_done
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jsr read_pad
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lda #$80
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and pad1trig+1
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bne spc_key_b
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bra spc_playloop
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spc_key_b:
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rep #$20 : .al
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tsc
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sta saved_sp ; Save SP for later re-entry
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lda #$fa50 ; Write reset signature
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sta @warm_signature
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sep #$20 : .as
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sei ; Blank screen & issue CMD_RESET command to Microcontroller...
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stz $2100 ; ...this is required, because there is no other way to stop S-SMP & S-DSP
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lda #CMD_RESET
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sta @AVR_CMD
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-
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bra - ; At this point, the SNES waits for an external reset from the Microcontroller
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spc_exit: ; Return from player in case of wrong SPC file data
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plp
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rts
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;---------------------------------------
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spc700_load:
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php
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sep #$20 : .as
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rep #$10 : .xl
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sei ; Disable NMI & IRQ
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stz $4200 ; The SPC player code is really timing sensitive ;)
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jsr upload_dsp_regs ; Upload S-DSP registers
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jsr upload_high_ram ; Upload 63.5K of SPC700 ram
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jsr upload_low_ram ; Upload rest of ram
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jsr restore_final ; Restore SPC700 state & start execution
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lda #$81 ; VBlank NMI + Auto Joypad Read
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sta $4200 ; enable V-BLANK NMI
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cli
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plp
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rts
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;---------------------------------------
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; Uploads DSP registers and some other setup code
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upload_dsp_regs:
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; ---- Begin upload
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ldy #$0002
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jsr spc_begin_upload
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; ---- Upload loader
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ldx #$0000
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-
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lda @loader,x
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jsr spc_upload_byte
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inx
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cpy #31 ; size of loader
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bne -
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; ---- Upload SP, PC & PSW
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lda @SPC_HEADER+43
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jsr spc_upload_byte
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lda @SPC_HEADER+38
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jsr spc_upload_byte
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lda @SPC_HEADER+37
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jsr spc_upload_byte
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lda @SPC_HEADER+42
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jsr spc_upload_byte
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; ---- Upload DSP registers
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ldx #$0000
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-
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lda @SPC_DSP_REGS,x
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jsr spc_upload_byte
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inx
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cpx #128
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bne -
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; --- Upload fixed values for $F1-$F3
|
||||
|
||||
ldy #$00F1
|
||||
jsr spc_next_upload
|
||||
|
||||
lda #$80 ; stop timers
|
||||
jsr spc_upload_byte
|
||||
lda #$6c ; get dspaddr set for later
|
||||
jsr spc_upload_byte
|
||||
lda #$60
|
||||
jsr spc_upload_byte
|
||||
|
||||
; ---- Upload $f8-$1ff
|
||||
|
||||
ldy #$00F8
|
||||
jsr spc_next_upload
|
||||
|
||||
ldx #$00F8
|
||||
-
|
||||
lda @SPC_DATA,x
|
||||
jsr spc_upload_byte
|
||||
inx
|
||||
cpx #$200
|
||||
bne -
|
||||
|
||||
; ---- Execute loader
|
||||
|
||||
ldy #$0002
|
||||
jsr spc_execute
|
||||
rts
|
||||
;---------------------------------------
|
||||
upload_high_ram:
|
||||
|
||||
ldy #$0002
|
||||
jsr spc_begin_upload
|
||||
|
||||
; ---- Upload transfer routine
|
||||
|
||||
ldx #$0000
|
||||
-
|
||||
lda @transfer,x
|
||||
jsr spc_upload_byte
|
||||
inx
|
||||
cpy #43 ; size of transfer routine
|
||||
bne -
|
||||
|
||||
ldx #$023f ; prepare transfer address
|
||||
|
||||
; ---- Execute transfer routine
|
||||
|
||||
ldy #$0002
|
||||
sty APUIO2
|
||||
stz APUIO1
|
||||
lda APUIO0
|
||||
inc
|
||||
inc
|
||||
sta APUIO0
|
||||
; Wait for acknowledgement
|
||||
-
|
||||
cmp APUIO0
|
||||
bne -
|
||||
|
||||
; ---- Burst transfer of 63.5K using custom routine
|
||||
|
||||
outer_transfer_loop:
|
||||
ldy #$003f ; 3
|
||||
inner_transfer_loop:
|
||||
lda @SPC_DATA,x ; 5 |
|
||||
sta APUIO0 ; 4 |
|
||||
lda @SPC_DATA+$40,x ; 5 |
|
||||
sta APUIO1 ; 4 |
|
||||
lda @SPC_DATA+$80,x ; 5 |
|
||||
sta APUIO2 ; 4 |
|
||||
lda @SPC_DATA+$C0,x ; 5 |
|
||||
sta APUIO3 ; 4 |
|
||||
tya ; 2 >> 38 cycles
|
||||
-
|
||||
cmp APUIO3 ; 4 |
|
||||
bne - ; 3 |
|
||||
dex ; 2 |
|
||||
dey ; 2 |
|
||||
bpl inner_transfer_loop ; 3 >> 14 cycles
|
||||
|
||||
rep #$21 : .al ; 3 |
|
||||
txa ; 2 |
|
||||
adc #$140 ; 3 |
|
||||
tax ; 2 |
|
||||
sep #$20 : .as ; 3 |
|
||||
cpx #$003f ; 3 |
|
||||
bne outer_transfer_loop ; 3 >> 19 cycles
|
||||
|
||||
rts
|
||||
|
||||
;---------------------------------------
|
||||
upload_low_ram:
|
||||
|
||||
; ---- Upload $0002-$00EF
|
||||
|
||||
ldy #$0002
|
||||
jsr spc_begin_upload
|
||||
|
||||
ldx #$0002
|
||||
-
|
||||
lda @SPC_DATA,x
|
||||
jsr spc_upload_byte
|
||||
inx
|
||||
cpx #$00F0
|
||||
bne -
|
||||
rts
|
||||
;---------------------------------------
|
||||
; Executes final restoration code
|
||||
restore_final:
|
||||
jsr start_exec_io
|
||||
stz $420d ; SPC700 I/O code requires SLOW timing
|
||||
|
||||
; ---- Restore first two bytes of RAM
|
||||
|
||||
lda @SPC_DATA
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_DATA
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$00C4 ; MOV $00,A
|
||||
jsr exec_instr
|
||||
|
||||
lda @SPC_DATA+1
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_DATA+1
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$01C4 ; MOV $01,A
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore SP
|
||||
|
||||
lda @SPC_HEADER+43
|
||||
sec
|
||||
sbc #3
|
||||
xba
|
||||
lda #$cd ; MOV X,#@SPC_HEADER+43
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$bd ; MOV SP,X
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore X
|
||||
|
||||
lda @SPC_HEADER+40
|
||||
xba
|
||||
lda #$cd ; MOV X,#@SPC_HEADER+40
|
||||
tax
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore Y
|
||||
|
||||
lda @SPC_HEADER+41
|
||||
xba
|
||||
lda #$8d ; MOV Y,#@SPC_HEADER+41
|
||||
tax
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore DSP FLG register
|
||||
|
||||
lda @SPC_DSP_REGS+$6c
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_DSP_REGS+$6c
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$f3C4 ; MOV $f3,A -> $f2 has been set-up before by SPC700 loader
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore DSP KON register
|
||||
|
||||
lda #$4C
|
||||
xba
|
||||
lda #$e8 ; MOV A,#$4c
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$f2C4 ; MOV $f2,A
|
||||
jsr exec_instr
|
||||
lda @SPC_DSP_REGS+$4C
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_DSP_REGS+$4c
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$f3C4 ; MOV $f3,A
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore DSP register address
|
||||
|
||||
lda @SPC_DATA+$F2
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_DATA+$F2
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$f2C4 ; MOV dest,A
|
||||
jsr exec_instr
|
||||
|
||||
; ---- Restore CONTROL register
|
||||
|
||||
lda @SPC_DATA+$F1
|
||||
and #$CF ; don't clear input ports
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_DATA+$F1
|
||||
tax
|
||||
jsr exec_instr
|
||||
ldx #$f1C4 ; MOV $F1,A
|
||||
jsr exec_instr
|
||||
|
||||
;---- Restore A
|
||||
|
||||
lda @SPC_HEADER+39
|
||||
xba
|
||||
lda #$e8 ; MOV A,#@SPC_HEADER+39
|
||||
tax
|
||||
jsr exec_instr
|
||||
|
||||
;---- Restore PSW and PC
|
||||
|
||||
ldx #$7F00 ; NOP; RTI
|
||||
stx APUIO0
|
||||
lda #$FC ; Patch loop to execute instruction just written
|
||||
sta APUIO3
|
||||
|
||||
;---- restore IO ports $f4 - $f7
|
||||
|
||||
rep #$20 : .al
|
||||
lda @SPC_DATA+$F4
|
||||
tax
|
||||
lda @SPC_DATA+$F6
|
||||
sta APUIO2
|
||||
stx APUIO0 ; last to avoid overwriting RETI before run
|
||||
sep #$20 : .as
|
||||
|
||||
lda #$01
|
||||
sta $420d ; restore FAST CPU operation
|
||||
rts
|
||||
;---------------------------------------
|
||||
spc_begin_upload:
|
||||
|
||||
sty APUIO2 ; Set address
|
||||
|
||||
ldy #$BBAA ; Wait for SPC
|
||||
-
|
||||
cpy APUIO0
|
||||
bne -
|
||||
|
||||
lda #$CC ; Send acknowledgement
|
||||
sta APUIO1
|
||||
sta APUIO0
|
||||
|
||||
- ; Wait for acknowledgement
|
||||
cmp APUIO0
|
||||
bne -
|
||||
|
||||
ldy #0 ; Initialize index
|
||||
rts
|
||||
;---------------------------------------
|
||||
spc_upload_byte:
|
||||
sta APUIO1
|
||||
|
||||
tya ; Signal it's ready
|
||||
sta APUIO0
|
||||
- ; Wait for acknowledgement
|
||||
cmp APUIO0
|
||||
bne -
|
||||
|
||||
iny
|
||||
|
||||
rts
|
||||
;---------------------------------------
|
||||
spc_next_upload:
|
||||
sty APUIO2
|
||||
|
||||
; Send command
|
||||
; Special case operation has been fully tested.
|
||||
lda APUIO0
|
||||
inc
|
||||
inc
|
||||
bne +
|
||||
inc
|
||||
+
|
||||
sta APUIO1
|
||||
sta APUIO0
|
||||
|
||||
; Wait for acknowledgement
|
||||
-
|
||||
cmp APUIO0
|
||||
bne -
|
||||
|
||||
ldy #0
|
||||
rts
|
||||
;---------------------------------------
|
||||
spc_execute:
|
||||
sty APUIO2
|
||||
|
||||
stz APUIO1
|
||||
|
||||
lda APUIO0
|
||||
inc
|
||||
inc
|
||||
sta APUIO0
|
||||
|
||||
; Wait for acknowledgement
|
||||
-
|
||||
cmp APUIO0
|
||||
bne -
|
||||
|
||||
rts
|
||||
;---------------------------------------
|
||||
start_exec_io:
|
||||
; Set execution address
|
||||
ldx #$00F5
|
||||
stx APUIO2
|
||||
|
||||
stz APUIO1 ; NOP
|
||||
ldx #$FE2F ; BRA *-2
|
||||
|
||||
; Signal to SPC that we're ready
|
||||
lda APUIO0
|
||||
inc
|
||||
inc
|
||||
sta APUIO0
|
||||
|
||||
; Wait for acknowledgement
|
||||
-
|
||||
cmp APUIO0
|
||||
bne -
|
||||
|
||||
; Quickly write branch
|
||||
stx APUIO2
|
||||
|
||||
rts
|
||||
;---------------------------------------
|
||||
exec_instr:
|
||||
; Replace instruction
|
||||
stx APUIO0
|
||||
lda #$FC
|
||||
sta APUIO3 ; 30
|
||||
|
||||
; SPC BRA loop takes 4 cycles, so it reads
|
||||
; the branch offset every 4 SPC cycles (84 master).
|
||||
; We must handle the case where it read just before
|
||||
; the write above, and when it reads just after it.
|
||||
; If it reads just after, we have at least 7 SPC
|
||||
; cycles (147 master) to change restore the branch
|
||||
; offset.
|
||||
|
||||
; 48 minimum, 90 maximum
|
||||
ora #0
|
||||
ora #0
|
||||
ora #0
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
; 66 delay, about the middle of the above limits
|
||||
phd ;4
|
||||
pld ;5
|
||||
|
||||
; Give plenty of extra time if single execution
|
||||
; isn't needed, as this avoids such tight timing
|
||||
; requirements.
|
||||
|
||||
; phd ;4
|
||||
; pld ;5
|
||||
; phd ;4
|
||||
; pld ;5
|
||||
|
||||
; Patch loop to skip first two bytes
|
||||
lda #$FE ; 16
|
||||
sta APUIO3 ; 30
|
||||
|
||||
; 38 minimum (assuming 66 delay above)
|
||||
phd ; 4
|
||||
pld ; 5
|
||||
|
||||
; Give plenty of extra time if single execution
|
||||
; isn't needed, as this avoids such tight timing
|
||||
; requirements.
|
||||
|
||||
phd
|
||||
pld
|
||||
phd
|
||||
pld
|
||||
rts
|
||||
Loading…
x
Reference in New Issue
Block a user