diff --git a/src/fpga_spi.c b/src/fpga_spi.c
index ab38f15..ed315ad 100644
--- a/src/fpga_spi.c
+++ b/src/fpga_spi.c
@@ -135,7 +135,8 @@
 #include "timer.h"
 
 void fpga_spi_init(void) {
-  spi_init(SPI_SPEED_FPGA_FAST);
+  spi_init(SPI_SPEED_FAST);
+  BITBAND(FPGA_MCU_RDY_REG->FIODIR, FPGA_MCU_RDY_BIT) = 0;
 }
 
 void set_msu_addr(uint16_t address) {
diff --git a/src/fpga_spi.h b/src/fpga_spi.h
index fc4778f..201179f 100644
--- a/src/fpga_spi.h
+++ b/src/fpga_spi.h
@@ -29,6 +29,8 @@
 
 #include <arm/NXP/LPC17xx/LPC17xx.h>
 #include "bits.h"
+#include "spi.h"
+#include "config.h"
 
 #define FPGA_SS_BIT	16
 #define FPGA_SS_REG	LPC_GPIO0
@@ -53,6 +55,7 @@
 #define FEAT_ST0010        (1 << 1)
 #define FEAT_DSPX          (1 << 0)
 
+#define FPGA_WAIT_RDY()    do {while(BITBAND(SSP_REGS->SR, SSP_BSY)); while(!BITBAND(FPGA_MCU_RDY_REG->FIOPIN, FPGA_MCU_RDY_BIT));} while (0)
 
 void fpga_spi_init(void);
 uint8_t fpga_test(void);
diff --git a/src/memory.c b/src/memory.c
index b8cdfa4..17523f9 100644
--- a/src/memory.c
+++ b/src/memory.c
@@ -63,7 +63,7 @@ void sram_writebyte(uint8_t val, uint32_t addr) {
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
   FPGA_TX_BYTE(val);
-  FPGA_TX_BYTE(0x00); /* dummy */
+  FPGA_WAIT_RDY();
   FPGA_DESELECT();
 }
 
@@ -71,8 +71,8 @@ uint8_t sram_readbyte(uint32_t addr) {
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88); /* READ */
-  FPGA_TX_BYTE(0x00); /* dummy */
-  uint8_t val = FPGA_TXRX_BYTE(0x00);
+  FPGA_WAIT_RDY();
+  uint8_t val = FPGA_RX_BYTE();
   FPGA_DESELECT();
   return val;
 }
@@ -82,8 +82,9 @@ void sram_writeshort(uint16_t val, uint32_t addr) {
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
   FPGA_TX_BYTE(val&0xff);
+  FPGA_WAIT_RDY();
   FPGA_TX_BYTE((val>>8)&0xff);
-  FPGA_TX_BYTE(0x00); /* dummy */
+  FPGA_WAIT_RDY();
   FPGA_DESELECT();
 }
 
@@ -92,10 +93,13 @@ void sram_writelong(uint32_t val, uint32_t addr) {
   FPGA_SELECT();
   FPGA_TX_BYTE(0x98); /* WRITE */
   FPGA_TX_BYTE(val&0xff);
+  FPGA_WAIT_RDY();
   FPGA_TX_BYTE((val>>8)&0xff);
+  FPGA_WAIT_RDY();
   FPGA_TX_BYTE((val>>16)&0xff);
+  FPGA_WAIT_RDY();
   FPGA_TX_BYTE((val>>24)&0xff);
-  FPGA_TX_BYTE(0x00);
+  FPGA_WAIT_RDY();
   FPGA_DESELECT();
 }
 
@@ -103,9 +107,10 @@ uint16_t sram_readshort(uint32_t addr) {
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88);
-  FPGA_TX_BYTE(0x00);
-  uint32_t val = FPGA_TXRX_BYTE(0x00);
-  val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8);
+  FPGA_WAIT_RDY();
+  uint32_t val = FPGA_RX_BYTE();
+  FPGA_WAIT_RDY();
+  val |= ((uint32_t)FPGA_RX_BYTE()<<8);
   FPGA_DESELECT();
   return val;
 }
@@ -114,11 +119,14 @@ uint32_t sram_readlong(uint32_t addr) {
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88);
-  FPGA_TX_BYTE(0x00);
-  uint32_t val = FPGA_TXRX_BYTE(0x00);
-  val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8);
-  val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<16);
-  val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<24);
+  FPGA_WAIT_RDY();
+  uint32_t val = FPGA_RX_BYTE();
+  FPGA_WAIT_RDY();
+  val |= ((uint32_t)FPGA_RX_BYTE()<<8);
+  FPGA_WAIT_RDY();
+  val |= ((uint32_t)FPGA_RX_BYTE()<<16);
+  FPGA_WAIT_RDY();
+  val |= ((uint32_t)FPGA_RX_BYTE()<<24);
   FPGA_DESELECT();
   return val;
 }
@@ -127,13 +135,16 @@ void sram_readlongblock(uint32_t* buf, uint32_t addr, uint16_t count) {
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88);
-  FPGA_TX_BYTE(0x00);
   uint16_t i=0;
   while(i<count) {
-    uint32_t val = (uint32_t)FPGA_TXRX_BYTE(0x00)<<24;
-    val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<16);
-    val |= ((uint32_t)FPGA_TXRX_BYTE(0x00)<<8);
-    val |= FPGA_TXRX_BYTE(0x00);
+    FPGA_WAIT_RDY();
+    uint32_t val = (uint32_t)FPGA_RX_BYTE()<<24;
+    FPGA_WAIT_RDY();
+    val |= ((uint32_t)FPGA_RX_BYTE()<<16);
+    FPGA_WAIT_RDY();
+    val |= ((uint32_t)FPGA_RX_BYTE()<<8);
+    FPGA_WAIT_RDY();
+    val |= FPGA_RX_BYTE();
     buf[i++] = val;
   }
   FPGA_DESELECT();
@@ -145,9 +156,9 @@ void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
   set_mcu_addr(addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88);	/* READ */
-  FPGA_TX_BYTE(0x00);	/* dummy */
   while(count--) {
-    *(tgt++) = FPGA_TXRX_BYTE(0x00);
+    FPGA_WAIT_RDY();
+    *(tgt++) = FPGA_RX_BYTE();
   }
   FPGA_DESELECT();
 }
@@ -160,8 +171,8 @@ void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
   FPGA_TX_BYTE(0x98);	/* WRITE */
   while(count--) {
     FPGA_TX_BYTE(*src++);
+    FPGA_WAIT_RDY();
   }
-  FPGA_TX_BYTE(0x00);	/* dummy */
   FPGA_DESELECT();
 }
 
@@ -309,8 +320,8 @@ uint32_t load_sram(uint8_t* filename, uint32_t base_addr) {
     FPGA_TX_BYTE(0x98);
     for(int j=0; j<bytes_read; j++) {
       FPGA_TX_BYTE(file_buf[j]);
+      FPGA_WAIT_RDY();
     }
-    FPGA_TX_BYTE(0x00); /* dummy tx */
     FPGA_DESELECT();
   }
   file_close();
@@ -330,8 +341,8 @@ uint32_t load_sram_rle(uint8_t* filename, uint32_t base_addr) {
     data = rle_file_getc();
     if (file_res || file_status) break;
     FPGA_TX_BYTE(data);
+    FPGA_WAIT_RDY();
   }
-  FPGA_TX_BYTE(0x00); /* dummy tx */
   FPGA_DESELECT();
   file_close();
   return (uint32_t)filesize;
@@ -349,9 +360,9 @@ uint32_t load_bootrle(uint32_t base_addr) {
     data = rle_mem_getc();
     if(rle_state) break;
     FPGA_TX_BYTE(data);
+    FPGA_WAIT_RDY();
     filesize++;
   }
-  FPGA_TX_BYTE(0x00); /* dummy tx */
   FPGA_DESELECT();
   return (uint32_t)filesize;
 }
@@ -370,9 +381,9 @@ void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
     set_mcu_addr(base_addr+count);
     FPGA_SELECT();
     FPGA_TX_BYTE(0x88); /* read */
-    FPGA_TX_BYTE(0x00); /* dummy */
     for(int j=0; j<sizeof(file_buf); j++) {
-      file_buf[j] = FPGA_TXRX_BYTE(0x00);
+      FPGA_WAIT_RDY();
+      file_buf[j] = FPGA_RX_BYTE();
       count++;
     }
     FPGA_DESELECT();
@@ -394,9 +405,9 @@ uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
   set_mcu_addr(base_addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88);
-  FPGA_TX_BYTE(0x00);
   for(count=0; count<size; count++) {
-    data = FPGA_TXRX_BYTE(0x00);
+    FPGA_WAIT_RDY();
+    data = FPGA_RX_BYTE();
     if(get_snes_reset()) {
       crc_valid = 0;
       break;
@@ -443,8 +454,8 @@ void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val) {
   FPGA_TX_BYTE(0x98);
   for(uint32_t i=0; i<len; i++) {
     FPGA_TX_BYTE(val);
+    FPGA_WAIT_RDY();
   }
-  FPGA_TX_BYTE(0x00);
   FPGA_DESELECT();
 }
 
@@ -452,14 +463,14 @@ uint64_t sram_gettime(uint32_t base_addr) {
   set_mcu_addr(base_addr);
   FPGA_SELECT();
   FPGA_TX_BYTE(0x88);
-  FPGA_TX_BYTE(0x00);
   uint8_t data;
   uint64_t result = 0LL;
   /* 1st nibble is the century - 10 (binary)
      4th nibble is the month (binary)
      all other fields are BCD */
   for(int i=0; i<12; i++) {
-    data = FPGA_TXRX_BYTE(0x00);
+    FPGA_WAIT_RDY();
+    data = FPGA_RX_BYTE();
     data &= 0xf;
     switch(i) {
       case 0:
diff --git a/src/msu1.c b/src/msu1.c
index 8a426f1..6dc298f 100644
--- a/src/msu1.c
+++ b/src/msu1.c
@@ -50,7 +50,6 @@ int msu1_loop() {
   UINT bytes_read2 = 1;
   FRESULT res;
   set_dac_vol(0x00);
-  spi_set_speed(SSP_CLK_DIVISOR_FAST);
   while(fpga_status() & 0x4000);
   uint16_t fpga_status_prev = fpga_status();
   uint16_t fpga_status_now = fpga_status();
@@ -250,7 +249,6 @@ int msu1_loop() {
     if(msu1_check_reset()) {
       f_close(&msufile);
       f_close(&file_handle);
-      spi_set_speed(SSP_CLK_DIVISOR_FPGA_SLOW);
       return 1;
     }
   }