Commit my latest changes

.gitignore

@@ -0,0 +1,22 @@
+*.cod
+*.hex
+*.lst
+*.o
+*.diff
+.DS_Store
+*.o65
+*.ips
+*.bin
+*.map
+*.o.d
+*.log
+*.smc
+*.sfc
+*~
+*.old
+*.elf
+*.img
+autoconf.h
+utils/rle
+utils/derle
+*.bit

cic/supercic/supercic-key.asm

@@ -744,4 +744,4 @@ supercic_pairmode_loop
 ; eeprom memory
 DEEPROM	CODE
 	de      0x09	; D411 (NTSC)
-end
+	end

cic/supercic/supercic-lock.asm

@@ -192,11 +192,11 @@ rst_loop
 	clrf	0x59		; clear D4
 	clrf	0x5e		;
 	clrf	0x5f		;
-        banksel EEADR		; fetch current mode from EEPROM
-        clrf    EEADR		; address 0
-        bsf     EECON1, RD	; 
-        movf    EEDAT, w        ; 
-        banksel PORTA
+	banksel EEADR		; fetch current mode from EEPROM
+	clrf    EEADR		; address 0
+	bsf     EECON1, RD	; 
+	movf    EEDAT, w        ; 
+	banksel PORTA
 	movwf	0x55		; store saved mode in mode var
 	movwf	0x56		; and temp LED
 	movwf	0x58		; and forced region

pcb/kicad/RevE2/sd2snes.pro

@@ -1,4 +1,4 @@
-update=Sat 25 Feb 2012 11:51:50 PM CET
+update=ven. 20 avril 2012 18:26:30 CEST
 version=1
 last_client=pcbnew
 [general]
@@ -87,6 +87,7 @@ PadDrlX=0
 PadDimH=197
 PadDimV=276
 BoardThickness=630
+SgPcb45=1
 TxtPcbV=800
 TxtPcbH=600
 TxtModV=600

src/Makefile

@@ -117,6 +117,7 @@ endif
 # CC must be defined here to generate the correct CFLAGS
 SHELL = sh
 CC = $(ARCH)-gcc
+#CC = clang
 OBJCOPY = $(ARCH)-objcopy
 OBJDUMP = $(ARCH)-objdump
 SIZE = $(ARCH)-size
@@ -125,7 +126,6 @@ REMOVE = rm -f
 COPY = cp
 AWK = awk
 
-
 #---------------- Compiler Options ----------------
 #  -g*:          generate debugging information
 #  -O*:          optimization level
@@ -138,8 +138,10 @@ CFLAGS += $(CDEFS) $(CINCS)
 CFLAGS += -O$(OPT)
 CFLAGS += $(CPUFLAGS) -nostartfiles
 #CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
-CFLAGS += -Wall -Wstrict-prototypes -Werror
+CFLAGS += -Wall -Wstrict-prototypes
+#-Werror
 CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
+#CFLAGS += -I/opt/arm-none-eabi-4.6.2/arm-none-eabi/include/
 CFLAGS += -I$(OBJDIR)
 CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
 CFLAGS += $(CSTANDARD)

src/bootldr/baudcalc.c

@@ -0,0 +1,80 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include "config.h"
+
+static uint8_t uart_lookupratio(float f_fr) {
+  uint16_t errors[72]={0,67,71,77,83,91,100,111,125,
+                       133,143,154,167,182,200,214,222,231,
+                       250,267,273,286,300,308,333,357,364,
+                       375,385,400,417,429,444,455,462,467,
+                       500,533,538,545,556,571,583,600,615,
+                       625,636,643,667,692,700,714,727,733,
+                       750,769,778,786,800,818,833,846,857,
+                       867,875,889,900,909,917,923,929,933};
+
+  uint8_t ratios[72]={0x10,0xf1,0xe1,0xd1,0xc1,0xb1,0xa1,0x91,0x81,
+                      0xf2,0x71,0xd2,0x61,0xb2,0x51,0xe3,0x92,0xd3,
+                      0x41,0xf4,0xb3,0x72,0xa3,0xd4,0x31,0xe5,0xb4,
+                      0x83,0xd5,0x52,0xc5,0x73,0x94,0xb5,0xd6,0xf7,
+                      0x21,0xf8,0xd7,0xb6,0x95,0x74,0xc7,0x53,0xd8,
+                      0x85,0xb7,0xe9,0x32,0xd9,0xa7,0x75,0xb8,0xfb,
+                      0x43,0xda,0x97,0xeb,0x54,0xb9,0x65,0xdb,0x76,
+                      0xfd,0x87,0x98,0xa9,0xba,0xcb,0xdc,0xed,0xfe};
+
+  int fr = (f_fr-1)*1000;
+  int i=0, i_result=0;
+  int err=0, lasterr=1000;
+  for(i=0; i<72; i++) {
+    if(fr<errors[i]) {
+      err=errors[i]-fr;
+    } else {
+      err=fr-errors[i];
+    }
+    if(err<lasterr) {
+      i_result=i;
+      lasterr=err;
+    }
+  }
+  return ratios[i_result];
+}
+static uint32_t baud2divisor(unsigned int baudrate) {
+  uint32_t int_ratio;
+  uint32_t error;
+  uint32_t dl=0;
+  float f_ratio;
+  float f_fr;
+  float f_dl;
+  float f_pclk = (float)CONFIG_CPU_FREQUENCY / CONFIG_UART_PCLKDIV;
+  uint8_t fract_ratio;
+  f_ratio=(f_pclk / 16 / baudrate);
+  int_ratio = (int)f_ratio;
+  error=(f_ratio*1000)-(int_ratio*1000);
+  if(error>990) {
+    int_ratio++;
+  } else if(error>10) {
+    f_fr=1.5;
+    f_dl=f_pclk / (16 * baudrate * (f_fr));
+    dl = (int)f_dl;
+    f_fr=f_pclk / (16 * baudrate * dl);
+    fract_ratio = uart_lookupratio(f_fr);
+  }
+  if(!dl) {
+    return int_ratio;
+  } else {
+    return ((fract_ratio<<16)&0xff0000) | dl;
+  }
+}
+
+int main(int argc, char *argv[])
+{
+   if (argc != 2)
+   {
+      printf("usage: %s baud\n", argv[0]);
+      return -1;
+   }
+      
+   printf("Baud %d : 0x%X\n", atoi(argv[1]), baud2divisor(atoi(argv[1])));
+
+   return 0;
+}

src/bootldr/conf2h.awk

@@ -4,7 +4,7 @@
 # file to a C header. No copyright claimed.
 
 BEGIN {
-  print "// autoconf.h generated from " ARGV[1] " at " strftime() "\n" \
+  print "// autoconf.h generated from " ARGV[1] " at TODAY \n" \
     "#ifndef AUTOCONF_H\n" \
     "#define AUTOCONF_H"
 }

src/bootldr/config.h

@@ -56,6 +56,7 @@
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
 #define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      115200
 #define CONFIG_UART_DEADLOCKABLE
 
 #define SSP_CLK_DIVISOR_FAST 2

src/bootldr/fileops.h

@@ -31,7 +31,9 @@
 
 enum filestates { FILE_OK=0, FILE_ERR, FILE_EOF };
 
-BYTE file_buf[512];
+#define GCC_ALIGN_WORKAROUND __attribute__ ((aligned(4)))
+BYTE file_buf[512] GCC_ALIGN_WORKAROUND;
+
 FATFS fatfs;
 FIL file_handle;
 FRESULT file_res;

src/bootldr/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232"
-ft2232_layout "oocdlink"
-ft2232_latency 2
+ft2232_vid_pid 0x15ba 0x0003
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout "olimex-jtag"
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/bootldr/uart.c

@@ -119,7 +119,7 @@ void uart_init(void) {
 
   /* set baud rate - no fractional stuff for now */
   UART_REGS->LCR = BV(7) | 3; // always 8n1
-  div = 0x850004; // baud2divisor(CONFIG_UART_BAUDRATE);
+  div = 0xF80022; //0x850004; // baud2divisor(CONFIG_UART_BAUDRATE);
 
   UART_REGS->DLL = div & 0xff;
   UART_REGS->DLM = (div >> 8) & 0xff;

src/cli.c

@@ -58,8 +58,8 @@ static char *curchar;
 
 /* Word lists */
 static char command_words[] =
-  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0";
-enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16 };
+  "cd\0reset\0sreset\0dir\0ls\0test\0resume\0loadrom\0loadraw\0saveraw\0put\0rm\0d4\0vmode\0mapper\0settime\0time\0setfeature\0hexdump\0w8\0w16\0stramtest\0";
+enum { CMD_CD = 0, CMD_RESET, CMD_SRESET, CMD_DIR, CMD_LS, CMD_TEST, CMD_RESUME, CMD_LOADROM, CMD_LOADRAW, CMD_SAVERAW, CMD_PUT, CMD_RM, CMD_D4, CMD_VMODE, CMD_MAPPER, CMD_SETTIME, CMD_TIME, CMD_SETFEATURE, CMD_HEXDUMP, CMD_W8, CMD_W16, CMD_SRAMTEST };
 
 /* ------------------------------------------------------------------------- */
 /*   Parse functions                                                         */
@@ -416,6 +416,10 @@ void cmd_w16(void) {
   sram_writeshort(val, offset);
 }
 
+void cmd_sramtest(void) {
+   sram_memtest();
+}
+
 /* ------------------------------------------------------------------------- */
 /*   CLI interface functions                                                 */
 /* ------------------------------------------------------------------------- */
@@ -424,7 +428,7 @@ void cli_init(void) {
 }
 
 void cli_entrycheck() {
-  if(uart_gotc() && uart_getc() == 27) {
+  if(uart_gotc() && ((uart_getc() == 27) || (uart_getc() == 13))) {
     printf("*** BREAK\n");
     cli_loop();
   }
@@ -561,7 +565,10 @@ void cli_loop(void) {
     case CMD_W16:
       cmd_w16();
       break;
+    
+    case CMD_SRAMTEST:
+      cmd_sramtest();
+      break;
     }
-
   }
 }

src/conf2h.awk

@@ -4,7 +4,7 @@
 # file to a C header. No copyright claimed.
 
 BEGIN {
-  print "// autoconf.h generated from " ARGV[1] " at " strftime() "\n" \
+  print "// autoconf.h generated from " ARGV[1] " at TODAY\n" \
     "#ifndef AUTOCONF_H\n" \
     "#define AUTOCONF_H"
 }

src/config

@@ -1,4 +1,4 @@
-CONFIG_VERSION="0.1.3"
+CONFIG_VERSION="0.1.30"
 #FWVER=00010300
-CONFIG_FWVER=66304
+CONFIG_FWVER=66305
 CONFIG_MCU_FOSC=12000000

src/config.h

@@ -39,7 +39,8 @@
 //#define CONFIG_CPU_FREQUENCY      46000000
 #define CONFIG_UART_PCLKDIV       1
 #define CONFIG_UART_TX_BUF_SHIFT  8
-#define CONFIG_UART_BAUDRATE      921600
+//#define CONFIG_UART_BAUDRATE      921600
+#define CONFIG_UART_BAUDRATE      115200
 #define CONFIG_UART_DEADLOCKABLE
 
 #define SSP_CLK_DIVISOR_FAST 2

src/fpga.c

@@ -119,17 +119,17 @@ if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
       led_panic();
     }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
-    uart_putc('p');
+    //uart_putc('p');
 
 
     /* open configware file */
     file_open(filename, FA_READ);
     if(file_res) {
-      uart_putc('?');
-      uart_putc(0x30+file_res);
+      //uart_putc('?');
+      //uart_putc(0x30+file_res);
       return;
     }
-    uart_putc('C');
+    //uart_putc('C');
 
     for (;;) {
       data = rle_file_getc();
@@ -137,16 +137,16 @@ if(BITBAND(PROGBREG->FIOPIN, PROGBBIT)) {
       if (file_status || file_res) break;   /* error or eof */
       FPGA_SEND_BYTE_SERIAL(data);
     }
-    uart_putc('c');
+    //uart_putc('c');
     file_close();
-    printf("fpga_pgm: %d bytes programmed\n", i);
+    printf("%s: %d bytes programmed\n", __func__, i);
     delay_ms(1);
   } while (!fpga_get_done() && retries--);
   if(!fpga_get_done()) {
     printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
     led_panic();
   }
-  printf("FPGA configured\n");
+  printf("%s: FPGA configured\n", __func__);
   fpga_postinit();
 }
 
@@ -160,7 +160,7 @@ void fpga_rompgm() {
     i=0;
     timeout = getticks() + 100;
     fpga_set_prog_b(0);
-    uart_putc('P');
+    //uart_putc('P');
     fpga_set_prog_b(1);
     while(!fpga_get_initb()){
       if(getticks() > timeout) {
@@ -173,26 +173,26 @@ void fpga_rompgm() {
       led_panic();
     }
     LPC_GPIO2->FIOMASK1 = ~(BV(0));
-    uart_putc('p');
+    //uart_putc('p');
 
     /* open configware file */
     rle_mem_init(cfgware, sizeof(cfgware));
-    printf("sizeof(cfgware) = %d\n", sizeof(cfgware));
+    //printf("sizeof(cfgware) = %d\n", sizeof(cfgware));
     for (;;) {
       data = rle_mem_getc();
       if(rle_state) break;
       i++;
       FPGA_SEND_BYTE_SERIAL(data);
     }
-    uart_putc('c');
-    printf("fpga_pgm: %d bytes programmed\n", i);
+    //uart_putc('c');
+    printf("%s: %d bytes programmed\n", __func__, i);
     delay_ms(1);
   } while (!fpga_get_done() && retries--);
   if(!fpga_get_done()) {
     printf("FPGA failed to configure after %d tries.\n", MAXRETRIES);
     led_panic();
   }
-  printf("FPGA configured\n");
+  printf("%s: FPGA configured\n", __func__);
   fpga_postinit();
 }
 

src/main.c

@@ -53,280 +53,356 @@ enum system_states {
   SYS_LAST_STATUS = 1
 };
 
-int main(void) {
-  LPC_GPIO2->FIODIR = BV(4) | BV(5);
-  LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
-  BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
-  LPC_GPIO0->FIODIR = BV(16);
+int main(void)
+{
+   /* Start by initial configuration, needed in all cases */
+   LPC_GPIO2->FIODIR = BV(4) | BV(5);
+   LPC_GPIO1->FIODIR = BV(23) | BV(SNES_CIC_PAIR_BIT);
+   BITBAND(SNES_CIC_PAIR_REG->FIOSET, SNES_CIC_PAIR_BIT) = 1;
+   LPC_GPIO0->FIODIR = BV(16);
 
- /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
-  LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
-                      | BV(3) | BV(5);                    /* SSP0 (FPGA) except SS */
-  LPC_PINCON->PINSEL0 = BV(31);                            /* SSP0 */
-/*                      | BV(13) | BV(15) | BV(17) | BV(19)  SSP1 (SD) */
+   /* connect UART3 on P0[25:26] + SSP0 on P0[15:18] + MAT3.0 on P0[10] */
+   LPC_PINCON->PINSEL1 = BV(18) | BV(19) | BV(20) | BV(21) /* UART3 */
+                       | BV(3) | BV(5);                    /* SSP0 (FPGA) except SS */
+   LPC_PINCON->PINSEL0 = BV(31);                            /* SSP0 */
+   /*                      | BV(13) | BV(15) | BV(17) | BV(19)  SSP1 (SD) */
 
- /* pull-down CIC data lines */
-  LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);
+   /* pull-down CIC data lines */
+   LPC_PINCON->PINMODE0 = BV(0) | BV(1) | BV(2) | BV(3);
 
-  clock_disconnect();
-  snes_init();
-  snes_reset(1);
-  power_init();
-  timer_init();
-  uart_init();
-  fpga_spi_init();
-  spi_preinit();
-  led_init();
- /* do this last because the peripheral init()s change PCLK dividers */
-  clock_init();
-  LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
-led_pwm();
-  sdn_init();
-  printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\ncpu clock: %d Hz\n", CONFIG_CPU_FREQUENCY);
-printf("PCONP=%lx\n", LPC_SC->PCONP);
+   clock_disconnect();
+   /* First init all SNES functions */
+   snes_init();
+   snes_reset(1); /* Maintain RESET UP, to prevent SNES to start */
 
-  file_init();
-  cic_init(0);
-/* setup timer (fpga clk) */
-  LPC_TIM3->CTCR=0;
-  LPC_TIM3->EMR=EMC0TOGGLE;
-  LPC_TIM3->MCR=MR0R;
-  LPC_TIM3->MR0=1;
-  LPC_TIM3->TCR=1;
-  fpga_init();
-  fpga_rompgm();
-  sram_writebyte(0, SRAM_CMD_ADDR);
-  while(1) {
-    if(disk_state == DISK_CHANGED) {
-      sdn_init();
-      newcard = 1;
-    }
-    load_bootrle(SRAM_MENU_ADDR);
-    set_saveram_mask(0x1fff);
-    set_rom_mask(0x3fffff);
-    set_mapper(0x7);
-    snes_reset(0);
-    while(get_cic_state() == CIC_FAIL) {
-      rdyled(0);
+   /* Init all other parts */
+   power_init();
+   timer_init();
+   uart_init();
+   fpga_spi_init();
+   spi_preinit();
+   led_init();
+
+   /* do this last because the peripheral init()s change PCLK dividers */
+   clock_init();
+
+   LPC_PINCON->PINSEL0 |= BV(20) | BV(21);                  /* MAT3.0 (FPGA clock) */
+   led_pwm();
+   sdn_init();
+
+   /* Banner */
+   printf("\n\nsd2snes mk.2\n============\nfw ver.: " CONFIG_VERSION "\nfwver: %d\ncpu clock: %d Hz\n", CONFIG_FWVER, CONFIG_CPU_FREQUENCY);
+   printf("PCONP=%lx\n", LPC_SC->PCONP);
+
+   file_init();
+   cic_init(0);
+
+   /* FPGA Initialisation */
+   /* setup timer (fpga clk) */
+   LPC_TIM3->CTCR = 0;
+   LPC_TIM3->EMR  = EMC0TOGGLE;
+   LPC_TIM3->MCR  = MR0R;
+   LPC_TIM3->MR0  = 1;
+   LPC_TIM3->TCR  = 1;
+   fpga_init();
+   fpga_rompgm();
+
+   sram_writebyte(0, SRAM_CMD_ADDR);
+
+   /* Should test SRAM here */
+ 
+
+   while(1)
+   {
+      if(disk_state == DISK_CHANGED)
+      {
+         sdn_init();
+         newcard = 1;
+      }
+
+      load_bootrle(SRAM_MENU_ADDR);
+      set_saveram_mask(0x1fff);
+      set_rom_mask(0x3fffff);
+      set_mapper(0x7);
+      
+      /* Unlock SNES */
+      snes_reset(0);
+      
+      /* Check CIC status */
+      while(get_cic_state() == CIC_FAIL)
+      {
+         rdyled(0);
+         readled(0);
+         writeled(0);
+         delay_ms(500);
+         rdyled(1);
+         readled(1);
+         writeled(1);
+         delay_ms(500);
+      }
+
+      fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
+      sram_memtest();
+      
+      /* some sanity checks */
+      uint8_t card_go = 0;
+      while(!card_go)
+      {
+         if(disk_status(0) & (STA_NOINIT|STA_NODISK))
+         {
+	         snes_bootprint("        No SD Card found!       \0");
+      	   while(disk_status(0) & (STA_NOINIT|STA_NODISK));
+      	   delay_ms(200);
+         }
+         file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
+      
+         if(file_status != FILE_OK)
+         {
+         	snes_bootprint("  /sd2snes/menu.bin not found!  \0");
+         	while(disk_status(0) == RES_OK);
+         } 
+         else
+         {
+	         card_go = 1;
+         }
+         file_close();
+      }
+      snes_bootprint("           Loading ...          \0");
+      if(get_cic_state() == CIC_PAIR)
+      {
+         printf("PAIR MODE ENGAGED!\n");
+         cic_pair(CIC_NTSC, CIC_NTSC);
+      }
+      
+      rdyled(1);
       readled(0);
       writeled(0);
-      delay_ms(500);
-      rdyled(1);
-      readled(1);
-      writeled(1);
-      delay_ms(500);
-    }
-    /* some sanity checks */
-    uint8_t card_go = 0;
-    while(!card_go) {
-      if(disk_status(0) & (STA_NOINIT|STA_NODISK)) {
-	snes_bootprint("        No SD Card found!       \0");
-	while(disk_status(0) & (STA_NOINIT|STA_NODISK));
-	delay_ms(200);
+
+      cfg_load();
+      cfg_save();
+      
+      sram_writebyte(cfg_is_last_game_valid(), SRAM_STATUS_ADDR+SYS_LAST_STATUS);
+      cfg_get_last_game(file_lfn);
+      sram_writeblock(strrchr((const char*)file_lfn, '/')+1, SRAM_LASTGAME_ADDR, 256);
+      
+      *fs_path=0;
+      uint32_t saved_dir_id;
+      get_db_id(&saved_dir_id);
+
+      uint32_t mem_dir_id = sram_readlong(SRAM_DIRID);
+      uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
+      
+      printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id);
+      
+      if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard))
+      {
+         newcard = 0;
+         /* generate fs footprint (interesting files only) */
+         uint32_t curr_dir_id = scan_dir(fs_path, NULL, 0, 0);
+         printf("curr dir id = %lx\n", curr_dir_id);
+         /* files changed or no database found? */
+         if((get_db_id(&saved_dir_id) != FR_OK) || saved_dir_id != curr_dir_id)
+         {
+	         /* rebuild database */
+	         printf("saved dir id = %lx\n", saved_dir_id);
+	         snes_bootprint("     rebuilding database ...    \0");
+	         curr_dir_id = scan_dir(fs_path, NULL, 1, 0);
+         	sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
+         	uint32_t endaddr, direndaddr;
+         	sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
+         	sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
+         	printf("endaddr: 0x%lX dirend: 0x%lX\n", endaddr, direndaddr);
+         	snes_bootprint("       sorting database ...     \0");
+         	sort_all_dir(direndaddr);
+         	printf("done\n");
+         	snes_bootprint("        saving database ...     \0");
+         	save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
+         	save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
+         	printf("done\n");
+         }
+         else
+         {
+         	printf("saved dir id = %lx\n", saved_dir_id);
+         	printf("different card, consistent db, loading db...\n");
+         	load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
+         	load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+         }
+      
+         sram_writelong(curr_dir_id, SRAM_DIRID);
+         sram_writelong(0x12345678, SRAM_SCRATCHPAD);
       }
-      file_open((uint8_t*)"/sd2snes/menu.bin", FA_READ);
-      if(file_status != FILE_OK) {
-	snes_bootprint("  /sd2snes/menu.bin not found!  \0");
-	while(disk_status(0) == RES_OK);
-      } else {
-	card_go = 1;
+      else
+      {
+         snes_bootprint("    same card, loading db...     \0");
+         printf("same card, loading db...\n");
+         load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
+         load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
       }
-      file_close();
-    }
-    snes_bootprint("           Loading ...          \0");
-    if(get_cic_state() == CIC_PAIR) {
-      printf("PAIR MODE ENGAGED!\n");
-      cic_pair(CIC_NTSC, CIC_NTSC);
-    }
-    rdyled(1);
-    readled(0);
-    writeled(0);
 
-    cfg_load();
-    cfg_save();
-    sram_writebyte(cfg_is_last_game_valid(), SRAM_STATUS_ADDR+SYS_LAST_STATUS);
-    cfg_get_last_game(file_lfn);
-    sram_writeblock(strrchr((const char*)file_lfn, '/')+1, SRAM_LASTGAME_ADDR, 256);
-    *fs_path=0;
-    uint32_t saved_dir_id;
-    get_db_id(&saved_dir_id);
+#if 1
+      cli_loop();
+#endif
 
-    uint32_t mem_dir_id = sram_readlong(SRAM_DIRID);
-    uint32_t mem_magic = sram_readlong(SRAM_SCRATCHPAD);
-    printf("mem_magic=%lx mem_dir_id=%lx saved_dir_id=%lx\n", mem_magic, mem_dir_id, saved_dir_id);
-    if((mem_magic != 0x12345678) || (mem_dir_id != saved_dir_id) || (newcard)) {
-      newcard = 0;
-      /* generate fs footprint (interesting files only) */
-      uint32_t curr_dir_id = scan_dir(fs_path, NULL, 0, 0);
-      printf("curr dir id = %lx\n", curr_dir_id);
-      /* files changed or no database found? */
-      if((get_db_id(&saved_dir_id) != FR_OK)
-	|| saved_dir_id != curr_dir_id) {
-	/* rebuild database */
-	printf("saved dir id = %lx\n", saved_dir_id);
-	printf("rebuilding database...");
-	snes_bootprint("     rebuilding database ...    \0");
-	curr_dir_id = scan_dir(fs_path, NULL, 1, 0);
-	sram_writeblock(&curr_dir_id, SRAM_DB_ADDR, 4);
-	uint32_t endaddr, direndaddr;
-	sram_readblock(&endaddr, SRAM_DB_ADDR+4, 4);
-	sram_readblock(&direndaddr, SRAM_DB_ADDR+8, 4);
-	printf("%lx %lx\n", endaddr, direndaddr);
-	printf("sorting database...");
-	snes_bootprint("       sorting database ...     \0");
-	sort_all_dir(direndaddr);
-	printf("done\n");
-	snes_bootprint("        saving database ...     \0");
-	save_sram((uint8_t*)"/sd2snes/sd2snes.db", endaddr-SRAM_DB_ADDR, SRAM_DB_ADDR);
-	save_sram((uint8_t*)"/sd2snes/sd2snes.dir", direndaddr-(SRAM_DIR_ADDR), SRAM_DIR_ADDR);
-	printf("done\n");
-      } else {
-	printf("saved dir id = %lx\n", saved_dir_id);
-	printf("different card, consistent db, loading db...\n");
-	load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
-	load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
+      /* load menu */
+      fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
+      fpga_dspx_reset(1);
+
+      uart_putc('(');
+      load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR, 0);
+      /* force memory size + mapper */
+      set_rom_mask(0x3fffff);
+      set_mapper(0x7);
+      uart_putc(')');
+      uart_putcrlf();
+
+      sram_writebyte(0, SRAM_CMD_ADDR);
+
+      if((rtc_state = rtc_isvalid()) != RTC_OK)
+      {
+         printf("RTC invalid!\n");
+         sram_writebyte(0xff, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
+         set_bcdtime(0x20110401000000LL);
+         set_fpga_time(0x20110401000000LL);
+         invalidate_rtc();
       }
-      sram_writelong(curr_dir_id, SRAM_DIRID);
-      sram_writelong(0x12345678, SRAM_SCRATCHPAD);
-    } else {
-      snes_bootprint("    same card, loading db...     \0");
-      printf("same card, loading db...\n");
-      load_sram((uint8_t*)"/sd2snes/sd2snes.db", SRAM_DB_ADDR);
-      load_sram((uint8_t*)"/sd2snes/sd2snes.dir", SRAM_DIR_ADDR);
-    }
-    /* cli_loop(); */
-    /* load menu */
+      else
+      {
+         printf("RTC valid!\n");
+         sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
+         set_fpga_time(get_bcdtime());
+      }
+      sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20);
+      printf("SNES GO!\n");
+      snes_reset(1);
+      delay_ms(1);
+      snes_reset(0);
 
-    fpga_pgm((uint8_t*)"/sd2snes/fpga_base.bit");
-    fpga_dspx_reset(1);
-    uart_putc('(');
-    load_rom((uint8_t*)"/sd2snes/menu.bin", SRAM_MENU_ADDR, 0);
-    /* force memory size + mapper */
-    set_rom_mask(0x3fffff);
-    set_mapper(0x7);
-    uart_putc(')');
-    uart_putcrlf();
+      uint8_t cmd = 0;
+      uint64_t btime = 0;
+      uint32_t filesize=0;
+      sram_writebyte(32, SRAM_CMD_ADDR);
+      
+      printf("test sram\n");
+      while(!sram_reliable()) cli_entrycheck();
+      
+      printf("ok\n");
 
-    sram_writebyte(0, SRAM_CMD_ADDR);
-
-    if((rtc_state = rtc_isvalid()) != RTC_OK) {
-      printf("RTC invalid!\n");
-      sram_writebyte(0xff, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
-      set_bcdtime(0x20110401000000LL);
-      set_fpga_time(0x20110401000000LL);
-      invalidate_rtc();
-    } else {
-      printf("RTC valid!\n");
-      sram_writebyte(0x00, SRAM_STATUS_ADDR+SYS_RTC_STATUS);
-      set_fpga_time(get_bcdtime());
-    }
-    sram_memset(SRAM_SYSINFO_ADDR, 13*40, 0x20);
-    printf("SNES GO!\n");
-    snes_reset(1);
-    delay_ms(1);
-    snes_reset(0);
-
-    uint8_t cmd = 0;
-    uint64_t btime = 0;
-    uint32_t filesize=0;
-    sram_writebyte(32, SRAM_CMD_ADDR);
-    printf("test sram\n");
-    while(!sram_reliable()) cli_entrycheck();
-    printf("ok\n");
 //while(1) {
 //  delay_ms(1000);
 //  printf("Estimated SNES master clock: %ld Hz\n", get_snes_sysclk());
 //}
   //sram_hexdump(SRAM_DB_ADDR, 0x200);
   //sram_hexdump(SRAM_MENU_ADDR, 0x400);
-    while(!cmd) {
-      cmd=menu_main_loop();
-      printf("cmd: %d\n", cmd);
-      uart_putc('-');
-      switch(cmd) {
-	case SNES_CMD_LOADROM:
-	  get_selected_name(file_lfn);
-	  printf("Selected name: %s\n", file_lfn);
-          cfg_save_last_game(file_lfn);
-          cfg_set_last_game_valid(1);
-          cfg_save();
-	  filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
-	  break;
-	case SNES_CMD_SETRTC:
-          /* get time from RAM */
-          btime = sram_gettime(SRAM_PARAM_ADDR);
-          /* set RTC */
-          set_bcdtime(btime);
-          set_fpga_time(btime);
-	  cmd=0; /* stay in menu loop */
-	  break;
-        case SNES_CMD_SYSINFO:
-          /* go to sysinfo loop */
-          sysinfo_loop();
-          cmd=0; /* stay in menu loop */
-          break;
-        case SNES_CMD_LOADLAST:
-          cfg_get_last_game(file_lfn);
-          printf("Selected name: %s\n", file_lfn);
-          filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
-          break;
-	default:
-	  printf("unknown cmd: %d\n", cmd);
-	  cmd=0; /* unknown cmd: stay in loop */
-	  break;
-      }
-    }
-    printf("cmd was %x, going to snes main loop\n", cmd);
 
-    if(romprops.has_msu1 && msu1_loop()) {
-      prepare_reset();
-      continue;
-    }
+      while(!cmd)
+      {
+         cmd=menu_main_loop();
+         printf("cmd: %d\n", cmd);
+         uart_putc('-');
+         switch(cmd)
+         {
+	      case SNES_CMD_LOADROM:
+	         get_selected_name(file_lfn);
+	         printf("Selected name: %s\n", file_lfn);
+            cfg_save_last_game(file_lfn);
+            cfg_set_last_game_valid(1);
+            cfg_save();
+	         filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+	         break;
 
-    cmd=0;
-    uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
-    uint16_t reset_count=0;
-    while(fpga_test() == FPGA_TEST_TOKEN) {
-      cli_entrycheck();
-      sleep_ms(250);
-      sram_reliable();
-      printf("%s ", get_cic_statename(get_cic_state()));
-      if(reset_changed) {
-        printf("reset\n");
-        reset_changed = 0;
-        fpga_reset_srtc_state();
+	      case SNES_CMD_SETRTC:
+            /* get time from RAM */
+            btime = sram_gettime(SRAM_PARAM_ADDR);
+            /* set RTC */
+            set_bcdtime(btime);
+            set_fpga_time(btime);
+	         cmd=0; /* stay in menu loop */
+	         break;
+
+         case SNES_CMD_SYSINFO:
+            /* go to sysinfo loop */
+            sysinfo_loop();
+            cmd=0; /* stay in menu loop */
+            break;
+
+         case SNES_CMD_LOADLAST:
+            cfg_get_last_game(file_lfn);
+            printf("Selected name: %s\n", file_lfn);
+            filesize = load_rom(file_lfn, SRAM_ROM_ADDR, LOADROM_WITH_SRAM | LOADROM_WITH_RESET);
+            break;
+
+	      default:
+	         printf("unknown cmd: %d\n", cmd);
+	         cmd=0; /* unknown cmd: stay in loop */
+	         break;
+         }
       }
-      snes_reset_now=get_snes_reset();
-      if(snes_reset_now) {
-	if(!snes_reset_prev) {
-	  printf("RESET BUTTON DOWN\n");
-	  snes_reset_state=1;
-	  reset_count=0;
-	}
-      } else {
-	if(snes_reset_prev) {
-	  printf("RESET BUTTON UP\n");
-	  snes_reset_state=0;
-	}
+      
+      printf("cmd was %x, going to snes main loop\n", cmd);
+
+      if(romprops.has_msu1 && msu1_loop())
+      {
+         prepare_reset();
+         continue;
       }
-      if(snes_reset_state) {
-	reset_count++;
-      } else {
-	sram_reliable();
-	snes_main_loop();
+
+      cmd=0;
+      uint8_t snes_reset_prev=0, snes_reset_now=0, snes_reset_state=0;
+      uint16_t reset_count=0;
+      while(fpga_test() == FPGA_TEST_TOKEN)
+      {
+         cli_entrycheck();
+         sleep_ms(250);
+         sram_reliable();
+         printf("%s ", get_cic_statename(get_cic_state()));
+         if(reset_changed)
+         {
+            printf("reset\n");
+            reset_changed = 0;
+            fpga_reset_srtc_state();
+         }
+         snes_reset_now=get_snes_reset();
+         if(snes_reset_now)
+         {
+	         if(!snes_reset_prev)
+	         {
+	            printf("RESET BUTTON DOWN\n");
+	            snes_reset_state=1;
+	            reset_count=0;
+	         }
+         }
+         else
+         {
+	         if(snes_reset_prev)
+	         {
+	            printf("RESET BUTTON UP\n");
+	            snes_reset_state=0;
+	         }
+         }
+         if(snes_reset_state)
+         {
+         	reset_count++;
+         }
+         else
+         {
+	         sram_reliable();
+	         snes_main_loop();
+         }
+         if(reset_count>4)
+         {
+	         reset_count=0;
+            prepare_reset();
+	         break;
+         }
+         snes_reset_prev = snes_reset_now;
       }
-      if(reset_count>4) {
-	reset_count=0;
-        prepare_reset();
-	break;
+
+      /* fpga test fail: panic */
+      if(fpga_test() != FPGA_TEST_TOKEN)
+      {
+         led_panic();
       }
-      snes_reset_prev = snes_reset_now;
-    }
-    /* fpga test fail: panic */
-    if(fpga_test() != FPGA_TEST_TOKEN){
-      led_panic();
-    }
-    /* else reset */
-  }
+      /* else reset */
+   }
 }
 

src/memory.c

@@ -182,7 +182,7 @@ uint32_t load_rom(uint8_t* filename, uint32_t base_addr, uint8_t flags) {
   UINT count=0;
   tick_t ticksstart, ticks_total=0;
   ticksstart=getticks();
-  printf("%s\n", filename);
+  printf("Loading: %s\n", filename);
   file_open(filename, FA_READ);
   if(file_res) {
     uart_putc('?');
@@ -470,6 +470,99 @@ void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val) {
   FPGA_DESELECT();
 }
 
+/* memtest functions */
+uint8_t memtest_checkvalue(uint8_t value)
+{
+   uint8_t ret = 0;
+   uint32_t idx, lasterr = 0, errwas = 0, errcount = 0;
+   uint8_t data;
+   set_saveram_mask(0x0);
+   set_rom_mask(0x0);
+   printf("%s: Set memory to 0x%02X...\n", __func__, value);
+   sram_memset(0x00000, 0x1000000, value);
+   printf("Checking... [");
+   
+   set_mcu_addr(0x0);
+   
+   FPGA_SELECT();
+   FPGA_WAIT_RDY();
+   FPGA_TX_BYTE(0x88);
+   for(idx = 0; idx < 0x1000000; idx++)
+   {
+      FPGA_WAIT_RDY();
+      data = FPGA_RX_BYTE();
+      if ((idx % 0x100000) == 0)
+         uart_putc('.');
+
+      if ((idx % 0x10000) == 0)
+         toggle_read_led();
+
+      if (data != value)
+      {
+         //printf("%06x [%02x],", idx, data);
+         lasterr = idx;
+         errwas = data;
+         errcount++;
+         writeled(1);
+         ret = 0xFF;
+      }
+   }
+   printf("]\n");
+   if (errcount > 0)
+      printf("Found %d error(s) - last @ %x [%02x]\n", errcount, lasterr, errwas);
+
+   FPGA_DESELECT(); 
+   return ret;
+}
+
+uint8_t fpga_check(uint8_t value)
+{
+   uint8_t ret = 0, read;
+   FPGA_SELECT();
+   FPGA_WAIT_RDY();
+   FPGA_TX_BYTE(0xFF);
+   FPGA_TX_BYTE(value);
+   FPGA_TX_BYTE(value);
+   read = FPGA_RX_BYTE();
+   if (read != value)
+   {
+      printf("%02x != %02x!!\n", value, read);
+      ret = 0xFF;
+   }
+   FPGA_DESELECT();
+   return ret;
+}
+
+uint8_t sram_memtest(void)
+{
+   uint32_t ret;
+   printf("%s: Start memory test...\n", __func__);
+   writeled(0);
+   printf("Check FPGA Communication..\n");
+   printf("fpga_test   =   %02X\n", fpga_test());
+      
+   printf("fpga_status = %04X\n", fpga_status());
+   
+   ret  = fpga_check(0x00);
+   ret |= fpga_check(0xFF);
+   ret |= fpga_check(0xAA);
+   ret |= fpga_check(0x55);
+   if (ret != 0x00)
+   {
+      printf("Error communicating with FPGA...\n");
+      //return ret;
+   }
+    
+   
+    
+   ret  = memtest_checkvalue(0x00);
+   ret |= memtest_checkvalue(0xFF);
+   ret |= memtest_checkvalue(0xAA);
+   ret |= memtest_checkvalue(0x55);
+
+   return ret;
+}
+
 uint64_t sram_gettime(uint32_t base_addr) {
   set_mcu_addr(base_addr);
   FPGA_SELECT();

src/memory.h

@@ -71,4 +71,6 @@ uint8_t sram_reliable(void);
 void sram_memset(uint32_t base_addr, uint32_t len, uint8_t val);
 uint64_t sram_gettime(uint32_t base_addr);
 
+uint8_t sram_memtest(void);
+
 #endif

src/openocd-usb.cfg

@@ -5,8 +5,14 @@
 #
 
 interface ft2232
-ft2232_vid_pid 0x0403 0x6010
-ft2232_device_desc "Dual RS232"
-ft2232_layout "oocdlink"
-ft2232_latency 2
+ft2232_vid_pid 0x15ba 0x0003
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout "olimex-jtag"
+
+
+#interface ft2232
+#ft2232_vid_pid 0x0403 0x6010
+#ft2232_device_desc "Dual RS232"
+#ft2232_layout "oocdlink"
+#ft2232_latency 2
 #adapter_khz 10

src/snes.c

@@ -165,6 +165,7 @@ void get_selected_name(uint8_t* fn) {
 }
 
 void snes_bootprint(void* msg) {
+  printf("snes_boot: %s\n",msg);
   sram_writeblock(msg, SRAM_CMD_ADDR, 33);
 }
 

src/tests/Makefile

@@ -138,7 +138,8 @@ CFLAGS += $(CDEFS) $(CINCS)
 CFLAGS += -O$(OPT)
 CFLAGS += $(CPUFLAGS) -nostartfiles
 #CFLAGS += -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
-CFLAGS += -Wall -Wstrict-prototypes -Werror
+CFLAGS += -Wall -Wstrict-prototypes
+#-Werror
 CFLAGS += -Wa,-adhlns=$(OBJDIR)/$(<:.c=.lst)
 CFLAGS += -I$(OBJDIR)
 CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))

verilog/sd2snes/ipcore_dir/dac_buf.v

@@ -1,29 +1,28 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used             *
-*     solely for design, simulation, implementation and creation of            *
-*     design files limited to Xilinx devices or technologies. Use              *
-*     with non-Xilinx devices or technologies is expressly prohibited          *
-*     and immediately terminates your license.                                 *
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
-*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
-*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
-*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
-*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
-*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
-*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
-*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
-*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
-*     FOR A PARTICULAR PURPOSE.                                                *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
 *                                                                              *
-*     Xilinx products are not intended for use in life support                 *
-*     appliances, devices, or systems. Use in such applications are            *
-*     expressly prohibited.                                                    *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
 *                                                                              *
-*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file dac_buf.v when simulating
@@ -57,7 +56,7 @@ output [31 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_1 #(
+  BLK_MEM_GEN_V6_3 #(
     .C_ADDRA_WIDTH(11),
     .C_ADDRB_WIDTH(9),
     .C_ALGORITHM(1),
@@ -69,6 +68,7 @@ output [31 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/dac_buf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.1
-# Date: Mon Jun 13 22:11:22 2011
+# Xilinx Core Generator version 13.4
+# Date: Tue May 15 16:23:22 2012
 #
 ##############################################################
 #
@@ -12,12 +12,16 @@
 #
 ##############################################################
 #
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
+#
+##############################################################
+#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Advanced
+SET designentry = Verilog
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Foundation_ISE
@@ -29,10 +33,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = true
+SET vhdlsim = false
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -49,6 +53,7 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
+CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -95,7 +100,7 @@ CSET write_width_a=8
 CSET write_width_b=32
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+MISC pkg_timestamp=2011-10-21T13:54:23Z
 # END Extra information
 GENERATE
-# CRC: 70eef295
+# CRC: e5078255

verilog/sd2snes/ipcore_dir/dac_buf.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="dac_buf.ngc" xil_pn:type="FILE_NGC">
@@ -26,13 +26,7 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
-    </file>
+    <file xil_pn:name="dac_buf.vhd" xil_pn:type="FILE_VHDL"/>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/msu_databuf.v

@@ -1,29 +1,28 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used             *
-*     solely for design, simulation, implementation and creation of            *
-*     design files limited to Xilinx devices or technologies. Use              *
-*     with non-Xilinx devices or technologies is expressly prohibited          *
-*     and immediately terminates your license.                                 *
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
-*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
-*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
-*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
-*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
-*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
-*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
-*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
-*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
-*     FOR A PARTICULAR PURPOSE.                                                *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
 *                                                                              *
-*     Xilinx products are not intended for use in life support                 *
-*     appliances, devices, or systems. Use in such applications are            *
-*     expressly prohibited.                                                    *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
 *                                                                              *
-*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file msu_databuf.v when simulating
@@ -57,7 +56,7 @@ output [7 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_1 #(
+  BLK_MEM_GEN_V6_3 #(
     .C_ADDRA_WIDTH(14),
     .C_ADDRB_WIDTH(14),
     .C_ALGORITHM(1),
@@ -69,6 +68,7 @@ output [7 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/msu_databuf.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.1
-# Date: Mon Jun 13 22:13:20 2011
+# Xilinx Core Generator version 13.4
+# Date: Tue May 15 16:26:06 2012
 #
 ##############################################################
 #
@@ -12,12 +12,16 @@
 #
 ##############################################################
 #
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
+#
+##############################################################
+#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Advanced
+SET designentry = Verilog
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Foundation_ISE
@@ -29,10 +33,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = true
+SET vhdlsim = false
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -49,6 +53,7 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
+CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -95,7 +100,7 @@ CSET write_width_a=8
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+MISC pkg_timestamp=2011-10-21T13:54:23Z
 # END Extra information
 GENERATE
-# CRC: eabbe14d
+# CRC: cbebd26a

verilog/sd2snes/ipcore_dir/msu_databuf.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="msu_databuf.ngc" xil_pn:type="FILE_NGC">
@@ -26,13 +26,7 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="msu_databuf.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
-    </file>
+    <file xil_pn:name="msu_databuf.vhd" xil_pn:type="FILE_VHDL"/>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/upd77c25_datram.v

@@ -1,29 +1,28 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used             *
-*     solely for design, simulation, implementation and creation of            *
-*     design files limited to Xilinx devices or technologies. Use              *
-*     with non-Xilinx devices or technologies is expressly prohibited          *
-*     and immediately terminates your license.                                 *
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
-*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
-*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
-*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
-*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
-*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
-*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
-*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
-*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
-*     FOR A PARTICULAR PURPOSE.                                                *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
 *                                                                              *
-*     Xilinx products are not intended for use in life support                 *
-*     appliances, devices, or systems. Use in such applications are            *
-*     expressly prohibited.                                                    *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
 *                                                                              *
-*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file upd77c25_datram.v when simulating
@@ -63,7 +62,7 @@ output [7 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_1 #(
+  BLK_MEM_GEN_V6_3 #(
     .C_ADDRA_WIDTH(10),
     .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
@@ -75,6 +74,7 @@ output [7 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/upd77c25_datram.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.1
-# Date: Sun Jun 19 20:18:04 2011
+# Xilinx Core Generator version 13.4
+# Date: Wed May 16 07:50:33 2012
 #
 ##############################################################
 #
@@ -12,12 +12,16 @@
 #
 ##############################################################
 #
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
+#
+##############################################################
+#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Advanced
+SET designentry = Verilog
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Other
@@ -29,10 +33,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = true
+SET vhdlsim = false
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -49,6 +53,7 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
+CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -95,7 +100,7 @@ CSET write_width_a=16
 CSET write_width_b=8
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+MISC pkg_timestamp=2011-10-21T13:54:23Z
 # END Extra information
 GENERATE
-# CRC: 78e2bfe1
+# CRC: 94c2e5cc

verilog/sd2snes/ipcore_dir/upd77c25_datram.xise

@@ -12,12 +12,12 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="upd77c25_datram.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="upd77c25_datram.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -26,13 +26,7 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="upd77c25_datram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
-    </file>
+    <file xil_pn:name="upd77c25_datram.vhd" xil_pn:type="FILE_VHDL"/>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/upd77c25_datrom.v

@@ -1,29 +1,28 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used             *
-*     solely for design, simulation, implementation and creation of            *
-*     design files limited to Xilinx devices or technologies. Use              *
-*     with non-Xilinx devices or technologies is expressly prohibited          *
-*     and immediately terminates your license.                                 *
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
-*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
-*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
-*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
-*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
-*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
-*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
-*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
-*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
-*     FOR A PARTICULAR PURPOSE.                                                *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
 *                                                                              *
-*     Xilinx products are not intended for use in life support                 *
-*     appliances, devices, or systems. Use in such applications are            *
-*     expressly prohibited.                                                    *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
 *                                                                              *
-*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file upd77c25_datrom.v when simulating
@@ -57,7 +56,7 @@ output [15 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_1 #(
+  BLK_MEM_GEN_V6_3 #(
     .C_ADDRA_WIDTH(11),
     .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
@@ -69,6 +68,7 @@ output [15 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/upd77c25_datrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.1
-# Date: Wed Jun 22 21:30:01 2011
+# Xilinx Core Generator version 13.4
+# Date: Wed May 16 07:43:52 2012
 #
 ##############################################################
 #
@@ -12,12 +12,16 @@
 #
 ##############################################################
 #
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
+#
+##############################################################
+#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Advanced
+SET designentry = Verilog
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Other
@@ -29,10 +33,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = true
+SET vhdlsim = false
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -49,6 +53,7 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
+CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -95,7 +100,7 @@ CSET write_width_a=16
 CSET write_width_b=16
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+MISC pkg_timestamp=2011-10-21T13:54:23Z
 # END Extra information
 GENERATE
-# CRC: 7b2b203b
+# CRC: 4c89ee28

verilog/sd2snes/ipcore_dir/upd77c25_datrom.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="upd77c25_datrom.ngc" xil_pn:type="FILE_NGC">
@@ -26,13 +26,7 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="upd77c25_datrom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
-    </file>
+    <file xil_pn:name="upd77c25_datrom.vhd" xil_pn:type="FILE_VHDL"/>
   </files>
 
   <properties>

verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.v

@@ -1,29 +1,28 @@
 /*******************************************************************************
-*     This file is owned and controlled by Xilinx and must be used             *
-*     solely for design, simulation, implementation and creation of            *
-*     design files limited to Xilinx devices or technologies. Use              *
-*     with non-Xilinx devices or technologies is expressly prohibited          *
-*     and immediately terminates your license.                                 *
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
 *                                                                              *
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
-*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
-*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
-*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
-*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
-*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
-*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
-*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
-*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
 *     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
 *     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
-*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
-*     FOR A PARTICULAR PURPOSE.                                                *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
 *                                                                              *
-*     Xilinx products are not intended for use in life support                 *
-*     appliances, devices, or systems. Use in such applications are            *
-*     expressly prohibited.                                                    *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
 *                                                                              *
-*     (c) Copyright 1995-2011 Xilinx, Inc.                                     *
+*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
 *     All rights reserved.                                                     *
 *******************************************************************************/
 // You must compile the wrapper file upd77c25_pgmrom.v when simulating
@@ -57,7 +56,7 @@ output [23 : 0] doutb;
 
 // synthesis translate_off
 
-  BLK_MEM_GEN_V6_1 #(
+  BLK_MEM_GEN_V6_3 #(
     .C_ADDRA_WIDTH(11),
     .C_ADDRB_WIDTH(11),
     .C_ALGORITHM(1),
@@ -69,6 +68,7 @@ output [23 : 0] doutb;
     .C_DEFAULT_DATA("0"),
     .C_DISABLE_WARN_BHV_COLL(0),
     .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
     .C_FAMILY("spartan3"),
     .C_HAS_AXI_ID(0),
     .C_HAS_ENA(0),

verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xco

@@ -1,7 +1,7 @@
 ##############################################################
 #
-# Xilinx Core Generator version 13.1
-# Date: Wed Jun 22 21:31:49 2011
+# Xilinx Core Generator version 13.4
+# Date: Wed May 16 08:14:01 2012
 #
 ##############################################################
 #
@@ -12,12 +12,16 @@
 #
 ##############################################################
 #
+#  Generated from component: xilinx.com:ip:blk_mem_gen:6.3
+#
+##############################################################
+#
 # BEGIN Project Options
 SET addpads = false
 SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
-SET designentry = Advanced
+SET designentry = Verilog
 SET device = xc3s400
 SET devicefamily = spartan3
 SET flowvendor = Other
@@ -29,10 +33,10 @@ SET removerpms = false
 SET simulationfiles = Behavioral
 SET speedgrade = -4
 SET verilogsim = true
-SET vhdlsim = true
+SET vhdlsim = false
 # END Project Options
 # BEGIN Select
-SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.1
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.3
 # END Select
 # BEGIN Parameters
 CSET additional_inputs_for_power_estimation=false
@@ -49,6 +53,7 @@ CSET disable_collision_warnings=false
 CSET disable_out_of_range_warnings=false
 CSET ecc=false
 CSET ecctype=No_ECC
+CSET enable_32bit_address=false
 CSET enable_a=Always_Enabled
 CSET enable_b=Always_Enabled
 CSET error_injection_type=Single_Bit_Error_Injection
@@ -95,7 +100,7 @@ CSET write_width_a=24
 CSET write_width_b=24
 # END Parameters
 # BEGIN Extra information
-MISC pkg_timestamp=2011-02-03T22:20:43.000Z
+MISC pkg_timestamp=2011-10-21T13:54:23Z
 # END Extra information
 GENERATE
-# CRC: b11006ad
+# CRC: 4fd43971

verilog/sd2snes/ipcore_dir/upd77c25_pgmrom.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="upd77c25_pgmrom.ngc" xil_pn:type="FILE_NGC">
@@ -26,13 +26,7 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="upd77c25_pgmrom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
-    </file>
+    <file xil_pn:name="upd77c25_pgmrom.vhd" xil_pn:type="FILE_VHDL"/>
   </files>
 
   <properties>

verilog/sd2snes/sd2snes.xise

@@ -12,7 +12,7 @@
     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
   </header>
 
-  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
 
   <files>
     <file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">