336 lines
7.5 KiB
C
336 lines
7.5 KiB
C
/* sd2snes - SD card based universal cartridge for the SNES
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Copyright (C) 2009-2010 Maximilian Rehkopf <otakon@gmx.net>
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AVR firmware portion
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Inspired by and based on code from sd2iec, written by Ingo Korb et al.
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See sdcard.c|h, config.h.
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FAT file system access based on code by ChaN, Jim Brain, Ingo Korb,
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see ff.c|h.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License only.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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memory.c: RAM operations
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*/
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#include <stdint.h>
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#include <avr/pgmspace.h>
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#include <util/delay.h>
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#include "config.h"
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#include "uart.h"
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#include "fpga.h"
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#include "crc16.h"
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#include "ff.h"
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#include "fileops.h"
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#include "spi.h"
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#include "fpga_spi.h"
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#include "avrcompat.h"
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#include "led.h"
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#include "smc.h"
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#include "fpga_spi.h"
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#include "memory.h"
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#include "snes.h"
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char* hex = "0123456789ABCDEF";
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void sram_hexdump(uint32_t addr, uint32_t len) {
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static uint8_t buf[16];
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uint32_t ptr;
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for(ptr=0; ptr < len; ptr += 16) {
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sram_readblock((void*)buf, ptr+addr, 16);
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uart_trace(buf, 0, 16);
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}
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}
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void sram_writebyte(uint8_t val, uint32_t addr) {
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x91); // WRITE
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spiTransferByte(val);
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spiTransferByte(0x00); // dummy
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spi_none();
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}
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uint8_t sram_readbyte(uint32_t addr) {
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x81); // READ
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spiTransferByte(0x00); // dummy
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uint8_t val = spiTransferByte(0x00);
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spi_none();
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return val;
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}
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void sram_writeshort(uint16_t val, uint32_t addr) {
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x91); // WRITE
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spiTransferByte(val&0xff); // 7-0
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spiTransferByte((val>>8)&0xff); // 15-8
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spiTransferByte(0x00); // dummy
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spi_none();
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}
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void sram_writelong(uint32_t val, uint32_t addr) {
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x91); // WRITE
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spiTransferByte(val&0xff); // 7-0
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spiTransferByte((val>>8)&0xff); // 15-8
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spiTransferByte((val>>16)&0xff); // 23-15
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spiTransferByte((val>>24)&0xff); // 31-24
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spiTransferByte(0x00); // dummy
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spi_none();
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}
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uint16_t sram_readshort(uint32_t addr) {
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x81);
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spiTransferByte(0x00);
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uint32_t val = spiTransferByte(0x00);
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val |= ((uint32_t)spiTransferByte(0x00)<<8);
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spi_none();
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return val;
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}
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uint32_t sram_readlong(uint32_t addr) {
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x81);
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spiTransferByte(0x00);
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uint32_t count=0;
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uint32_t val = spiTransferByte(count & 0xff);
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count++;
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val |= ((uint32_t)spiTransferByte(count & val)<<8);
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count++;
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val |= ((uint32_t)spiTransferByte(count & val)<<16);
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count++;
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val |= ((uint32_t)spiTransferByte(count & val)<<24);
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count++;
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spi_none();
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return val;
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}
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void sram_readblock(void* buf, uint32_t addr, uint16_t size) {
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uint16_t count=size;
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uint8_t* tgt = buf;
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x81); // READ
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spiTransferByte(0x00); // dummy
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while(count--) {
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*(tgt++) = spiTransferByte(0x00);
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}
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spi_none();
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}
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void sram_writeblock(void* buf, uint32_t addr, uint16_t size) {
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uint16_t count=size;
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uint8_t* src = buf;
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set_avr_addr(addr);
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spi_fpga();
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spiTransferByte(0x91); // WRITE
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while(count--) {
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spiTransferByte(*src++);
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}
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spiTransferByte(0x00); // dummy
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spi_none();
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}
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uint32_t load_rom(uint8_t* filename, uint32_t base_addr) {
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// uint8_t dummy;
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UINT bytes_read;
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DWORD filesize;
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UINT count=0;
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file_open(filename, FA_READ);
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filesize = file_handle.fsize;
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smc_id(&romprops);
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set_avr_addr(base_addr);
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dprintf("no nervous breakdown beyond this point! or else!\n");
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if(file_res) {
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uart_putc('?');
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uart_putc(0x30+file_res);
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return 0;
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}
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f_lseek(&file_handle, romprops.offset);
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spi_none();
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for(;;) {
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SPI_OFFLOAD=1;
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spi_none();
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bytes_read = file_read();
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if (file_res || !bytes_read) break;
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if(!(count++ % 8)) {
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// toggle_busy_led();
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bounce_busy_led();
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uart_putc('.');
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}
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/* spi_fpga();
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spiTransferByte(0x91); // write w/ increment
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if(!(count++ % 8)) {
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// toggle_busy_led();
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bounce_busy_led();
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uart_putc('.');
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}
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for(int j=0; j<bytes_read; j++) {
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// spiTransferByte(file_buf[j]);
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SPDR = file_buf[j];
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loop_until_bit_is_set(SPSR, SPIF);
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dummy = SPDR;
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}
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spiTransferByte(0x00); // dummy tx for increment+write pulse */
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}
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file_close();
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spi_none();
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set_avr_mapper(romprops.mapper_id);
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uart_puthex(romprops.header.map);
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uart_putc(0x30+romprops.mapper_id);
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uint32_t rammask;
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uint32_t rommask;
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if(filesize > (romprops.romsize_bytes + romprops.offset)) {
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romprops.romsize_bytes <<= 1;
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}
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if(romprops.header.ramsize == 0) {
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rammask = 0;
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} else {
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rammask = romprops.ramsize_bytes - 1;
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}
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rommask = romprops.romsize_bytes - 1;
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uart_putc(' ');
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uart_puthex(romprops.header.ramsize);
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uart_putc('-');
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uart_puthexlong(rammask);
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uart_putc(' ');
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uart_puthex(romprops.header.romsize);
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uart_putc('-');
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uart_puthexlong(rommask);
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set_saveram_mask(rammask);
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set_rom_mask(rommask);
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return (uint32_t)filesize;
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}
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uint32_t load_sram(uint8_t* filename, uint32_t base_addr) {
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set_avr_addr(base_addr);
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UINT bytes_read;
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DWORD filesize;
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file_open(filename, FA_READ);
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filesize = file_handle.fsize;
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if(file_res) return 0;
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for(;;) {
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// FPGA_SS_HIGH();
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// SPI_SS_LOW();
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SPI_OFFLOAD=1;
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bytes_read = file_read();
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// SPI_SS_HIGH();
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if (file_res || !bytes_read) break;
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// FPGA_SS_LOW();
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/* spiTransferByte(0x91);
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for(int j=0; j<bytes_read; j++) {
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spiTransferByte(file_buf[j]);
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}
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spiTransferByte(0x00); // dummy tx
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FPGA_SS_HIGH(); // */
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}
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file_close();
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return (uint32_t)filesize;
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}
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void save_sram(uint8_t* filename, uint32_t sram_size, uint32_t base_addr) {
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uint32_t count = 0;
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uint32_t num = 0;
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spi_none();
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file_open(filename, FA_CREATE_ALWAYS | FA_WRITE);
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if(file_res) {
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uart_putc(0x30+file_res);
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}
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while(count<sram_size) {
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set_avr_addr(base_addr+count);
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spi_fpga();
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spiTransferByte(0x81); // read
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spiTransferByte(0); // dummy
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for(int j=0; j<sizeof(file_buf); j++) {
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file_buf[j] = spiTransferByte(0x00);
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count++;
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}
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spi_none();
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num = file_write();
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if(file_res) {
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uart_putc(0x30+file_res);
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}
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}
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file_close();
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}
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uint32_t calc_sram_crc(uint32_t base_addr, uint32_t size) {
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uint8_t data;
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uint32_t count;
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uint16_t crc;
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crc=0;
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crc_valid=1;
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set_avr_addr(base_addr);
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spi_fpga();
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spiTransferByte(0x81);
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spiTransferByte(0x00);
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for(count=0; count<size; count++) {
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data = spiTransferByte(0);
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if(get_snes_reset()) {
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crc_valid = 0;
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break;
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}
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crc += crc16_update(crc, &data, 1);
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}
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spi_none();
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return crc;
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}
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uint8_t sram_reliable() {
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uint16_t score=0;
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uint32_t val;
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// uint32_t val = sram_readlong(SRAM_SCRATCHPAD);
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uint8_t result = 0;
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/* while(score<SRAM_RELIABILITY_SCORE) {
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if(sram_readlong(SRAM_SCRATCHPAD)==val) {
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score++;
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} else {
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set_pwr_led(0);
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score=0;
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}
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}*/
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for(uint16_t i = 0; i < SRAM_RELIABILITY_SCORE; i++) {
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val=sram_readlong(SRAM_SCRATCHPAD);
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if(val==0x12345678) {
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score++;
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// } else {
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// dprintf("i=%d val=%08lX\n", i, val);
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}
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}
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if(score<SRAM_RELIABILITY_SCORE) {
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result = 0;
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// dprintf("score=%d\n", score);
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} else {
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result = 1;
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}
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set_pwr_led(result);
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return result;
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}
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