53 lines
1.2 KiB
Verilog
53 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 22:40:46 12/20/2010
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// Design Name:
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// Module Name: clk_test
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clk_test(
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input clk,
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input sysclk,
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output [31:0] snes_sysclk_freq
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);
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reg [31:0] snes_sysclk_freq_r;
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assign snes_sysclk_freq = snes_sysclk_freq_r;
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reg [31:0] sysclk_counter;
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reg [31:0] sysclk_value;
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initial snes_sysclk_freq_r = 32'hFFFFFFFF;
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initial sysclk_counter = 0;
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initial sysclk_value = 0;
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reg [1:0] sysclk_sreg;
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always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
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wire sysclk_rising = (sysclk_sreg == 2'b01);
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always @(posedge clk) begin
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if(sysclk_counter < 96000000) begin
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sysclk_counter <= sysclk_counter + 1;
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if(sysclk_rising) sysclk_value <= sysclk_value + 1;
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end else begin
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snes_sysclk_freq_r <= sysclk_value;
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sysclk_counter <= 0;
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sysclk_value <= 0;
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end
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end
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endmodule
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