181 lines
3.2 KiB
Verilog
181 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:11:58 05/13/2009
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// Design Name: main
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// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/tf_main.v
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// Project Name: sd2snes
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: main
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tf_main;
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// Inputs
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reg CLK;
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reg [2:0] MAPPER;
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reg [23:0] SNES_ADDR;
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reg SNES_READ;
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reg SNES_WRITE;
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reg SNES_CS;
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reg AVR_ENA;
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// Outputs
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wire [20:0] SRAM_ADDR;
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wire [3:0] ROM_SEL;
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wire SRAM_OE;
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wire SRAM_WE;
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wire SNES_DATABUS_OE;
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wire SNES_DATABUS_DIR;
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wire MODE;
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// Bidirs
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wire [7:0] SNES_DATA;
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wire [7:0] SRAM_DATA;
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wire [7:0] AVR_DATA;
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reg [7:0] SRAM_DATA_BUF;
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reg [7:0] SNES_DATA_BUF;
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SCK = 0;
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MOSI = 0;
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SSEL = 1;
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input_data = 0;
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// Wait 100 ns for global reset to finish
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#100;
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// Add stimulus here
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SSEL = 0;
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MOSI=1;
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#100 SCK=1;
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#100 SCK=0;
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MOSI=0;
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#100 SCK=1;
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#100 SCK=0;
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MOSI=0;
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#100 SCK=1;
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#100 SCK=0;
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MOSI=1;
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#100 SCK=1;
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#100 SCK=0;
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MOSI=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#200;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#200;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SCK=1;
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#100 SCK=0;
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#100 SSEL=1;
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end
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always begin
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#19 clk = ~clk;
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end
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// Instantiate the Unit Under Test (UUT)
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main uut (
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.CLKIN(CLK),
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.MAPPER(MAPPER),
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.SNES_ADDR(SNES_ADDR),
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.SNES_READ(SNES_READ),
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.SNES_WRITE(SNES_WRITE),
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.SNES_CS(SNES_CS),
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.SNES_DATA(SNES_DATA),
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.SRAM_DATA(SRAM_DATA),
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.SRAM_ADDR(SRAM_ADDR),
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.ROM_SEL(ROM_SEL),
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.SRAM_OE(SRAM_OE),
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.SRAM_WE(SRAM_WE),
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.AVR_ENA(AVR_ENA),
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.SNES_DATABUS_OE(SNES_DATABUS_OE),
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.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
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.MODE(MODE)
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);
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assign SRAM_DATA = SRAM_DATA_BUF;
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initial begin
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// Initialize Inputs
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CLK = 1;
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MAPPER = 0;
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SNES_ADDR = 24'h223456;
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SNES_READ = 1;
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SNES_WRITE = 1;
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SNES_CS = 0;
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AVR_ENA = 1;
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SRAM_DATA_BUF = 8'hff;
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// Wait for global reset to finish
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#276;
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SNES_ADDR <= 24'h123456;
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SNES_READ <= 0;
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#176;
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SNES_READ <= 1;
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#100;
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SNES_WRITE <= 0;
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#176;
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SNES_WRITE <= 1;
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#100;
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SNES_READ <= 0;
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#276;
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// AVR_READ <= 1;
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// Add stimulus here
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end
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always
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#23 CLK <= ~CLK;
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// always begin
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// end
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endmodule
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