883 lines
26 KiB
Verilog
883 lines
26 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:14:37 10/13/2011
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// Design Name:
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// Module Name: cx4
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module cx4(
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input [7:0] DI,
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output [7:0] DO,
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input [12:0] ADDR,
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input CS,
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input SNES_VECT_EN,
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input nRD,
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input nWR,
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input CLK,
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input [23:0] DATROM_DI,
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input DATROM_WE,
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input [9:0] DATROM_ADDR,
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input [7:0] BUS_DI,
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output [23:0] BUS_ADDR,
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output BUS_RRQ,
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input BUS_RDY,
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output cx4_active
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);
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reg [2:0] cx4_busy;
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parameter BUSY_CACHE = 2'b00;
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parameter BUSY_DMA = 2'b01;
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parameter BUSY_CPU = 2'b10;
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wire datram_enable = CS & (ADDR[11:0] < 12'hc00);
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wire mmio_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] < 5'b10011);
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wire status_enable = CS & (ADDR[12:5] == 8'b11111010) & (ADDR[4:0] >= 5'b10011);
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wire vector_enable = (CS & (ADDR[12:5] == 8'b11111011)) | (cx4_active & SNES_VECT_EN);
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wire gpr_enable = CS & (&(ADDR[12:7]) && ADDR[5:4] != 2'b11);
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wire pgmrom_enable = CS & (ADDR[12:5] == 8'b11110000);
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wire [7:0] DATRAM_DO;
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reg [7:0] MMIO_DOr;
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wire [7:0] MMIO_DO;
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wire [7:0] STATUS_DO;
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wire [7:0] VECTOR_DO;
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wire [7:0] GPR_DO;
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assign DO = datram_enable ? DATRAM_DO
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: mmio_enable ? MMIO_DO
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: status_enable ? STATUS_DO
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: vector_enable ? VECTOR_DO
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: gpr_enable ? GPR_DO
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: 8'h00;
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/* 0x1f40 - 0x1f52: MMIO
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SNES: 8 bits / CX4: various */
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reg [23:0] cx4_mmio_dmasrc;
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reg [15:0] cx4_mmio_dmalen;
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reg [23:0] cx4_mmio_dmatgt;
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reg cx4_mmio_cachepage;
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reg [23:0] cx4_mmio_pgmoff;
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reg [1:0] cx4_mmio_savepage;
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reg [14:0] cx4_mmio_pgmpage;
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reg [7:0] cx4_mmio_pc;
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reg [7:0] cx4_mmio_r1f50;
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reg cx4_mmio_r1f51;
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reg cx4_mmio_r1f52;
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/* 0x1f53 - 0x1f5f: status register */
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assign cx4_active = |cx4_busy;
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/* 0x1f60 - 0x1f7f: reset vectors */
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reg [7:0] vector [31:0];
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/* 0x1f80 - 0x1faf (0x1fc0 - 0x1fef): general purpose register file
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SNES: 8 bits / CX4: 24 bits */
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reg [7:0] gpr [47:0];
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wire [47:0] cpu_mul_result;
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reg [14:0] cx4_mmio_pagemem[1:0];
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reg [23:0] const [15:0];
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reg [14:0] cachetag [1:0];
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reg [1:0] cachevalid;
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reg [14:0] cache_pgmpage;
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reg [14:0] cpu_cache_pgmpage;
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reg cache_cachepage;
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reg cpu_cache_cachepage;
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reg cpu_cache_done;
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reg [7:0] cpu_pc_stack [7:0];
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reg [7:0] cpu_page_stack;
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initial begin
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cache_pgmpage = 15'b0;
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cpu_cache_pgmpage = 15'b0;
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cache_cachepage = 1'b0;
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cpu_cache_cachepage = 1'b0;
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cpu_cache_done = 1'b0;
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cachetag[0] = 14'h0000;
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cachetag[1] = 14'h0000;
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cachevalid = 2'b00;
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cx4_busy = 3'b000;
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cx4_mmio_pgmoff = 24'h000000;
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cx4_mmio_pgmpage = 15'h0000;
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cx4_mmio_dmasrc = 24'h000000;
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cx4_mmio_dmalen = 16'h0000;
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cx4_mmio_dmatgt = 24'h000000;
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cx4_mmio_savepage = 2'b00;
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const[0] = 24'h000000;
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const[1] = 24'hffffff;
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const[2] = 24'h00ff00;
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const[3] = 24'hff0000;
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const[4] = 24'h00ffff;
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const[5] = 24'hffff00;
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const[6] = 24'h800000;
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const[7] = 24'h7fffff;
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const[8] = 24'h008000;
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const[9] = 24'h007fff;
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const[10] = 24'hff7fff;
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const[11] = 24'hffff7f;
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const[12] = 24'h010000;
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const[13] = 24'hfeffff;
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const[14] = 24'h000100;
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const[15] = 24'h00feff;
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cpu_pc_stack[0] = 8'b0;
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cpu_pc_stack[1] = 8'b0;
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cpu_pc_stack[2] = 8'b0;
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cpu_pc_stack[3] = 8'b0;
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cpu_pc_stack[4] = 8'b0;
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cpu_pc_stack[5] = 8'b0;
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cpu_pc_stack[6] = 8'b0;
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cpu_pc_stack[7] = 8'b0;
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cpu_page_stack = 8'b0;
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end
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assign MMIO_DO = MMIO_DOr;
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assign VECTOR_DO = vector [ADDR[4:0]];
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assign GPR_DO = gpr [ADDR[5:0]];
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assign STATUS_DO = {1'b0, cx4_active, 4'b0000, ~cx4_active, 1'b0};
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reg [7:0] DIr;
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always @(posedge CLK) DIr <= DI;
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reg [4:0] datram_enable_sreg;
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initial datram_enable_sreg = 5'b11111;
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always @(posedge CLK) datram_enable_sreg <= {datram_enable_sreg[3:0], datram_enable};
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reg [5:0] nWR_sreg;
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always @(posedge CLK) nWR_sreg <= {nWR_sreg[4:0], nWR};
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wire WR_EN = (nWR_sreg[5:0] == 6'b000001);
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wire DATRAM_WR_EN = datram_enable & WR_EN;
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wire MMIO_WR_EN = mmio_enable & WR_EN;
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wire VECTOR_WR_EN = vector_enable & WR_EN;
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wire GPR_WR_EN = gpr_enable & WR_EN;
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reg [23:0] cpu_idb; // tmp register for reg file read
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/* Need to cache when:
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1f48 is written
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AND (selected cache page is invalid
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OR selected cache page does not contain requested page already)
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*/
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reg CACHE_TRIG_ENr;
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reg CACHE_TRIG_EN2r;
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reg cpu_cache_en;
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initial begin
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CACHE_TRIG_ENr = 1'b0;
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CACHE_TRIG_EN2r = 1'b0;
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cpu_cache_en = 1'b0;
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end
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always @(posedge CLK) CACHE_TRIG_EN2r <= CACHE_TRIG_ENr;
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wire CACHE_TRIG_EN = CACHE_TRIG_EN2r;
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reg DMA_TRIG_ENr;
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initial DMA_TRIG_ENr = 1'b0;
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wire DMA_TRIG_EN = DMA_TRIG_ENr;
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reg CACHE_BUS_RRQr;
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reg DMA_BUS_RRQr;
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reg cpu_bus_rq;
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initial begin
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CACHE_BUS_RRQr = 1'b0;
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DMA_BUS_RRQr = 1'b0;
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cpu_bus_rq = 1'b0;
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end
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assign BUS_RRQ = CACHE_BUS_RRQr | DMA_BUS_RRQr | cpu_bus_rq;
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reg cpu_page;
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reg [14:0] cpu_p;
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reg [7:0] cpu_pc;
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reg [23:0] cpu_a;
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reg fl_n;
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reg fl_z;
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reg fl_c;
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reg cpu_go_en_r;
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initial cpu_go_en_r = 1'b0;
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initial begin
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cx4_mmio_r1f50 = 8'h33;
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cx4_mmio_r1f51 = 1'b0;
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cx4_mmio_r1f52 = 1'b1;
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end
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always @(posedge CLK) begin
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case (ADDR[4:0])
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5'h00: MMIO_DOr <= cx4_mmio_dmasrc[7:0]; // 1f40
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5'h01: MMIO_DOr <= cx4_mmio_dmasrc[15:8]; // 1f41
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5'h02: MMIO_DOr <= cx4_mmio_dmasrc[23:16]; // 1f42
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5'h03: MMIO_DOr <= cx4_mmio_dmalen[7:0]; // 1f43
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5'h04: MMIO_DOr <= cx4_mmio_dmalen[15:8]; // 1f44
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5'h05: MMIO_DOr <= cx4_mmio_dmatgt[7:0]; // 1f45
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5'h06: MMIO_DOr <= cx4_mmio_dmatgt[15:8]; // 1f46
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5'h07: MMIO_DOr <= cx4_mmio_dmatgt[23:16]; // 1f47
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5'h08: MMIO_DOr <= {7'b0, cx4_mmio_cachepage};
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5'h09: MMIO_DOr <= cx4_mmio_pgmoff[7:0]; // 1f49
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5'h0a: MMIO_DOr <= cx4_mmio_pgmoff[15:8]; // 1f4a
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5'h0b: MMIO_DOr <= cx4_mmio_pgmoff[23:16]; // 1f4b
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5'h0c: MMIO_DOr <= {6'b0, cx4_mmio_savepage}; // 1f4c
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5'h0d: MMIO_DOr <= cx4_mmio_pgmpage[7:0]; // 1f4d
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5'h0e: MMIO_DOr <= {1'b0, cx4_mmio_pgmpage[14:8]}; // 1f4e
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5'h0f: MMIO_DOr <= cx4_mmio_pc; // 1f4f
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5'h10: MMIO_DOr <= cx4_mmio_r1f50; // 1f50
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5'h11: MMIO_DOr <= {7'b0, cx4_mmio_r1f51}; // 1f51
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5'h12: MMIO_DOr <= {7'b0, cx4_mmio_r1f52}; // 1f52
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default: MMIO_DOr <= 8'hff;
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endcase
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end
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always @(posedge CLK) begin
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if(MMIO_WR_EN) begin
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case(ADDR[4:0])
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5'h00: cx4_mmio_dmasrc[7:0] <= DIr; // 1f40
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5'h01: cx4_mmio_dmasrc[15:8] <= DIr; // 1f41
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5'h02: cx4_mmio_dmasrc[23:16] <= DIr; // 1f42
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5'h03: cx4_mmio_dmalen[7:0] <= DIr; // 1f43
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5'h04: cx4_mmio_dmalen[15:8] <= DIr; // 1f44
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5'h05: cx4_mmio_dmatgt[7:0] <= DIr; // 1f45
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5'h06: cx4_mmio_dmatgt[15:8] <= DIr; // 1f46
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5'h07: begin
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cx4_mmio_dmatgt[23:16] <= DIr; // 1f47
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DMA_TRIG_ENr <= 1'b1;
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end
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5'h08: begin
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cx4_mmio_cachepage <= DIr[0]; // 1f48
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CACHE_TRIG_ENr <= 1'b1;
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end
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5'h09: cx4_mmio_pgmoff[7:0] <= DIr; // 1f49
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5'h0a: cx4_mmio_pgmoff[15:8] <= DIr; // 1f4a
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5'h0b: cx4_mmio_pgmoff[23:16] <= DIr; // 1f4b
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5'h0c: begin
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cx4_mmio_savepage <= DIr[1:0];
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if(DIr[0]) cx4_mmio_pagemem[0] <= cx4_mmio_pgmpage;
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if(DIr[1]) cx4_mmio_pagemem[1] <= cx4_mmio_pgmpage;
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end
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5'h0d: cx4_mmio_pgmpage[7:0] <= DIr; // 1f4d
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5'h0e: cx4_mmio_pgmpage[14:8] <= DIr[6:0]; // 1f4e
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5'h0f: begin
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cx4_mmio_pc <= DIr; // 1f4f
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if(cx4_mmio_savepage[0]
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&& cx4_mmio_pagemem[0] == cx4_mmio_pgmpage)
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cx4_mmio_cachepage <= 1'b0;
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else if(cx4_mmio_savepage[1]
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&& cx4_mmio_pagemem[1] == cx4_mmio_pgmpage)
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cx4_mmio_cachepage <= 1'b1;
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cpu_go_en_r <= 1'b1;
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end
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5'h10: cx4_mmio_r1f50 <= DIr & 8'h77; // 1f50
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5'h11: cx4_mmio_r1f51 <= DIr[0]; // 1f51
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5'h12: cx4_mmio_r1f52 <= DIr[0]; // 1f52
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endcase
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end else begin
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CACHE_TRIG_ENr <= 1'b0;
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DMA_TRIG_ENr <= 1'b0;
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cpu_go_en_r <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(VECTOR_WR_EN) vector[ADDR[4:0]] <= DIr;
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end
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reg [4:0] CACHE_ST;
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parameter ST_CACHE_IDLE = 5'b00001;
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parameter ST_CACHE_START = 5'b00010;
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parameter ST_CACHE_WAIT = 5'b00100;
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parameter ST_CACHE_ADDR = 5'b01000;
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parameter ST_CACHE_END = 5'b10000;
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initial CACHE_ST = ST_CACHE_IDLE;
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reg [4:0] DMA_ST;
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parameter ST_DMA_IDLE = 5'b00001;
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parameter ST_DMA_START = 5'b00010;
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parameter ST_DMA_WAIT = 5'b00100;
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parameter ST_DMA_ADDR = 5'b01000;
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parameter ST_DMA_END = 5'b10000;
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initial DMA_ST = ST_DMA_IDLE;
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reg [23:0] CACHE_SRC_ADDRr;
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wire [22:0] MAPPED_CACHE_SRC_ADDR = {CACHE_SRC_ADDRr[23:16],CACHE_SRC_ADDRr[14:0]};
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reg [23:0] DMA_SRC_ADDRr;
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wire [22:0] MAPPED_DMA_SRC_ADDR = {DMA_SRC_ADDRr[23:16],DMA_SRC_ADDRr[14:0]};
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wire [22:0] MAPPED_CPU_BUS_ADDR;
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assign BUS_ADDR = cx4_busy[BUSY_CACHE] ? MAPPED_CACHE_SRC_ADDR
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: cx4_busy[BUSY_DMA] ? MAPPED_DMA_SRC_ADDR
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: MAPPED_CPU_BUS_ADDR;
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reg cx4_pgmrom_we;
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initial cx4_pgmrom_we = 1'b0;
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reg [9:0] cx4_pgmrom_addr;
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reg [19:0] cache_count;
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initial cache_count = 20'b0;
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always @(posedge CLK) begin
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case(CACHE_ST)
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ST_CACHE_IDLE: begin
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if(CACHE_TRIG_EN
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& (~cachevalid[cx4_mmio_cachepage]
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| |(cachetag[cx4_mmio_cachepage] ^ cx4_mmio_pgmpage))) begin
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CACHE_ST <= ST_CACHE_START;
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cache_pgmpage <= cx4_mmio_pgmpage;
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cache_cachepage <= cx4_mmio_cachepage;
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end else if(cpu_cache_en
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& (~cachevalid[~cpu_page]
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| |(cachetag[~cpu_page] ^ cpu_p))) begin
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CACHE_ST <= ST_CACHE_START;
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cache_pgmpage <= cpu_p;
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cache_cachepage <= ~cpu_page;
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cx4_busy[BUSY_CACHE] <= 1'b1;
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end
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else CACHE_ST <= ST_CACHE_IDLE;
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end
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ST_CACHE_START: begin
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cx4_busy[BUSY_CACHE] <= 1'b1;
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CACHE_SRC_ADDRr <= cx4_mmio_pgmoff + {cache_pgmpage, 9'b0};
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cx4_pgmrom_addr <= {cache_cachepage, 9'b0};
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CACHE_ST <= ST_CACHE_WAIT;
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cache_count <= 10'b0;
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CACHE_BUS_RRQr <= 1'b1;
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end
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ST_CACHE_WAIT: begin
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CACHE_BUS_RRQr <= 1'b0;
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if(~CACHE_BUS_RRQr & BUS_RDY) begin
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CACHE_ST <= ST_CACHE_ADDR;
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cx4_pgmrom_we <= 1'b1;
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cache_count <= cache_count + 1;
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end else CACHE_ST <= ST_CACHE_WAIT;
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end
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ST_CACHE_ADDR: begin
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cx4_pgmrom_we <= 1'b0;
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CACHE_SRC_ADDRr <= CACHE_SRC_ADDRr + 1;
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cx4_pgmrom_addr <= cx4_pgmrom_addr + 1;
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if(cache_count == 9'h1ff) begin
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cx4_busy[BUSY_CACHE] <= 1'b0;
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cachetag[cache_cachepage] <= cache_pgmpage;
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cachevalid[cache_cachepage] <= 1'b1;
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CACHE_ST <= ST_CACHE_IDLE;
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end else begin
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CACHE_BUS_RRQr <= 1'b1;
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CACHE_ST <= ST_CACHE_WAIT;
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end
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end
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endcase
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end
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reg cx4_dma_datram_we;
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reg cx4_cpu_datram_we;
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initial cx4_dma_datram_we = 1'b0;
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initial cx4_cpu_datram_we = 1'b0;
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wire cx4_datram_we = cx4_dma_datram_we | cx4_cpu_datram_we;
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reg [11:0] cx4_dma_datram_addr;
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reg [11:0] cx4_cpu_datram_addr;
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wire [11:0] cx4_datram_addr = cx4_busy[BUSY_DMA] ? cx4_dma_datram_addr : cx4_cpu_datram_addr;
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reg [23:0] cx4_cpu_datram_di;
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wire [7:0] cx4_datram_di = cx4_busy[BUSY_DMA] ? BUS_DI : cx4_cpu_datram_di;
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reg [15:0] dma_count;
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initial dma_count = 16'b0;
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always @(posedge CLK) begin
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case(DMA_ST)
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ST_DMA_IDLE: begin
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if(DMA_TRIG_EN) begin
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DMA_ST <= ST_DMA_START;
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end else DMA_ST <= ST_DMA_IDLE;
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end
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ST_DMA_START: begin
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cx4_busy[BUSY_DMA] <= 1'b1;
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DMA_SRC_ADDRr <= cx4_mmio_dmasrc;
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cx4_dma_datram_addr <= (cx4_mmio_dmatgt & 24'h000fff);
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DMA_ST <= ST_DMA_WAIT;
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dma_count <= cx4_mmio_dmalen;
|
|
DMA_BUS_RRQr <= 1'b1;
|
|
end
|
|
ST_DMA_WAIT: begin
|
|
DMA_BUS_RRQr <= 1'b0;
|
|
if(~DMA_BUS_RRQr & BUS_RDY) begin
|
|
DMA_ST <= ST_DMA_ADDR;
|
|
cx4_dma_datram_we <= 1'b1;
|
|
dma_count <= dma_count - 1;
|
|
end else DMA_ST <= ST_DMA_WAIT;
|
|
end
|
|
ST_DMA_ADDR: begin
|
|
cx4_dma_datram_we <= 1'b0;
|
|
DMA_SRC_ADDRr <= DMA_SRC_ADDRr + 1;
|
|
cx4_dma_datram_addr <= cx4_dma_datram_addr + 1;
|
|
if(dma_count == 16'h0000) begin
|
|
cx4_busy[BUSY_DMA] <= 1'b0;
|
|
DMA_ST <= ST_DMA_IDLE;
|
|
end else begin
|
|
DMA_BUS_RRQr <= 1'b1;
|
|
DMA_ST <= ST_DMA_WAIT;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
|
|
/***************************
|
|
=========== CPU ===========
|
|
***************************/
|
|
reg [4:0] CPU_STATE;
|
|
reg [2:0] cpu_sp;
|
|
initial cpu_sp = 3'b000;
|
|
wire [15:0] cpu_op_w;
|
|
reg [15:0] cpu_op;
|
|
reg [23:0] cpu_busdata;
|
|
reg [23:0] cpu_romdata;
|
|
reg [23:0] cpu_ramdata;
|
|
reg [23:0] cpu_busaddr;
|
|
assign MAPPED_CPU_BUS_ADDR = {cpu_busaddr[23:16], cpu_busaddr[14:0]};
|
|
reg [23:0] cpu_romaddr;
|
|
reg [23:0] cpu_ramaddr;
|
|
reg [23:0] cpu_acch;
|
|
reg [23:0] cpu_accl;
|
|
reg [23:0] cpu_mul_src;
|
|
reg [24:0] cpu_alu_res;
|
|
reg [23:0] cpu_dummy;
|
|
reg [23:0] cpu_tmp;
|
|
|
|
reg [23:0] cpu_sa; // tmp register for shifted accumulator
|
|
|
|
wire [9:0] cx4_datrom_addr = cpu_a[9:0];
|
|
wire [23:0] cx4_datrom_do;
|
|
wire [7:0] cx4_datram_do;
|
|
|
|
parameter ST_CPU_IDLE = 5'b00001;
|
|
parameter ST_CPU_0 = 5'b00010;
|
|
parameter ST_CPU_1 = 5'b00100;
|
|
parameter ST_CPU_2 = 5'b01000;
|
|
parameter ST_CPU_3 = 5'b10000;
|
|
|
|
initial CPU_STATE = ST_CPU_IDLE;
|
|
|
|
parameter OP_NOP = 5'b00000;
|
|
parameter OP_JP = 5'b00001;
|
|
parameter OP_SKIP = 5'b00010;
|
|
parameter OP_RT = 5'b00011;
|
|
parameter OP_LD = 5'b00100;
|
|
parameter OP_ST = 5'b00101;
|
|
parameter OP_SWP = 5'b00110;
|
|
parameter OP_RDROM = 5'b00111;
|
|
parameter OP_RDRAM = 5'b01000;
|
|
parameter OP_WRRAM = 5'b01001;
|
|
parameter OP_ALU = 5'b01010;
|
|
parameter OP_MUL = 5'b01011;
|
|
parameter OP_WAI = 5'b01100;
|
|
parameter OP_BUS = 5'b01101;
|
|
parameter OP_CMP = 5'b01110;
|
|
parameter OP_SEX = 5'b01111;
|
|
parameter OP_HLT = 5'b10000;
|
|
|
|
wire [6:0] op_id = cpu_op_w[15:10];
|
|
reg [7:0] op_param;
|
|
reg [4:0] op;
|
|
reg [1:0] op_sa;
|
|
reg op_imm;
|
|
reg op_p;
|
|
reg op_call;
|
|
reg op_jump;
|
|
reg condtrue;
|
|
|
|
always @(posedge CLK) begin
|
|
if(cpu_go_en_r) cx4_busy[BUSY_CPU] <= 1'b1;
|
|
else if(op == OP_HLT) cx4_busy[BUSY_CPU] <= 1'b0;
|
|
end
|
|
|
|
always @(posedge CLK) begin
|
|
case(op_sa)
|
|
2'b00: cpu_sa <= cpu_a;
|
|
2'b01: cpu_sa <= cpu_a << 1;
|
|
2'b10: cpu_sa <= cpu_a << 8;
|
|
2'b11: cpu_sa <= cpu_a << 16;
|
|
endcase
|
|
end
|
|
|
|
reg jp_docache;
|
|
initial jp_docache = 1'b0;
|
|
|
|
always @(posedge CLK) begin
|
|
case(CPU_STATE)
|
|
ST_CPU_IDLE: begin
|
|
if(cpu_go_en_r) begin
|
|
cpu_pc <= cx4_mmio_pc;
|
|
cpu_page <= cx4_mmio_cachepage;
|
|
cpu_p <= cx4_mmio_pgmpage;
|
|
op <= OP_NOP;
|
|
CPU_STATE <= ST_CPU_2;
|
|
end
|
|
else CPU_STATE <= ST_CPU_IDLE;
|
|
end
|
|
ST_CPU_0: begin // Phase 0:
|
|
cpu_cache_en <= 1'b0;
|
|
if(op == OP_HLT) begin
|
|
CPU_STATE <= ST_CPU_IDLE;
|
|
end
|
|
else CPU_STATE <= ST_CPU_1;
|
|
case(op)
|
|
OP_JP: begin
|
|
case(cpu_op[11:10])
|
|
2'b10: condtrue <= 1'b1;
|
|
2'b11: condtrue <= fl_z;
|
|
2'b00: condtrue <= fl_c;
|
|
2'b01: condtrue <= fl_n;
|
|
endcase
|
|
if(op_p && !jp_docache) begin
|
|
jp_docache <= 1'b1;
|
|
cpu_cache_en <= 1'b1;
|
|
end
|
|
end
|
|
OP_SKIP: begin
|
|
case(cpu_op[9:8])
|
|
2'b01: condtrue <= (fl_c == cpu_op[0]);
|
|
2'b10: condtrue <= (fl_z == cpu_op[0]);
|
|
2'b11: condtrue <= (fl_n == cpu_op[0]);
|
|
endcase
|
|
end
|
|
OP_LD, OP_ALU, OP_MUL, OP_CMP, OP_SEX: begin
|
|
if(op_imm) cpu_idb <= {16'b0, op_param};
|
|
else casex(op_param)
|
|
8'h00: cpu_idb <= cpu_a;
|
|
8'h01: cpu_idb <= cpu_acch;
|
|
8'h02: cpu_idb <= cpu_accl;
|
|
8'h03: cpu_idb <= cpu_busdata;
|
|
8'h08: cpu_idb <= cpu_romdata;
|
|
8'h0c: cpu_idb <= cpu_ramdata;
|
|
8'h13: cpu_idb <= cpu_busaddr;
|
|
8'h1c: cpu_idb <= cpu_ramaddr;
|
|
8'h5x: cpu_idb <= const[op_param[3:0]];
|
|
8'h6x: cpu_idb <= {gpr[op_param[3:0]*3+2],
|
|
gpr[op_param[3:0]*3+1],
|
|
gpr[op_param[3:0]*3]};
|
|
default: cpu_idb <= 24'b0;
|
|
endcase
|
|
end
|
|
OP_ST: begin
|
|
cpu_idb <= cpu_a;
|
|
end
|
|
OP_SWP: begin
|
|
cpu_idb <= cpu_a;
|
|
casex(op_param)
|
|
8'h00: cpu_tmp <= cpu_a;
|
|
8'h01: cpu_tmp <= cpu_acch;
|
|
8'h02: cpu_tmp <= cpu_accl;
|
|
8'h03: cpu_tmp <= cpu_busdata;
|
|
8'h08: cpu_tmp <= cpu_romdata;
|
|
8'h0c: cpu_tmp <= cpu_ramdata;
|
|
8'h13: cpu_tmp <= cpu_busaddr;
|
|
8'h1c: cpu_tmp <= cpu_ramaddr;
|
|
8'h5x: cpu_tmp <= const[op_param[3:0]];
|
|
8'h6x: cpu_tmp <= {gpr[op_param[3:0]*3+2],
|
|
gpr[op_param[3:0]*3+1],
|
|
gpr[op_param[3:0]*3]};
|
|
default: cpu_tmp <= 24'b0;
|
|
endcase
|
|
end
|
|
OP_RDRAM, OP_WRRAM: begin
|
|
if(op_imm) cx4_cpu_datram_addr <= {16'b0, op_param} + cpu_ramaddr;
|
|
else casex(op_param)
|
|
8'h00: cx4_cpu_datram_addr <= cpu_a;
|
|
8'h01: cx4_cpu_datram_addr <= cpu_acch;
|
|
8'h02: cx4_cpu_datram_addr <= cpu_accl;
|
|
8'h03: cx4_cpu_datram_addr <= cpu_busdata;
|
|
8'h08: cx4_cpu_datram_addr <= cpu_romdata;
|
|
8'h0c: cx4_cpu_datram_addr <= cpu_ramdata;
|
|
8'h13: cx4_cpu_datram_addr <= cpu_busaddr;
|
|
8'h1c: cx4_cpu_datram_addr <= cpu_ramaddr;
|
|
8'h5x: cx4_cpu_datram_addr <= const[op_param[3:0]];
|
|
8'h6x: cx4_cpu_datram_addr <= {gpr[op_param[3:0]*3+2],
|
|
gpr[op_param[3:0]*3+1],
|
|
gpr[op_param[3:0]*3]};
|
|
default: cx4_cpu_datram_addr <= 24'b0;
|
|
endcase
|
|
end
|
|
OP_BUS: cpu_bus_rq <= 1'b1;
|
|
endcase
|
|
end
|
|
ST_CPU_1: begin
|
|
CPU_STATE <= ST_CPU_2;
|
|
condtrue <= 1'b0;
|
|
case(op)
|
|
OP_JP: begin
|
|
cpu_cache_en <= 1'b0;
|
|
if(!cpu_cache_en && !cx4_busy[BUSY_CACHE]) begin
|
|
jp_docache <= 1'b0;
|
|
if(condtrue) begin
|
|
if(op_call) begin
|
|
cpu_page_stack[cpu_sp] <= cpu_page;
|
|
cpu_pc_stack[cpu_sp] <= cpu_pc + 1;
|
|
cpu_sp <= cpu_sp + 1;
|
|
end
|
|
cpu_pc <= op_param;
|
|
cpu_page <= cpu_page ^ op_p;
|
|
end else cpu_pc <= cpu_pc + 1;
|
|
end
|
|
end
|
|
OP_SKIP: begin
|
|
if(condtrue) cpu_pc <= cpu_pc + 2;
|
|
else cpu_pc <= cpu_pc + 1;
|
|
end
|
|
OP_RT: begin
|
|
cpu_page <= cpu_page_stack[cpu_sp - 1];
|
|
cpu_pc <= cpu_pc_stack[cpu_sp - 1];
|
|
cpu_sp <= cpu_sp - 1;
|
|
end
|
|
OP_WAI: if(BUS_RDY) cpu_pc <= cpu_pc + 1;
|
|
OP_BUS: begin
|
|
cpu_bus_rq <= 1'b0;
|
|
cpu_pc <= cpu_pc + 1;
|
|
end
|
|
default: cpu_pc <= cpu_pc + 1;
|
|
endcase
|
|
end
|
|
ST_CPU_2: begin
|
|
CPU_STATE <= ST_CPU_3;
|
|
case(op)
|
|
OP_LD: begin
|
|
casex(cpu_op[11:8])
|
|
4'b0x00: cpu_a <= cpu_idb;
|
|
4'b0x11: cpu_p <= cpu_idb;
|
|
4'b1100: cpu_p[7:0] <= op_param;
|
|
4'b1101: cpu_p[14:8] <= op_param;
|
|
endcase
|
|
end
|
|
OP_ST, OP_SWP: begin
|
|
casex(op_param)
|
|
8'h01: cpu_acch <= cpu_idb;
|
|
8'h02: cpu_accl <= cpu_idb;
|
|
8'h08: cpu_romdata <= cpu_idb;
|
|
8'h0c: cpu_ramdata <= cpu_idb;
|
|
8'h13: cpu_busaddr <= cpu_idb;
|
|
8'h1c: cpu_ramaddr <= cpu_idb;
|
|
endcase
|
|
if(op==OP_SWP) cpu_a <= cpu_tmp;
|
|
end
|
|
OP_RDROM: cpu_romdata <= cx4_datrom_do;
|
|
OP_RDRAM: begin
|
|
case(cpu_op[9:8])
|
|
2'b00: cpu_ramdata[7:0] <= cx4_datram_do;
|
|
2'b01: cpu_ramdata[15:8] <= cx4_datram_do;
|
|
2'b10: cpu_ramdata[23:16] <= cx4_datram_do;
|
|
endcase
|
|
end
|
|
OP_WRRAM: begin
|
|
case(cpu_op[9:8])
|
|
2'b00: cx4_cpu_datram_di <= cpu_ramdata[7:0];
|
|
2'b01: cx4_cpu_datram_di <= cpu_ramdata[15:8];
|
|
2'b10: cx4_cpu_datram_di <= cpu_ramdata[23:16];
|
|
endcase
|
|
cx4_cpu_datram_we <= 1'b1;
|
|
end
|
|
OP_CMP: begin
|
|
case(cpu_op[15:11])
|
|
5'b01001: cpu_alu_res <= cpu_idb - cpu_sa;
|
|
5'b01010: cpu_alu_res <= cpu_sa - cpu_idb;
|
|
endcase
|
|
end
|
|
OP_SEX: begin
|
|
case(cpu_op[9:8])
|
|
2'b01: cpu_alu_res <= {{16{cpu_idb[7]}}, cpu_idb[7:0]};
|
|
2'b10: cpu_alu_res <= {{8{cpu_idb[15]}}, cpu_idb[15:0]};
|
|
endcase
|
|
end
|
|
OP_ALU: begin
|
|
case(cpu_op[15:11])
|
|
5'b10000: cpu_alu_res <= cpu_sa + cpu_idb;
|
|
5'b10001: cpu_alu_res <= cpu_idb - cpu_sa;
|
|
5'b10010: cpu_alu_res <= cpu_sa - cpu_idb;
|
|
5'b10101: cpu_alu_res <= cpu_sa ^ cpu_idb;
|
|
5'b10110: cpu_alu_res <= cpu_sa & cpu_idb;
|
|
5'b10111: cpu_alu_res <= cpu_sa | cpu_idb;
|
|
5'b11000: cpu_alu_res <= cpu_a >> cpu_idb;
|
|
5'b11001: cpu_alu_res <= ($signed(cpu_a)) >>> cpu_idb;
|
|
5'b11010: {cpu_dummy, cpu_alu_res[23:0]} <= {cpu_a, cpu_a} >> cpu_idb;
|
|
5'b11011: cpu_alu_res <= cpu_a << cpu_idb;
|
|
endcase
|
|
end
|
|
endcase
|
|
end
|
|
ST_CPU_3: begin
|
|
CPU_STATE <= ST_CPU_0;
|
|
case(op)
|
|
OP_BUS: cpu_busaddr <= cpu_busaddr + 1;
|
|
OP_WRRAM: cx4_cpu_datram_we <= 1'b0;
|
|
OP_CMP: begin
|
|
fl_n <= cpu_alu_res[23];
|
|
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
|
fl_c <= ~cpu_alu_res[24];
|
|
end
|
|
OP_SEX: cpu_a <= cpu_alu_res[23:0];
|
|
OP_ALU: begin
|
|
cpu_a <= cpu_alu_res[23:0];
|
|
case(cpu_op[15:11])
|
|
5'b10000: begin
|
|
fl_n <= cpu_alu_res[23];
|
|
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
|
fl_c <= cpu_alu_res[24];
|
|
end
|
|
5'b10001, 5'b10010: begin
|
|
fl_n <= cpu_alu_res[23];
|
|
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
|
fl_c <= ~cpu_alu_res[24];
|
|
end
|
|
default: begin
|
|
fl_n <= cpu_alu_res[23];
|
|
fl_z <= cpu_alu_res[23:0] == 24'b0;
|
|
end
|
|
endcase
|
|
end
|
|
OP_MUL: begin
|
|
cpu_acch <= cpu_mul_result[47:24];
|
|
cpu_accl <= cpu_mul_result[23:0];
|
|
fl_z <= (cpu_mul_result == 48'b0);
|
|
fl_n <= cpu_mul_result[47];
|
|
end
|
|
endcase
|
|
cpu_op <= cpu_op_w;
|
|
casex(cpu_op_w[15:11])
|
|
5'b00000: op <= OP_NOP;
|
|
|
|
5'b00x01: op <= OP_JP;
|
|
5'b00x10: op <= OP_JP;
|
|
5'b00100: op <= OP_SKIP;
|
|
5'b00111: op <= OP_RT;
|
|
|
|
5'b01100: op <= OP_LD;
|
|
5'b01111: op <= OP_LD;
|
|
5'b11100: op <= OP_ST;
|
|
5'b11110: op <= OP_SWP;
|
|
|
|
5'b01110: op <= OP_RDROM;
|
|
5'b01101: op <= OP_RDRAM;
|
|
5'b11101: op <= OP_WRRAM;
|
|
|
|
5'b01001: op <= OP_CMP;
|
|
5'b01010: op <= OP_CMP;
|
|
5'b01011: op <= OP_SEX;
|
|
5'b10000: op <= OP_ALU;
|
|
5'b10001: op <= OP_ALU;
|
|
5'b10010: op <= OP_ALU;
|
|
5'b10101: op <= OP_ALU;
|
|
5'b10110: op <= OP_ALU;
|
|
5'b10111: op <= OP_ALU;
|
|
5'b11000: op <= OP_ALU;
|
|
5'b11001: op <= OP_ALU;
|
|
5'b11010: op <= OP_ALU;
|
|
5'b11011: op <= OP_ALU;
|
|
5'b10011: op <= OP_MUL;
|
|
|
|
5'b00011: op <= OP_WAI;
|
|
5'b01000: op <= OP_BUS;
|
|
|
|
5'b11111: op <= OP_HLT;
|
|
endcase
|
|
op_imm <= cpu_op_w[10];
|
|
op_p <= cpu_op_w[9];
|
|
op_call <= cpu_op_w[13];
|
|
op_param <= cpu_op_w[7:0];
|
|
op_sa <= cpu_op_w[9:8];
|
|
end
|
|
endcase
|
|
end
|
|
|
|
reg[2:0] BUSRD_STATE;
|
|
parameter ST_BUSRD_IDLE = 3'b001;
|
|
parameter ST_BUSRD_WAIT = 3'b010;
|
|
parameter ST_BUSRD_END = 3'b100;
|
|
initial BUSRD_STATE = ST_BUSRD_IDLE;
|
|
reg cpu_bus_rq2;
|
|
always @(posedge CLK) cpu_bus_rq2 <= cpu_bus_rq;
|
|
|
|
always @(posedge CLK) begin
|
|
if(CPU_STATE == ST_CPU_2
|
|
&& (op == OP_ST || op == OP_SWP)
|
|
&& op_param == 8'h03)
|
|
cpu_busdata <= cpu_idb;
|
|
else begin
|
|
case(BUSRD_STATE)
|
|
ST_BUSRD_IDLE: begin
|
|
if(cpu_bus_rq2) begin
|
|
BUSRD_STATE <= ST_BUSRD_WAIT;
|
|
end
|
|
end
|
|
ST_BUSRD_WAIT: begin
|
|
if(BUS_RDY) BUSRD_STATE <= ST_BUSRD_END;
|
|
else BUSRD_STATE <= ST_BUSRD_WAIT;
|
|
end
|
|
ST_BUSRD_END: begin
|
|
if(~cpu_busaddr[22]) cpu_busdata <= BUS_DI;
|
|
else cpu_busdata <= 8'h00;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// gpr write, either by CPU or by MMIO
|
|
always @(posedge CLK) begin
|
|
if(CPU_STATE == ST_CPU_2
|
|
&& (op == OP_ST || op == OP_SWP)
|
|
&& (op_param[7:4] == 4'h6)) begin
|
|
gpr[op_param[3:0]*3+2] <= cpu_idb[23:16];
|
|
gpr[op_param[3:0]*3+1] <= cpu_idb[15:8];
|
|
gpr[op_param[3:0]*3] <= cpu_idb[7:0];
|
|
end
|
|
else if(GPR_WR_EN) gpr[ADDR[5:0]] <= DIr;
|
|
end
|
|
|
|
/***************************
|
|
=========== MEM ===========
|
|
***************************/
|
|
cx4_datrom cx4_datrom (
|
|
.clka(CLK), // input clka
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.wea(DATROM_WE), // input [0 : 0] wea
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.addra(DATROM_ADDR), // input [9 : 0] addra
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.dina(DATROM_DI), // input [23 : 0] dina
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.clkb(CLK), // input clkb
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.addrb(cx4_datrom_addr), // input [9 : 0] addrb
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.doutb(cx4_datrom_do) // output [23 : 0] doutb
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);
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cx4_datram cx4_datram (
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.clka(CLK), // input clka
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.wea(DATRAM_WR_EN), // input [0 : 0] wea
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.addra(ADDR[11:0]), // input [11 : 0] addra
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.dina(DIr), // input [7 : 0] dina
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.douta(DATRAM_DO), // output [7 : 0] douta
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.clkb(CLK), // input clkb
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.web(cx4_datram_we), // input [0 : 0] web
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.addrb(cx4_datram_addr), // input [11 : 0] addrb
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.dinb(cx4_datram_di), // input [7 : 0] dinb
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.doutb(cx4_datram_do) // output [7 : 0] doutb
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);
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cx4_pgmrom cx4_pgmrom (
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.clka(CLK), // input clka
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.wea(cx4_pgmrom_we), // input [0 : 0] wea
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.addra(cx4_pgmrom_addr), // input [9 : 0] addra
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.dina(BUS_DI), // input [7 : 0] dina
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.clkb(CLK), // input clkb
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.addrb({cpu_page,cpu_pc}), // input [8 : 0] addrb
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.doutb(cpu_op_w) // output [15 : 0] doutb
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);
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cx4_mul cx4_mul (
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.clk(CLK), // input clk
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.a(cpu_a), // input [23 : 0] a
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.b(cpu_idb), // input [23 : 0] b
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.p(cpu_mul_result) // output [47 : 0] p
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);
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endmodule
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