121 lines
3.4 KiB
Verilog
121 lines
3.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 22:40:46 12/20/2010
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// Design Name:
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// Module Name: clk_test
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clk_test(
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input clk,
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input sysclk,
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input read,
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input write,
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input pawr,
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input pard,
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input refresh,
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input cpuclk,
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input romsel,
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output reg [31:0] snes_sysclk_freq,
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output reg [31:0] snes_read_freq,
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output reg [31:0] snes_write_freq,
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output reg [31:0] snes_pawr_freq,
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output reg [31:0] snes_pard_freq,
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output reg [31:0] snes_refresh_freq,
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output reg [31:0] snes_cpuclk_freq,
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output reg [31:0] snes_romsel_freq
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);
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reg [31:0] sysclk_counter;
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reg [31:0] sysclk_value;
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reg [31:0] read_value;
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reg [31:0] write_value;
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reg [31:0] pard_value;
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reg [31:0] pawr_value;
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reg [31:0] refresh_value;
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reg [31:0] cpuclk_value;
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reg [31:0] romsel_value;
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initial snes_sysclk_freq = 32'hFFFFFFFF;
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initial sysclk_counter = 0;
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initial sysclk_value = 0;
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initial read_value = 0;
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initial write_value = 0;
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initial pard_value = 0;
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initial pawr_value = 0;
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initial refresh_value = 0;
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initial cpuclk_value = 0;
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initial romsel_value = 0;
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reg [1:0] sysclk_sreg;
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reg [1:0] read_sreg;
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reg [1:0] write_sreg;
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reg [1:0] pard_sreg;
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reg [1:0] pawr_sreg;
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reg [1:0] refresh_sreg;
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reg [1:0] cpuclk_sreg;
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reg [1:0] romsel_sreg;
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always @(posedge clk) romsel_sreg <= {romsel_sreg[0], romsel};
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wire romsel_rising = (romsel_sreg == 2'b01);
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always @(posedge clk) cpuclk_sreg <= {cpuclk_sreg[0], cpuclk};
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wire cpuclk_rising = (cpuclk_sreg == 2'b01);
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always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
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wire sysclk_rising = (sysclk_sreg == 2'b01);
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always @(posedge clk) read_sreg <= {read_sreg[0], read};
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wire read_rising = (read_sreg == 2'b01);
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always @(posedge clk) write_sreg <= {write_sreg[0], write};
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wire write_rising = (write_sreg == 2'b01);
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always @(posedge clk) pard_sreg <= {pard_sreg[0], pard};
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wire pard_rising = (pard_sreg == 2'b01);
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always @(posedge clk) pawr_sreg <= {pawr_sreg[0], pawr};
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wire pawr_rising = (pawr_sreg == 2'b01);
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always @(posedge clk) refresh_sreg <= {refresh_sreg[0], refresh};
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wire refresh_rising = (refresh_sreg == 2'b01);
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always @(posedge clk) begin
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if(sysclk_counter < 96000000) begin
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sysclk_counter <= sysclk_counter + 1;
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if(sysclk_rising) sysclk_value <= sysclk_value + 1;
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if(read_rising) read_value <= read_value + 1;
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if(write_rising) write_value <= write_value + 1;
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if(pard_rising) pard_value <= pard_value + 1;
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if(pawr_rising) pawr_value <= pawr_value + 1;
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if(refresh_rising) refresh_value <= refresh_value + 1;
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if(cpuclk_rising) cpuclk_value <= cpuclk_value + 1;
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if(romsel_rising) romsel_value <= romsel_value + 1;
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end else begin
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snes_sysclk_freq <= sysclk_value;
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snes_read_freq <= read_value;
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snes_write_freq <= write_value;
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snes_pard_freq <= pard_value;
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snes_pawr_freq <= pawr_value;
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snes_refresh_freq <= refresh_value;
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snes_cpuclk_freq <= cpuclk_value;
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snes_romsel_freq <= romsel_value;
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sysclk_counter <= 0;
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sysclk_value <= 0;
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read_value <= 0;
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write_value <= 0;
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pard_value <= 0;
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pawr_value <= 0;
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refresh_value <= 0;
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cpuclk_value <= 0;
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romsel_value <= 0;
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end
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end
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endmodule
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