597 lines
16 KiB
Verilog
597 lines
16 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: main
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Master Control FSM
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//
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// Dependencies: address
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module main(
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/* input clock */
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input CLKIN,
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/* SNES signals */
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input [23:0] SNES_ADDR,
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input SNES_READ,
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input SNES_WRITE,
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input SNES_CS,
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inout [7:0] SNES_DATA,
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input SNES_CPU_CLK,
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input SNES_REFRESH,
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output SNES_IRQ,
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output SNES_DATABUS_OE,
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output SNES_DATABUS_DIR,
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input SNES_SYSCLK,
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input [7:0] SNES_PA,
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input SNES_PARD,
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input SNES_PAWR,
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/* SRAM signals */
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/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
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inout [15:0] ROM_DATA,
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output [22:0] ROM_ADDR,
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output ROM_CE,
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output ROM_OE,
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output ROM_WE,
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output ROM_BHE,
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output ROM_BLE,
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/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
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inout [7:0] RAM_DATA,
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output [18:0] RAM_ADDR,
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output RAM_OE,
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output RAM_WE,
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/* MCU signals */
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input SPI_MOSI,
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inout SPI_MISO,
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input SPI_SS,
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inout SPI_SCK,
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input MCU_OVR,
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output MCU_RDY,
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output DAC_MCLK,
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output DAC_LRCK,
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output DAC_SDOUT,
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/* SD signals */
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input [3:0] SD_DAT,
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inout SD_CMD,
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inout SD_CLK,
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/* debug */
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output p113_out
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);
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wire [31:0] snes_sysclk_freq;
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wire [31:0] snes_read_freq;
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wire [31:0] snes_write_freq;
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wire [31:0] snes_pard_freq;
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wire [31:0] snes_pawr_freq;
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wire [31:0] snes_refresh_freq;
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wire [31:0] snes_cpuclk_freq;
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wire [31:0] snes_romsel_freq;
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clk_test snes_clk_test (
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.clk(CLK2),
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.sysclk(SNES_SYSCLK),
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.read(SNES_READ),
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.write(SNES_WRITE),
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.pard(SNES_PARD),
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.pawr(SNES_PAWR),
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.refresh(SNES_REFRESH),
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.cpuclk(SNES_CPU_CLK),
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.romsel(SNES_CS),
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.snes_sysclk_freq(snes_sysclk_freq),
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.snes_read_freq(snes_read_freq),
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.snes_write_freq(snes_write_freq),
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.snes_pard_freq(snes_pard_freq),
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.snes_pawr_freq(snes_pawr_freq),
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.snes_refresh_freq(snes_refresh_freq),
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.snes_cpuclk_freq(snes_cpuclk_freq),
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.snes_romsel_freq(snes_romsel_freq)
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);
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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wire [31:0] spi_byte_cnt;
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wire [2:0] spi_bit_cnt;
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wire [23:0] MCU_ADDR;
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wire [2:0] MAPPER;
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wire [23:0] SAVERAM_MASK;
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wire [23:0] ROM_MASK;
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wire [7:0] SD_DMA_SRAM_DATA;
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wire [1:0] SD_DMA_TGT;
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wire [10:0] SD_DMA_PARTIAL_START;
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wire [10:0] SD_DMA_PARTIAL_END;
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wire [10:0] dac_addr;
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wire [23:0] ram0_addr;
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wire [18:0] ram1_addr;
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wire [7:0] PA_addr;
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wire [12:0] bram_addr;
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wire ROM_ADDR0;
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sd_dma snes_sd_dma(
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.CLK(CLK2),
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.SD_DAT(SD_DAT),
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.SD_CLK(SD_CLK),
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.SD_DMA_EN(SD_DMA_EN),
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.SD_DMA_STATUS(SD_DMA_STATUS),
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.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
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.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
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.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
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.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
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.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
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.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
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);
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wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
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dac snes_dac(
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.clkin(CLK2),
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.sysclk(SNES_SYSCLK),
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.mclk(DAC_MCLK),
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.lrck(DAC_LRCK),
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.sdout(DAC_SDOUT),
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.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
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.pgm_address(dac_addr),
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.pgm_data(SD_DMA_SRAM_DATA),
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.DAC_STATUS(DAC_STATUS),
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.play(dac_play),
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.reset(dac_reset)
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);
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spi snes_spi(
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.clk(CLK2),
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.MOSI(SPI_MOSI),
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.MISO(SPI_MISO),
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.SSEL(SPI_SS),
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.SCK(SPI_SCK),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.input_data(spi_input_data),
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.byte_cnt(spi_byte_cnt),
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.bit_cnt(spi_bit_cnt)
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);
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reg [7:0] MCU_DINr;
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wire [7:0] MCU_DOUT;
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wire [7:0] mcu_bram_data_in;
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wire [7:0] mcu_bram_data_out;
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wire [12:0] mcu_bram_addr;
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mcu_cmd snes_mcu_cmd(
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.clk(CLK2),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.mcu_mapper(MAPPER),
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.mcu_write(MCU_WRITE),
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.mcu_data_in(MCU_DINr),
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.mcu_data_out(MCU_DOUT),
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.spi_byte_cnt(spi_byte_cnt),
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.spi_bit_cnt(spi_bit_cnt),
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.spi_data_out(spi_input_data),
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.addr_out(MCU_ADDR),
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.saveram_mask_out(SAVERAM_MASK),
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.rom_mask_out(ROM_MASK),
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.SD_DMA_EN(SD_DMA_EN),
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.SD_DMA_STATUS(SD_DMA_STATUS),
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.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
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.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
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.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
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.SD_DMA_TGT(SD_DMA_TGT),
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.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
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.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
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.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
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.dac_addr_out(dac_addr),
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.DAC_STATUS(DAC_STATUS),
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// .dac_volume_out(dac_volume),
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// .dac_volume_latch_out(dac_vol_latch),
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.dac_play_out(dac_play),
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.dac_reset_out(dac_reset),
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.featurebits_out(featurebits),
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.mcu_rrq(MCU_RRQ),
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.mcu_wrq(MCU_WRQ),
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.mcu_rq_rdy(MCU_RDY),
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.ramsel_out(MCU_RAMSEL),
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.snes_sysclk_freq(snes_sysclk_freq),
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.snes_read_freq(snes_read_freq),
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.snes_write_freq(snes_write_freq),
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.snes_pard_freq(snes_pard_freq),
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.snes_pawr_freq(snes_pawr_freq),
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.snes_refresh_freq(snes_refresh_freq),
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.snes_cpuclk_freq(snes_cpuclk_freq),
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.snes_romsel_freq(snes_romsel_freq),
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.mcu_bram_addr(mcu_bram_addr),
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.mcu_bram_data_in(mcu_bram_data_in),
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.mcu_bram_data_out(mcu_bram_data_out),
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.mcu_bram_we(mcu_bram_we)
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);
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wire [7:0] DCM_STATUS;
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// dcm1: dfs 4x
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my_dcm snes_dcm(
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.CLKIN(CLKIN),
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.CLKFX(CLK2),
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.LOCKED(DCM_LOCKED),
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.RST(DCM_RST),
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.STATUS(DCM_STATUS)
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);
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assign DCM_RST=0;
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reg [5:0] SNES_READr;
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reg [5:0] SNES_WRITEr;
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reg [5:0] SNES_CPU_CLKr;
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wire SNES_RD_start = (SNES_READr == 6'b111110);
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wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
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wire SNES_WR_rising = (SNES_WRITEr == 6'b000001);
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wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
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wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
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always @(posedge CLK2) begin
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SNES_READr <= {SNES_READr[4:0], SNES_READ};
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SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
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SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
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end
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reg [7:0] ram0_bank;
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initial ram0_bank = 8'h00;
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reg ram0_linear;
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initial ram0_linear = 1'b0;
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address snes_addr(
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.CLK(CLK2),
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.SNES_ADDR(SNES_ADDR), // requested address from SNES
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.ram0_addr(ram0_addr), // Address to request from SRAM (active low)
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.ram1_addr(ram1_addr),
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.PA_addr(PA_addr),
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.bram_addr(bram_addr),
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.ram0_enable(ram0_enable),
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.ram1_enable(ram1_enable),
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.PA_enable(PA_enable),
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.bram_enable(bram_enable),
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.ram0_bank(ram0_bank),
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.ram0_linear(ram0_linear),
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.irq_enable(irq_enable),
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.bank_enable(bank_enable),
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.linear_enable(linear_enable)
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);
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always @(posedge CLK2) begin
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if(SNES_WR_rising && bank_enable) ram0_bank <= SNES_DATA;
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end
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always @(posedge CLK2) begin
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if(SNES_WR_rising && linear_enable) ram0_linear <= SNES_DATA[0];
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end
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reg [7:0] irq_count_r;
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initial irq_count_r = 8'b0;
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reg SNES_IRQr;
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initial SNES_IRQr = 0;
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always @(posedge CLK2) begin
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if(SNES_WR_rising & irq_enable) SNES_IRQr <= 1'b1;
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else if(irq_count_r == 8'h00) SNES_IRQr <= 1'b0;
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end
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always @(posedge CLK2) begin
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if(SNES_WR_rising & irq_enable) irq_count_r <= 8'h01;
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else irq_count_r <= irq_count_r + 1;
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end
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wire [7:0] bram_data_out;
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bram test_bram (
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.clka(CLK2), // input clka
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.wea(~SNES_WRITE & bram_enable), // input [0 : 0] wea
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.addra(bram_addr), // input [12 : 0] addra
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.dina(SNES_DATA), // input [7 : 0] dina
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.douta(bram_data_out), // output [7 : 0] douta
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.clkb(CLK2), // input clkb
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.web(mcu_bram_we), // input [0 : 0] web
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.addrb(mcu_bram_addr), // input [12 : 0] addrb
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.dinb(mcu_bram_data_out), // input [7 : 0] dinb
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.doutb(mcu_bram_data_in) // output [7 : 0] doutb
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);
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reg [1:0] SNES_PAWR_start_r;
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always @(posedge CLK2) SNES_PAWR_start_r <= {SNES_PAWR_start_r[0], SNES_PAWR};
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wire SNES_PAWR_start = (SNES_PAWR_start_r == 2'b01);
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wire [7:0] PA_data_out;
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PA test_PA (
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.clka(CLK2), // input clka
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.wea(SNES_PAWR_start), // input [0 : 0] wea
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.addra(SNES_PA), // input [7 : 0] addra
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.dina(SNES_DATA), // input [7 : 0] dina
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.clkb(CLK2), // input clkb
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.addrb(PA_addr), // input [7 : 0] addrb
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.doutb(PA_data_out) // output [7 : 0] doutb
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);
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parameter MODE_SNES = 1'b0;
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parameter MODE_MCU = 1'b1;
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parameter ST_IDLE = 18'b000000000000000001;
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parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
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parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
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parameter ST_SNES_RD_END = 18'b000000000000001000;
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parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
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parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
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parameter ST_SNES_WR_DATA = 18'b000000000001000000;
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parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
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parameter ST_SNES_WR_END = 18'b000000000100000000;
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parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
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parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
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parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
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parameter ST_MCU_RD_END = 18'b000001000000000000;
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parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
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parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
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parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
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parameter ST_MCU_WR_END = 18'b010000000000000000;
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parameter ROM_RD_WAIT = 4'h4;
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parameter ROM_RD_WAIT_MCU = 4'h6;
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parameter ROM_WR_WAIT1 = 4'h2;
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parameter ROM_WR_WAIT2 = 4'h3;
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parameter ROM_WR_WAIT_MCU = 4'h6;
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reg [17:0] STATE;
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initial STATE = ST_IDLE;
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reg [7:0] SNES_DINr;
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reg [7:0] ROM_DOUTr;
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reg [7:0] RAM_DOUTr;
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assign SNES_DATA = (!SNES_READ) ? (ram0_enable ? SNES_DINr
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:ram1_enable ? SNES_DINr
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:bram_enable ? bram_data_out
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:PA_enable ? PA_data_out
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:SNES_DINr /*(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])*/) : 8'bZ;
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reg [3:0] ST_MEM_DELAYr;
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reg MCU_RD_PENDr;
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reg MCU_WR_PENDr;
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reg [23:0] ROM_ADDRr;
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reg [18:0] RAM_ADDRr;
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reg NEED_SNES_ADDRr;
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always @(posedge CLK2) begin
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if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
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else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
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end
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wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
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assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : (ASSERT_SNES_ADDR) ? ram0_addr[23:1] : ROM_ADDRr[23:1];
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assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : (ASSERT_SNES_ADDR) ? ram0_addr[0] : ROM_ADDRr[0];
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assign RAM_ADDR = ASSERT_SNES_ADDR ? ram1_addr : RAM_ADDRr;
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reg ROM_WEr;
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initial ROM_WEr = 1'b1;
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reg RAM_WEr;
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initial RAM_WEr = 1'b1;
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reg RQ_MCU_RDYr;
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initial RQ_MCU_RDYr = 1'b1;
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assign MCU_RDY = RQ_MCU_RDYr;
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always @(posedge CLK2) begin
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if(MCU_RRQ) begin
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MCU_RD_PENDr <= 1'b1;
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RQ_MCU_RDYr <= 1'b0;
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end else if(MCU_WRQ) begin
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MCU_WR_PENDr <= 1'b1;
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RQ_MCU_RDYr <= 1'b0;
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end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
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MCU_RD_PENDr <= 1'b0;
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MCU_WR_PENDr <= 1'b0;
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RQ_MCU_RDYr <= 1'b1;
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end
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end
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reg snes_wr_cycle;
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wire ram_enable = ram0_enable | ram1_enable;
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always @(posedge CLK2) begin
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if(ram_enable & SNES_cycle_start & ~SNES_WR_start) begin
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STATE <= ST_SNES_RD_ADDR;
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end else if(ram_enable & SNES_WR_start) begin
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snes_wr_cycle <= 1'b1;
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STATE <= ST_SNES_WR_ADDR;
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end else begin
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case(STATE)
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ST_IDLE: begin
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if(ram0_enable) ROM_ADDRr <= ram0_addr;
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if(ram1_enable) RAM_ADDRr <= ram1_addr;
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if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
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else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
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else STATE <= ST_IDLE;
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end
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ST_SNES_RD_ADDR: begin
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STATE <= ST_SNES_RD_WAIT;
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ST_MEM_DELAYr <= ROM_RD_WAIT;
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end
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ST_SNES_RD_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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|
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
|
|
else STATE <= ST_SNES_RD_WAIT;
|
|
if(ram0_enable) begin
|
|
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
|
|
else SNES_DINr <= ROM_DATA[15:8];
|
|
end else if(ram1_enable) begin
|
|
SNES_DINr <= RAM_DATA[7:0];
|
|
end
|
|
end
|
|
ST_SNES_RD_END: begin
|
|
STATE <= ST_IDLE;
|
|
if(ram0_enable) begin
|
|
if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
|
|
else SNES_DINr <= ROM_DATA[15:8];
|
|
end else if(ram1_enable) begin
|
|
SNES_DINr <= RAM_DATA[7:0];
|
|
end
|
|
end
|
|
ST_SNES_WR_ADDR: begin
|
|
if(ram0_enable) ROM_WEr <= 1'b0;
|
|
if(ram1_enable) RAM_WEr <= 1'b0;
|
|
STATE <= ST_SNES_WR_WAIT1;
|
|
ST_MEM_DELAYr <= ROM_WR_WAIT1;
|
|
end
|
|
ST_SNES_WR_WAIT1: begin
|
|
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
|
|
else STATE <= ST_SNES_WR_WAIT1;
|
|
end
|
|
ST_SNES_WR_DATA: begin
|
|
if(ram0_enable) ROM_DOUTr <= SNES_DATA;
|
|
if(ram1_enable) RAM_DOUTr <= SNES_DATA;
|
|
ST_MEM_DELAYr <= ROM_WR_WAIT2;
|
|
STATE <= ST_SNES_WR_WAIT2;
|
|
end
|
|
ST_SNES_WR_WAIT2: begin
|
|
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
|
|
else STATE <= ST_SNES_WR_WAIT2;
|
|
end
|
|
ST_SNES_WR_END: begin
|
|
STATE <= ST_IDLE;
|
|
ROM_WEr <= 1'b1;
|
|
RAM_WEr <= 1'b1;
|
|
snes_wr_cycle <= 1'b0;
|
|
end
|
|
ST_MCU_RD_ADDR: begin
|
|
if(MCU_RAMSEL == 1'b0) ROM_ADDRr <= MCU_ADDR;
|
|
else RAM_ADDRr <= MCU_ADDR;
|
|
STATE <= ST_MCU_RD_WAIT;
|
|
ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
|
|
end
|
|
ST_MCU_RD_WAIT: begin
|
|
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
if(ST_MEM_DELAYr == 4'h0) begin
|
|
STATE <= ST_MCU_RD_WAIT2;
|
|
ST_MEM_DELAYr <= 4'h2;
|
|
end
|
|
else STATE <= ST_MCU_RD_WAIT;
|
|
if(MCU_RAMSEL == 1'b0) begin
|
|
if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
|
|
else MCU_DINr <= ROM_DATA[15:8];
|
|
end else MCU_DINr <= RAM_DATA;
|
|
end
|
|
ST_MCU_RD_WAIT2: begin
|
|
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
if(ST_MEM_DELAYr == 4'h0) begin
|
|
STATE <= ST_MCU_RD_END;
|
|
end else STATE <= ST_MCU_RD_WAIT2;
|
|
end
|
|
ST_MCU_RD_END: begin
|
|
STATE <= ST_IDLE;
|
|
end
|
|
ST_MCU_WR_ADDR: begin
|
|
if(MCU_RAMSEL == 1'b0) ROM_ADDRr <= MCU_ADDR;
|
|
else RAM_ADDRr <= MCU_ADDR;
|
|
STATE <= ST_MCU_WR_WAIT;
|
|
ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
|
|
if(MCU_RAMSEL == 1'b0) ROM_DOUTr <= MCU_DOUT;
|
|
else RAM_DOUTr <= MCU_DOUT;
|
|
if(MCU_RAMSEL == 1'b0)
|
|
ROM_WEr <= 1'b0;
|
|
else if(MCU_RAMSEL == 1'b1)
|
|
RAM_WEr <= 1'b0;
|
|
end
|
|
ST_MCU_WR_WAIT: begin
|
|
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
if(ST_MEM_DELAYr == 4'h0) begin
|
|
ROM_WEr <= 1'b1;
|
|
RAM_WEr <= 1'b1;
|
|
STATE <= ST_MCU_WR_WAIT2;
|
|
ST_MEM_DELAYr <= 4'h2;
|
|
end
|
|
else begin
|
|
STATE <= ST_MCU_WR_WAIT;
|
|
end
|
|
end
|
|
ST_MCU_WR_WAIT2: begin
|
|
ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
|
|
if(ST_MEM_DELAYr == 4'h0) begin
|
|
STATE <= ST_MCU_WR_END;
|
|
end else STATE <= ST_MCU_WR_WAIT2;
|
|
end
|
|
ST_MCU_WR_END: begin
|
|
STATE <= ST_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
assign ROM_DATA[7:0] = ROM_ADDR0
|
|
?(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
|
|
: (!ROM_WE ? ROM_DOUTr : 8'bZ)
|
|
)
|
|
:8'bZ;
|
|
|
|
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
|
|
:(SD_DMA_TO_ROM ? (!MCU_WRITE ? MCU_DOUT : 8'bZ)
|
|
: (!ROM_WE ? ROM_DOUTr : 8'bZ)
|
|
);
|
|
|
|
assign RAM_DATA = !RAM_WE ? RAM_DOUTr : 8'bZ;
|
|
|
|
assign ROM_WE = SD_DMA_TO_ROM
|
|
?MCU_WRITE
|
|
:ROM_WEr | (ASSERT_SNES_ADDR & ~(snes_wr_cycle & ram0_enable));
|
|
|
|
assign RAM_WE = RAM_WEr | (ASSERT_SNES_ADDR & ~(snes_wr_cycle & ram1_enable));
|
|
|
|
assign RAM_OE = 1'b0;
|
|
|
|
// OE always active. Overridden by WE when needed.
|
|
assign ROM_OE = 1'b0;
|
|
|
|
assign ROM_CE = 1'b0;
|
|
|
|
assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
|
|
assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
|
|
|
|
assign SNES_DATABUS_OE = PA_enable ? 1'b0
|
|
: bram_enable ? 1'b0
|
|
: (~SNES_PAWR & SNES_READ) ? 1'b0
|
|
: SNES_CS ? SNES_WRITE
|
|
:((SNES_CS)
|
|
|(!ram0_enable & !ram1_enable)
|
|
|(SNES_READ & SNES_WRITE)
|
|
);
|
|
|
|
assign SNES_DATABUS_DIR = ~SNES_READ ? 1'b1 : 1'b0;
|
|
|
|
assign IRQ_DIR = 1'b0;
|
|
assign SNES_IRQ = SNES_IRQr;
|
|
|
|
assign p113_out = 1'b0;
|
|
|
|
endmodule
|