73 lines
3.0 KiB
Verilog
73 lines
3.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 13:06:52 06/28/2009
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// Design Name:
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// Module Name: dcm
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module my_dcm (
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input CLKIN,
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output CLKFX,
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output LOCKED,
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input RST,
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output[7:0] STATUS
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);
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// DCM: Digital Clock Manager Circuit
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// Spartan-3
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// Xilinx HDL Language Template, version 11.1
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DCM #(
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.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
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.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
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.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
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.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
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.CLKIN_PERIOD(41.667), // Specify period of input clock
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.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
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.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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// an integer from 0 to 15
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.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
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.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
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.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
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.FACTORY_JF(16'hFFFF), // FACTORY JF values
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// .LOC("DCM_X0Y0"),
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.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
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.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
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) DCM_inst (
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.CLK0(CLK0), // 0 degree DCM CLK output
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.CLK180(CLK180), // 180 degree DCM CLK output
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.CLK270(CLK270), // 270 degree DCM CLK output
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.CLK2X(CLK2X), // 2X DCM CLK output
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.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
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.CLK90(CLK90), // 90 degree DCM CLK output
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.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
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.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
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.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
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.LOCKED(LOCKED), // DCM LOCK status output
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.PSDONE(PSDONE), // Dynamic phase adjust done output
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.STATUS(STATUS), // 8-bit DCM status bits output
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.CLKFB(CLKFB), // DCM clock feedback
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.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
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.PSCLK(PSCLK), // Dynamic phase adjust clock input
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.PSEN(PSEN), // Dynamic phase adjust enable input
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.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
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.RST(RST) // DCM asynchronous reset input
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);
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endmodule
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