145 lines
8.9 KiB
XML
145 lines
8.9 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="11.5" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="address.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="data.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="dcm.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="spi.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="tf_spi.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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<file xil_pn:name="main_tf2.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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<file xil_pn:name="avr_cmd.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="tf_main.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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<file xil_pn:name="dcm2.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="dcm_srl16.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="spi_dma.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="tf_spi_dma.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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<file xil_pn:name="tf_main_3.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device" xil_pn:value="xc3s200" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Done (Output Events)" xil_pn:value="6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Extra Effort" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Balanced" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="tq144" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Register Duplication" xil_pn:value="On" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="5" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="High" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
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<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/ikari/prj/sd2snes/verilog/sd2snes/smartxplorer_results/run9/maptimingextraeffortct3.xds" xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="sd2snes" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tf_main_3" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings>
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<binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
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</bindings>
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<libraries/>
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<partitions/>
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</project>
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