663 lines
19 KiB
Verilog
663 lines
19 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Engineer: ikari
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//
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// Create Date: 17:09:03 01/16/2011
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// Design Name:
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// Module Name: upd77c25
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// Project Name: sd2snes
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// Target Devices: xc3s400
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// Tool versions: ISE 13.1
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// Description: NEC uPD77C25 core (for SNES DSP1-4)
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.2 - core fully operational, firmware download
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//
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//////////////////////////////////////////////////////////////////////////////////
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module upd77c25(
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input [7:0] DI,
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output [7:0] DO,
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input A0,
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input nCS,
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input nRD,
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input nWR,
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input RST,
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input CLK,
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input PGM_WR,
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input [23:0] PGM_DI,
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input [10:0] PGM_WR_ADDR,
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input DAT_WR,
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input [15:0] DAT_DI,
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input [10:0] DAT_WR_ADDR,
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input DP_nCS,
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input [10:0] DP_ADDR,
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// debug
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output [15:0] updDR,
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output [15:0] updSR,
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output [10:0] updPC,
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output [15:0] updA,
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output [15:0] updB,
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output [5:0] updFL_A,
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output [5:0] updFL_B
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);
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parameter STATE_FETCH = 8'b00000001;
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parameter STATE_LOAD = 8'b00000010;
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parameter STATE_ALU1 = 8'b00000100;
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parameter STATE_ALU2 = 8'b00001000;
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parameter STATE_STORE = 8'b00010000;
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parameter STATE_NEXT = 8'b00100000;
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parameter STATE_IDLE1 = 8'b01000000;
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parameter STATE_IDLE2 = 8'b10000000;
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parameter I_OP = 2'b00;
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parameter I_RT = 2'b01;
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parameter I_JP = 2'b10;
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parameter I_LD = 2'b11;
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parameter SR_RQM = 15;
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parameter SR_DRS = 12;
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parameter SR_DRC = 10;
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reg [1:0] flags_ov0;
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reg [1:0] flags_ov1;
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reg [1:0] flags_z;
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reg [1:0] flags_c;
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reg [1:0] flags_s0;
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reg [1:0] flags_s1;
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reg [10:0] pc; // program counter
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reg [7:0] insn_state; // execute state
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reg [1:0] regs_dpb;
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reg [3:0] regs_dph;
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reg [3:0] regs_dpl;
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reg [10:0] regs_rp;
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wire [15:0] ram_dina;
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reg [15:0] ram_dina_r;
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assign ram_dina = ram_dina_r;
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wire [23:0] pgm_doutb;
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upd77c25_pgmrom pgmrom (
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.clka(CLK), // input clka
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.wea(PGM_WR), // input [0 : 0] wea
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.addra(PGM_WR_ADDR), // input [10 : 0] addra
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.dina(PGM_DI), // input [23 : 0] dina
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.clkb(CLK), // input clkb
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.addrb(pc), // input [10 : 0] addrb
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.doutb(pgm_doutb) // output [23 : 0] doutb
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);
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wire [23:0] opcode_w = pgm_doutb;
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reg [1:0] op;
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reg [1:0] op_pselect;
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reg [3:0] op_alu;
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reg op_asl;
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reg [1:0] op_dpl;
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reg [3:0] op_dphm;
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reg op_rpdcr;
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reg [3:0] op_src;
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reg [3:0] op_dst;
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wire [15:0] dat_doutb;
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upd77c25_datrom datrom (
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.clka(CLK), // input clka
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.wea(DAT_WR), // input [0 : 0] wea
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.addra(DAT_WR_ADDR), // input [9 : 0] addra
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.dina(DAT_DI), // input [15 : 0] dina
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.clkb(CLK), // input clkb
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.addrb(regs_rp), // input [10 : 0] addrb
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.doutb(dat_doutb) // output [15 : 0] doutb
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);
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reg [4:0] reg_nCS_sreg;
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initial reg_nCS_sreg = 5'b11111;
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always @(posedge CLK) reg_nCS_sreg <= {reg_nCS_sreg[3:0], nCS};
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reg [5:0] reg_oe_sreg;
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initial reg_oe_sreg = 6'b111111;
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always @(posedge CLK) reg_oe_sreg <= {reg_oe_sreg[4:0], nRD};
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wire reg_oe_rising = !reg_nCS_sreg[4] && (reg_oe_sreg[5:0] == 6'b000001);
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wire reg_oe_falling = (reg_oe_sreg[5:0] == 6'b100000);
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reg [4:0] reg_DP_nCS_sreg;
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initial reg_DP_nCS_sreg = 5'b11111;
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always @(posedge CLK) reg_DP_nCS_sreg <= {reg_DP_nCS_sreg[3:0], DP_nCS};
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reg [5:0] reg_we_sreg;
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initial reg_we_sreg = 6'b111111;
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always @(posedge CLK) reg_we_sreg <= {reg_we_sreg[4:0], nWR};
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wire reg_we_rising = !reg_nCS_sreg[4] && (reg_we_sreg[5:0] == 6'b000001);
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wire [15:0] ram_douta;
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wire [9:0] ram_addra;
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reg [7:0] DP_DOr;
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wire [7:0] DP_DO;
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wire [7:0] UPD_DO;
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reg ram_web;
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reg [10:0] ram_addrb;
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always @(posedge CLK) begin
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ram_addrb <= DP_ADDR; //r[10:0];
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ram_web <= ~(nWR | reg_DP_nCS_sreg[0] | reg_DP_nCS_sreg[4]);
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end
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upd77c25_datram datram (
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.clka(CLK), // input clka
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.wea(ram_wea), // input [0 : 0] wea
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.addra(ram_addra), // input [9 : 0] addra
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.dina(ram_dina), // input [15 : 0] dina
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.douta(ram_douta), // output [15 : 0] douta
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.clkb(CLK), // input clkb
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.web(ram_web), // input [0 : 0] web
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.addrb(ram_addrb), // input [10 : 0] addrb
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.dinb(DI), // input [7 : 0] dinb
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.doutb(DP_DO) // output [7 : 0] doutb
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);
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assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == STATE_IDLE1);
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assign ram_addra = {regs_dpb,
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regs_dph | ((insn_state == STATE_ALU1 && op_dst == 4'b1100)
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? 4'b0100
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: 4'b0000),
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regs_dpl};
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reg signed [15:0] regs_k;
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reg signed [15:0] regs_l;
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reg [15:0] regs_trb;
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reg [15:0] regs_tr;
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reg [15:0] regs_dr;
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reg [15:0] regs_sr;
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reg [3:0] regs_sp;
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reg cond_true;
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reg [8:0] jp_brch;
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reg [10:0] jp_na;
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reg [15:0] ld_id;
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reg [3:0] ld_dst;
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wire [31:0] mul_result = regs_k * regs_l;
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reg [15:0] regs_m;
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reg [15:0] regs_n;
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reg [15:0] alu_p;
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reg [15:0] alu_q;
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reg [15:0] alu_r;
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reg [1:0] alu_store;
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reg [10:0] stack [15:0];
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reg [15:0] idb;
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reg [15:0] regs_ab [1:0];
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assign updDR = regs_dr;
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assign updSR = regs_sr;
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assign updPC = pc;
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assign updA = regs_ab[0];
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assign updB = regs_ab[1];
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assign updFL_A = {flags_s1[0],flags_s0[0],flags_c[0],flags_z[0],flags_ov1[0],flags_ov0[0]};
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assign updFL_B = {flags_s1[1],flags_s0[1],flags_c[1],flags_z[1],flags_ov1[1],flags_ov0[1]};
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initial begin
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alu_store = 2'b11;
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insn_state = STATE_IDLE1;
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regs_sp = 4'b0000;
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pc = 11'b0;
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regs_sr = 16'b0;
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regs_rp = 16'h0000;
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regs_dpb = 2'b0;
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regs_dph = 4'b0;
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regs_dpl = 4'b0;
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regs_k = 16'b0;
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regs_l = 16'b0;
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regs_ab[0] = 16'b0;
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regs_ab[1] = 16'b0;
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flags_ov0 = 2'b0;
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flags_ov1 = 2'b0;
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flags_z = 2'b0;
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flags_c = 2'b0;
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flags_s0 = 2'b0;
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flags_s1 = 2'b0;
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regs_tr = 16'b0;
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regs_trb = 16'b0;
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regs_dr = 16'b0;
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end
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reg [3:0] A0r;
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initial A0r = 4'b1111;
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always @(posedge CLK) A0r <= {A0r[2:0], A0};
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always @(posedge CLK) begin
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if(RST) begin
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if((op_src == 4'b1000 && op[1] == 1'b0 && insn_state == STATE_STORE)
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|| (op_dst == 4'b0110 && op != 2'b10 && insn_state == STATE_STORE)) regs_sr[SR_RQM] <= 1'b1;
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else if((reg_we_rising) && (A0r[3] == 1'b0)) begin
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if(!regs_sr[SR_DRC]) begin
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if(regs_sr[SR_DRS] == 1'b1) begin
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regs_sr[SR_RQM] <= 1'b0;
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end
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end else begin
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regs_sr[SR_RQM] <= 1'b0;
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end
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end
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else if(reg_oe_rising && (A0r[3] == 1'b0)) begin
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if(!regs_sr[SR_DRC]) begin
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if(regs_sr[SR_DRS] == 1'b1) begin
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regs_sr[SR_RQM] <= 1'b0;
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end
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end else begin
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regs_sr[SR_RQM] <= 1'b0;
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end
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end
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end else begin
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regs_sr[SR_RQM] <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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if(reg_we_rising && (A0r[3] == 1'b0)) begin
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if(!regs_sr[SR_DRC]) begin
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if(regs_sr[SR_DRS] == 1'b0) begin
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regs_sr[SR_DRS] <= 1'b1;
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end else begin
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regs_sr[SR_DRS] <= 1'b0;
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end
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end
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end else if(reg_oe_rising) begin
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case(A0r[3])
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1'b0: begin
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if(!regs_sr[SR_DRC]) begin
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if(regs_sr[SR_DRS] == 1'b0) begin
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regs_sr[SR_DRS] <= 1'b1;
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end else begin
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regs_sr[SR_DRS] <= 1'b0;
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end
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end
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end
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endcase
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end
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end else begin
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regs_sr[SR_DRS] <= 1'b0;
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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if(reg_we_rising && (A0r[3] == 1'b0)) begin
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if(!regs_sr[SR_DRC]) begin
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if(regs_sr[SR_DRS] == 1'b0) begin
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regs_dr[7:0] <= DI;
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end else begin
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regs_dr[15:8] <= DI;
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end
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end else begin
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regs_dr[7:0] <= DI;
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end
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end else if(ld_dst == 4'b0110 && insn_state == STATE_STORE) begin
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if (op == I_OP || op == I_RT) regs_dr <= idb;
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else if (op == I_LD) regs_dr <= ld_id;
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end
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end else begin
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regs_dr <= 16'h0000;
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end
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end
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always @(posedge CLK) begin
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if(reg_oe_falling) DP_DOr <= DP_DO;
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end
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assign UPD_DO = (A0 ? regs_sr[15:8] : (regs_sr[SR_DRC] ? regs_dr[7:0] : (regs_sr[SR_DRS] ? regs_dr[15:8] : regs_dr[7:0])));
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assign DO = !DP_nCS ? DP_DOr : UPD_DO;
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always @(posedge CLK) begin
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if(RST) begin
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case(insn_state)
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STATE_FETCH: begin
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insn_state <= STATE_LOAD;
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if(op == I_OP || op == I_RT) begin
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if(|op_alu) begin
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flags_z[op_asl] <= (alu_r == 0);
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flags_s0[op_asl] <= alu_r[15];
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end
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case(op_alu)
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4'b0001, 4'b0010, 4'b0011, 4'b1010, 4'b1101, 4'b1110, 4'b1111: begin
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flags_c[op_asl] <= 0;
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flags_ov0[op_asl] <= 0;
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flags_ov1[op_asl] <= 0;
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end
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4'b0100, 4'b0101, 4'b0110, 4'b0111, 4'b1000, 4'b1001: begin
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if(op_alu[0]) begin
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flags_c[op_asl] <= (alu_r < alu_q);
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flags_ov0[op_asl] <= (alu_q[15] ^ alu_r[15]) & ~(alu_q[15] ^ alu_p[15]);
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if((alu_q[15] ^ alu_r[15]) & ~(alu_q[15] ^ alu_p[15])) begin
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flags_s1[op_asl] <= flags_ov1[op_asl] ^ ~alu_r[15];
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flags_ov1[op_asl] <= ~flags_ov1[op_asl];
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end
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end else begin
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flags_c[op_asl] <= (alu_r > alu_q);
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flags_ov0[op_asl] <= (alu_q[15] ^ alu_r[15]) & (alu_q[15] ^ alu_p[15]);
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if((alu_q[15] ^ alu_r[15]) & (alu_q[15] ^ alu_p[15])) begin
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flags_s1[op_asl] <= flags_ov1[op_asl] ^ ~alu_r[15];
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flags_ov1[op_asl] <= ~flags_ov1[op_asl];
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end
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end
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end
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4'b1011: begin
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flags_c[op_asl] <= alu_q[0];
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flags_ov0[op_asl] <= 0;
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flags_ov1[op_asl] <= 0;
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end
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4'b1100: begin
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flags_c[op_asl] <= alu_q[15];
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flags_ov0[op_asl] <= 0;
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flags_ov1[op_asl] <= 0;
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end
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endcase
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end
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op <= opcode_w[23:22];
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op_pselect <= opcode_w[21:20];
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op_alu <= opcode_w[19:16];
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op_asl <= opcode_w[15];
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op_dpl <= opcode_w[14:13];
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op_dphm <= opcode_w[12:9];
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op_rpdcr <= opcode_w[8];
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op_src <= opcode_w[7:4];
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op_dst <= opcode_w[3:0];
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jp_brch <= opcode_w[21:13];
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jp_na <= opcode_w[12:2];
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ld_id <= opcode_w[21:6];
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ld_dst <= opcode_w[3:0];
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regs_m <= {mul_result[31], mul_result[29:15]};
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regs_n <= {mul_result[14:0], 1'b0};
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end
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STATE_LOAD: begin
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insn_state <= STATE_ALU1;
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case(op)
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I_OP, I_RT: begin
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case(op_src)
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4'b0000: idb <= regs_trb;
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4'b0001: idb <= regs_ab[0];
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4'b0010: idb <= regs_ab[1];
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4'b0011: idb <= regs_tr;
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4'b0100: idb <= {regs_dpb,regs_dph,regs_dpl};
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4'b0101: idb <= regs_rp;
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4'b0110: idb <= dat_doutb; // Address: [regs_rp]
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4'b0111: idb <= flags_s1[0] ? 16'h7fff : 16'h8000;
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4'b1000: idb <= regs_dr;
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4'b1001: idb <= regs_dr;
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4'b1010: idb <= regs_sr;
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4'b1101: idb <= regs_k;
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4'b1110: idb <= regs_l;
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4'b1111: idb <= ram_douta; // Address: [regs_dp]
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endcase
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end
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endcase
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end
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STATE_ALU1: begin
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insn_state <= STATE_STORE;
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case(op)
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I_OP, I_RT: begin
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alu_q <= regs_ab[op_asl];
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if(op_alu[3:1] == 3'b100) begin
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alu_p <= 16'h0001;
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end else begin
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case(op_pselect)
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2'b00:
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alu_p <= ram_douta;
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2'b01:
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alu_p <= idb;
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2'b10:
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alu_p <= regs_m;
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2'b11:
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alu_p <= regs_n;
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endcase
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end
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end
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I_JP: begin
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case(jp_brch)
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9'b100_000_000: cond_true <= 1;
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9'b101_000_000: cond_true <= 1;
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9'b010_000_000: cond_true <= (flags_c[0] == 0);
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9'b010_000_010: cond_true <= (flags_c[0] == 1);
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9'b010_000_100: cond_true <= (flags_c[1] == 0);
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9'b010_000_110: cond_true <= (flags_c[1] == 1);
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9'b010_001_000: cond_true <= (flags_z[0] == 0);
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9'b010_001_010: cond_true <= (flags_z[0] == 1);
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9'b010_001_100: cond_true <= (flags_z[1] == 0);
|
|
9'b010_001_110: cond_true <= (flags_z[1] == 1);
|
|
9'b010_010_000: cond_true <= (flags_ov0[0] == 0);
|
|
9'b010_010_010: cond_true <= (flags_ov0[0] == 1);
|
|
9'b010_010_100: cond_true <= (flags_ov0[1] == 0);
|
|
9'b010_010_110: cond_true <= (flags_ov0[1] == 1);
|
|
9'b010_011_000: cond_true <= (flags_ov1[0] == 0);
|
|
9'b010_011_010: cond_true <= (flags_ov1[0] == 1);
|
|
9'b010_011_100: cond_true <= (flags_ov1[1] == 0);
|
|
9'b010_011_110: cond_true <= (flags_ov1[1] == 1);
|
|
9'b010_100_000: cond_true <= (flags_s0[0] == 0);
|
|
9'b010_100_010: cond_true <= (flags_s0[0] == 1);
|
|
9'b010_100_100: cond_true <= (flags_s0[1] == 0);
|
|
9'b010_100_110: cond_true <= (flags_s0[1] == 1);
|
|
9'b010_101_000: cond_true <= (flags_s1[0] == 0);
|
|
9'b010_101_010: cond_true <= (flags_s1[0] == 1);
|
|
9'b010_101_100: cond_true <= (flags_s1[1] == 0);
|
|
9'b010_101_110: cond_true <= (flags_s1[1] == 1);
|
|
9'b010_110_000: cond_true <= (regs_dpl == 0);
|
|
9'b010_110_001: cond_true <= (regs_dpl != 0);
|
|
9'b010_110_010: cond_true <= (regs_dpl == 4'b1111);
|
|
9'b010_110_011: cond_true <= (regs_dpl != 4'b1111);
|
|
9'b010_111_100: cond_true <= (regs_sr[SR_RQM] == 0);
|
|
9'b010_111_110: cond_true <= (regs_sr[SR_RQM] == 1);
|
|
default: cond_true <= 0;
|
|
endcase
|
|
end
|
|
endcase
|
|
end
|
|
// STATE_ALU2: begin
|
|
//insn_state <= STATE_STORE;
|
|
// end
|
|
STATE_STORE: begin
|
|
insn_state <= STATE_IDLE1;
|
|
if(op[1] == 1'b0) begin
|
|
case(op_alu)
|
|
4'b0001: alu_r <= alu_q | alu_p;
|
|
4'b0010: alu_r <= alu_q & alu_p;
|
|
4'b0011: alu_r <= alu_q ^ alu_p;
|
|
4'b0100: alu_r <= alu_q - alu_p;
|
|
4'b0101: alu_r <= alu_q + alu_p;
|
|
4'b0110: alu_r <= alu_q - alu_p - flags_c[~op_asl];
|
|
4'b0111: alu_r <= alu_q + alu_p + flags_c[~op_asl];
|
|
4'b1000: alu_r <= alu_q - alu_p;
|
|
4'b1001: alu_r <= alu_q + alu_p;
|
|
4'b1010: alu_r <= ~alu_q;
|
|
4'b1011: alu_r <= {alu_q[15], alu_q[15:1]};
|
|
4'b1100: alu_r <= {alu_q[14:0], flags_c[~op_asl]};
|
|
4'b1101: alu_r <= {alu_q[13:0], 2'b11};
|
|
4'b1110: alu_r <= {alu_q[11:0], 4'b1111};
|
|
4'b1111: alu_r <= {alu_q[7:0], alu_q[15:8]};
|
|
endcase
|
|
end
|
|
case(op)
|
|
I_OP, I_RT: begin
|
|
case(op_dst)
|
|
4'b0001: begin
|
|
regs_ab[0] <= idb;
|
|
alu_store <= 2'b10;
|
|
end
|
|
4'b0010: begin
|
|
regs_ab[1] <= idb;
|
|
alu_store <= 2'b01;
|
|
end
|
|
4'b0011: regs_tr <= idb;
|
|
4'b0100: {regs_dpb,regs_dph,regs_dpl} <= idb[9:0];
|
|
4'b0101: regs_rp <= idb;
|
|
// 4'b0110: regs_dr <= idb;
|
|
4'b0111: begin
|
|
regs_sr[14] <= idb[14];
|
|
regs_sr[13] <= idb[13];
|
|
regs_sr[11] <= idb[11];
|
|
regs_sr[SR_DRC] <= idb[10];
|
|
regs_sr[9] <= idb[9];
|
|
regs_sr[8] <= idb[8];
|
|
regs_sr[7] <= idb[7];
|
|
regs_sr[1] <= idb[1];
|
|
regs_sr[0] <= idb[0];
|
|
end
|
|
4'b1010: regs_k <= idb;
|
|
4'b1011: begin
|
|
regs_k <= idb;
|
|
regs_l <= dat_doutb;
|
|
end
|
|
4'b1100: begin
|
|
regs_k <= ram_douta;
|
|
regs_l <= idb;
|
|
end
|
|
4'b1101: regs_l <= idb;
|
|
4'b1110: regs_trb <= idb;
|
|
4'b1111: ram_dina_r <= idb;
|
|
endcase
|
|
end
|
|
I_LD: begin
|
|
case(ld_dst)
|
|
4'b0001: regs_ab[0] <= ld_id;
|
|
4'b0010: regs_ab[1] <= ld_id;
|
|
4'b0011: regs_tr <= ld_id;
|
|
4'b0100: {regs_dpb,regs_dph,regs_dpl} <= ld_id[9:0];
|
|
4'b0101: regs_rp <= ld_id;
|
|
// 4'b0110: regs_dr <= ld_id;
|
|
4'b0111: begin
|
|
regs_sr[14] <= ld_id[14];
|
|
regs_sr[13] <= ld_id[13];
|
|
regs_sr[11] <= ld_id[11];
|
|
regs_sr[SR_DRC] <= ld_id[10];
|
|
regs_sr[9] <= ld_id[9];
|
|
regs_sr[8] <= ld_id[8];
|
|
regs_sr[7] <= ld_id[7];
|
|
regs_sr[1] <= ld_id[1];
|
|
regs_sr[0] <= ld_id[0];
|
|
end
|
|
4'b1010: regs_k <= ld_id;
|
|
4'b1011: begin
|
|
regs_k <= ld_id;
|
|
regs_l <= dat_doutb;
|
|
end
|
|
4'b1100: begin
|
|
regs_k <= ram_douta;
|
|
regs_l <= ld_id;
|
|
end
|
|
4'b1101: regs_l <= ld_id;
|
|
4'b1110: regs_trb <= ld_id;
|
|
4'b1111: ram_dina_r <= ld_id;
|
|
endcase
|
|
end
|
|
endcase
|
|
case(op)
|
|
I_OP, I_RT: begin
|
|
if(op_rpdcr) regs_rp <= regs_rp - 1;
|
|
if(op == I_OP) pc <= pc + 1;
|
|
else begin
|
|
pc <= stack[regs_sp-1];
|
|
regs_sp <= regs_sp - 1;
|
|
end
|
|
end
|
|
I_JP: begin
|
|
if(cond_true) begin
|
|
pc <= jp_na;
|
|
if(jp_brch[8:6] == 3'b101) begin
|
|
stack[regs_sp] <= pc + 1;
|
|
regs_sp <= regs_sp + 1;
|
|
end
|
|
end else pc <= pc + 1;
|
|
end
|
|
I_LD: begin
|
|
pc <= pc + 1;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// STATE_NEXT: begin
|
|
// insn_state <= STATE_IDLE1;
|
|
// end
|
|
|
|
STATE_IDLE1: begin
|
|
insn_state <= STATE_FETCH;
|
|
case(op)
|
|
I_OP, I_RT: begin
|
|
case(op_dpl)
|
|
2'b01: regs_dpl <= regs_dpl + 1;
|
|
2'b10: regs_dpl <= regs_dpl - 1;
|
|
2'b11: regs_dpl <= 4'b0000;
|
|
endcase
|
|
regs_dph <= regs_dph ^ op_dphm;
|
|
if(|op_alu && alu_store[op_asl]) regs_ab[op_asl] <= alu_r;
|
|
alu_store <= 2'b11;
|
|
end
|
|
endcase
|
|
end
|
|
endcase
|
|
end else begin
|
|
insn_state <= STATE_IDLE1;
|
|
pc <= 11'b0;
|
|
regs_sp <= 4'b0000;
|
|
cond_true <= 0;
|
|
regs_sr[14] <= 0;
|
|
regs_sr[13] <= 0;
|
|
regs_sr[11] <= 0;
|
|
regs_sr[SR_DRC] <= 0;
|
|
regs_sr[9] <= 0;
|
|
regs_sr[8] <= 0;
|
|
regs_sr[7] <= 0;
|
|
regs_rp <= 16'h0000;
|
|
regs_dpb <= 2'b0;
|
|
regs_dph <= 4'b0;
|
|
regs_dpl <= 4'b0;
|
|
regs_k <= 16'b0;
|
|
regs_l <= 16'b0;
|
|
regs_ab[0] <= 16'b0;
|
|
regs_ab[1] <= 16'b0;
|
|
flags_ov0 <= 2'b0;
|
|
flags_ov1 <= 2'b0;
|
|
flags_z <= 2'b0;
|
|
flags_c <= 2'b0;
|
|
flags_s0 <= 2'b0;
|
|
flags_s1 <= 2'b0;
|
|
regs_tr <= 16'b0;
|
|
regs_trb <= 16'b0;
|
|
op_pselect <= 2'b0;
|
|
op_alu <= 4'b0;
|
|
op_asl <= 1'b0;
|
|
op_dpl <= 2'b0;
|
|
op_dphm <= 4'b0;
|
|
op_rpdcr <= 1'b0;
|
|
op_src <= 4'b0;
|
|
op_dst <= 4'b0;
|
|
jp_brch <= 9'b0;
|
|
jp_na <= 11'b0;
|
|
ld_id <= 16'b0;
|
|
ld_dst <= 4'b0;
|
|
regs_m <= 16'b0;
|
|
regs_n <= 16'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|