654 lines
17 KiB
Verilog
654 lines
17 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: main
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Master Control FSM
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//
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// Dependencies: address
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module main(
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/* input clock */
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input CLKIN,
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/* SNES signals */
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input [23:0] SNES_ADDR,
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input SNES_READ,
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input SNES_WRITE,
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input SNES_CS,
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inout [7:0] SNES_DATA,
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input SNES_CPU_CLK,
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input SNES_REFRESH,
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inout SNES_IRQ,
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output SNES_DATABUS_OE,
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output SNES_DATABUS_DIR,
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output IRQ_DIR,
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input SNES_SYSCLK,
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/* SRAM signals */
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/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
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inout [15:0] ROM_DATA,
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output [22:0] ROM_ADDR,
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output ROM_CE,
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output ROM_OE,
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output ROM_WE,
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output ROM_BHE,
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output ROM_BLE,
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/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
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inout [7:0] RAM_DATA,
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output [18:0] RAM_ADDR,
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output RAM_CE,
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output RAM_OE,
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output RAM_WE,
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/* MCU signals */
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input SPI_MOSI,
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inout SPI_MISO,
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input SPI_SS,
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inout SPI_SCK,
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input MCU_OVR,
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output DAC_MCLK,
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output DAC_LRCK,
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output DAC_SDOUT,
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/* SD signals */
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input [3:0] SD_DAT,
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inout SD_CMD,
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inout SD_CLK
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/* debug */
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,
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output p113_out
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);
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wire dspx_dp_enable;
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assign p113_out = dspx_dp_enable;
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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wire [31:0] spi_byte_cnt;
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wire [2:0] spi_bit_cnt;
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wire [23:0] MCU_ADDR;
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wire [7:0] mcu_data_in;
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wire [7:0] mcu_data_out;
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wire [7:0] MCU_IN_DATA;
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wire [7:0] MCU_OUT_DATA;
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wire [3:0] MAPPER;
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wire [23:0] SAVERAM_MASK;
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wire [23:0] ROM_MASK;
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wire [7:0] SD_DMA_SRAM_DATA;
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wire [1:0] SD_DMA_TGT;
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wire [10:0] SD_DMA_PARTIAL_START;
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wire [10:0] SD_DMA_PARTIAL_END;
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wire [10:0] dac_addr;
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//wire [7:0] dac_volume;
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wire [7:0] msu_volumerq_out;
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wire [6:0] msu_status_out;
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wire [31:0] msu_addressrq_out;
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wire [15:0] msu_trackrq_out;
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wire [13:0] msu_write_addr;
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wire [13:0] msu_ptr_addr;
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wire [7:0] MSU_SNES_DATA_IN;
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wire [7:0] MSU_SNES_DATA_OUT;
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wire [5:0] msu_status_reset_bits;
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wire [5:0] msu_status_set_bits;
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wire [14:0] bsx_regs;
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wire [14:0] bsx_regs_in;
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wire [7:0] BSX_SNES_DATA_IN;
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wire [7:0] BSX_SNES_DATA_OUT;
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wire [7:0] bsx_regs_reset_bits;
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wire [7:0] bsx_regs_set_bits;
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wire [59:0] rtc_data;
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wire [59:0] rtc_data_in;
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wire [59:0] srtc_rtc_data_out;
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wire [7:0] SRTC_SNES_DATA_IN;
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wire [7:0] SRTC_SNES_DATA_OUT;
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wire [7:0] DSPX_SNES_DATA_IN;
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wire [7:0] DSPX_SNES_DATA_OUT;
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wire [23:0] dspx_pgm_data;
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wire [10:0] dspx_pgm_addr;
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wire dspx_pgm_we;
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wire [15:0] dspx_dat_data;
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wire [10:0] dspx_dat_addr;
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wire dspx_dat_we;
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wire [7:0] featurebits;
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//wire SD_DMA_EN; //SPI_DMA_CTRL;
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sd_dma snes_sd_dma(
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.CLK(CLK2),
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.SD_DAT(SD_DAT),
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.SD_CLK(SD_CLK),
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.SD_DMA_EN(SD_DMA_EN),
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.SD_DMA_STATUS(SD_DMA_STATUS),
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.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
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.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
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.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
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.SD_DMA_TGT(SD_DMA_TGT),
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.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
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.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
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.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END)
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);
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dac snes_dac(
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.clkin(CLK2),
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.sysclk(SNES_SYSCLK),
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.mclk(DAC_MCLK),
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.lrck(DAC_LRCK),
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.sdout(DAC_SDOUT),
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.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
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.pgm_address(dac_addr),
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.pgm_data(SD_DMA_SRAM_DATA),
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.DAC_STATUS(DAC_STATUS),
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.volume(msu_volumerq_out),
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.vol_latch(msu_volume_latch_out),
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.play(dac_play),
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.reset(dac_reset)
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);
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srtc snes_srtc (
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.clkin(CLK2),
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/*XXX*/.reg_addr(srtc_reg_addr),
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.addr_in(SNES_ADDR[0]),
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.data_in(SRTC_SNES_DATA_IN),
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.data_out(SRTC_SNES_DATA_OUT),
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.rtc_data_in(rtc_data),
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.reg_we(SNES_WRITE),
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.reg_oe(SNES_READ),
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.enable(srtc_enable),
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.rtc_data_out(srtc_rtc_data_out),
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.rtc_we(srtc_rtc_we),
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.reset(srtc_reset)
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);
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rtc snes_rtc (
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.clkin(CLKIN),
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.rtc_data(rtc_data),
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.rtc_data_in(rtc_data_in),
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.pgm_we(rtc_pgm_we),
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.rtc_data_in1(srtc_rtc_data_out),
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.we1(srtc_rtc_we)
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);
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msu snes_msu (
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.clkin(CLK2),
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.enable(msu_enable),
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.pgm_address(msu_write_addr),
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.pgm_data(SD_DMA_SRAM_DATA),
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.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
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.reg_addr(SNES_ADDR),
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.reg_data_in(MSU_SNES_DATA_IN),
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.reg_data_out(MSU_SNES_DATA_OUT),
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.reg_oe(SNES_READ),
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.reg_we(SNES_WRITE),
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.status_out(msu_status_out),
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.volume_out(msu_volumerq_out),
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.volume_latch_out(msu_volume_latch_out),
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.addr_out(msu_addressrq_out),
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.track_out(msu_trackrq_out),
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.status_reset_bits(msu_status_reset_bits),
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.status_set_bits(msu_status_set_bits),
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.status_reset_we(msu_status_reset_we),
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.msu_address_ext(msu_ptr_addr),
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.msu_address_ext_write(msu_addr_reset)
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);
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bsx snes_bsx(
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.clkin(CLK2),
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.use_bsx(use_bsx),
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.pgm_we(bsx_regs_reset_we),
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.snes_addr(SNES_ADDR),
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.reg_data_in(BSX_SNES_DATA_IN),
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.reg_data_out(BSX_SNES_DATA_OUT),
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.reg_oe(SNES_READ),
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.reg_we(SNES_WRITE),
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.regs_out(bsx_regs),
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.reg_reset_bits(bsx_regs_reset_bits),
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.reg_set_bits(bsx_regs_set_bits),
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.data_ovr(bsx_data_ovr),
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.flash_writable(IS_FLASHWR),
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.rtc_data(rtc_data)
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);
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spi snes_spi(
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.clk(CLK2),
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.MOSI(SPI_MOSI),
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.MISO(SPI_MISO),
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.SSEL(SPI_SS),
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.SCK(SPI_SCK),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.input_data(spi_input_data),
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.byte_cnt(spi_byte_cnt),
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.bit_cnt(spi_bit_cnt)
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);
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upd77c25 snes_dspx (
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.DI(DSPX_SNES_DATA_IN),
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.DO(DSPX_SNES_DATA_OUT),
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.A0(DSPX_A0),
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.nCS(~dspx_enable),
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.nRD(SNES_READ),
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.nWR(SNES_WRITE),
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.RST(~dspx_reset),
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.CLK(CLK2),
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.PGM_WR(dspx_pgm_we),
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.PGM_DI(dspx_pgm_data),
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.PGM_WR_ADDR(dspx_pgm_addr),
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.DAT_WR(dspx_dat_we),
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.DAT_DI(dspx_dat_data),
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.DAT_WR_ADDR(dspx_dat_addr),
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.DP_nCS(~dspx_dp_enable),
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.DP_ADDR(SNES_ADDR[10:0])
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);
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mcu_cmd snes_mcu_cmd(
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.clk(CLK2),
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.snes_sysclk(SNES_SYSCLK),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.mcu_mapper(MAPPER),
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.mcu_sram_size(SRAM_SIZE),
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.mcu_read(MCU_READ),
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.mcu_write(MCU_WRITE),
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.mcu_data_in(MCU_OUT_DATA),
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.mcu_data_out(MCU_IN_DATA),
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.spi_byte_cnt(spi_byte_cnt),
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.spi_bit_cnt(spi_bit_cnt),
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.spi_data_out(spi_input_data),
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.addr_out(MCU_ADDR),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.saveram_mask_out(SAVERAM_MASK),
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.rom_mask_out(ROM_MASK),
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.SD_DMA_EN(SD_DMA_EN),
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.SD_DMA_STATUS(SD_DMA_STATUS),
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.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
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.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
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.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
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.SD_DMA_TGT(SD_DMA_TGT),
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.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
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.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
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.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
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.dac_addr_out(dac_addr),
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.DAC_STATUS(DAC_STATUS),
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// .dac_volume_out(dac_volume),
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// .dac_volume_latch_out(dac_vol_latch),
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.dac_play_out(dac_play),
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.dac_reset_out(dac_reset),
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.msu_addr_out(msu_write_addr),
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.MSU_STATUS(msu_status_out),
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.msu_status_reset_out(msu_status_reset_bits),
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.msu_status_set_out(msu_status_set_bits),
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.msu_status_reset_we(msu_status_reset_we),
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.msu_volumerq(msu_volumerq_out),
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.msu_addressrq(msu_addressrq_out),
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.msu_trackrq(msu_trackrq_out),
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.msu_ptr_out(msu_ptr_addr),
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.msu_reset_out(msu_addr_reset),
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.bsx_regs_set_out(bsx_regs_set_bits),
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.bsx_regs_reset_out(bsx_regs_reset_bits),
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.bsx_regs_reset_we(bsx_regs_reset_we),
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.rtc_data_out(rtc_data_in),
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.rtc_pgm_we(rtc_pgm_we),
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.srtc_reset(srtc_reset),
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.dspx_pgm_data_out(dspx_pgm_data),
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.dspx_pgm_addr_out(dspx_pgm_addr),
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.dspx_pgm_we_out(dspx_pgm_we),
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.dspx_dat_data_out(dspx_dat_data),
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.dspx_dat_addr_out(dspx_dat_addr),
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.dspx_dat_we_out(dspx_dat_we),
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.dspx_reset_out(dspx_reset),
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.featurebits_out(featurebits)
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);
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// dcm1: dfs 4x
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my_dcm snes_dcm(
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.CLKIN(CLKIN),
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.CLKFX(CLK2),
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.LOCKED(DCM_LOCKED),
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.RST(DCM_RST),
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.STATUS(DCM_STATUS)
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);
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assign DCM_RST=0;
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wire SNES_RW;
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reg [1:0] SNES_READr;
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reg [1:0] SNES_WRITEr;
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reg [1:0] SNES_CSr;
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reg [5:0] SNES_CPU_CLKr;
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reg [5:0] SNES_RWr;
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reg [23:0] SNES_ADDRr;
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reg [23:0] SNES_ADDR_PREVr;
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reg [3:0] SNES_ADDRCHGr;
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wire SNES_READs = (SNES_READr == 2'b11);
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wire SNES_WRITEs = (SNES_WRITEr == 2'b11);
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wire SNES_CSs = (SNES_CSr == 2'b11);
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wire SNES_CPU_CLKs = SNES_CPU_CLK; // (SNES_CPU_CLKr == 2'b11);
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wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
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wire SNES_cycle_start = (SNES_CPU_CLKr == 6'b000011);
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wire SNES_ADDRCHG = (SNES_ADDRr != SNES_ADDR_PREVr);
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wire SNES_addr_start = (SNES_ADDRCHGr[0] == 1'b1);
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assign SNES_RW = (SNES_READ & SNES_WRITE);
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always @(posedge CLK2) begin
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SNES_READr <= {SNES_READr[0], SNES_READ};
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SNES_WRITEr <= {SNES_WRITEr[0], SNES_WRITE};
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SNES_CSr <= {SNES_CSr[0], SNES_CS};
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SNES_CPU_CLKr <= {SNES_CPU_CLKr[4:0], SNES_CPU_CLK};
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SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
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end
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reg ADDR_WRITE;
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wire ROM_SEL;
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address snes_addr(
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.CLK(CLK2),
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.MAPPER(MAPPER),
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.featurebits(featurebits),
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.SNES_ADDR(SNES_ADDR), // requested address from SNES
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.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
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.ROM_ADDR(ROM_ADDR), // Address to request from SRAM (active low)
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.ROM_SEL(ROM_SEL), // which SRAM unit to access
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.MCU_OVR(MCU_OVR), // enable MCU mode (active low)
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.MODE(MODE), // MCU(1) or SNES(0) ("bus phase")
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.IS_SAVERAM(IS_SAVERAM),
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.IS_ROM(IS_ROM),
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.IS_WRITABLE(IS_WRITABLE),
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.MCU_ADDR(MCU_ADDR),
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.ROM_ADDR0(ROM_ADDR0),
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.SAVERAM_MASK(SAVERAM_MASK),
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.ROM_MASK(ROM_MASK),
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//MSU-1
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.use_msu(use_msu),
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.msu_enable(msu_enable),
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//BS-X
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.use_bsx(use_bsx),
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.bsx_regs(bsx_regs),
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//SRTC
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.srtc_enable(srtc_enable),
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//uPD77C25
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.dspx_enable(dspx_enable),
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.dspx_dp_enable(dspx_dp_enable),
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.dspx_a0(DSPX_A0)
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);
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wire SNES_READ_CYCLEw;
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wire SNES_WRITE_CYCLEw;
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wire MCU_READ_CYCLEw;
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wire MCU_WRITE_CYCLEw;
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data snes_data(
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.CLK(CLK2),
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.SNES_READ(SNES_READ),
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.SNES_WRITE(SNES_WRITE),
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.MCU_READ(MCU_READ),
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.MCU_WRITE(MCU_WRITE),
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.SNES_DATA(SNES_DATA),
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.ROM_DATA(ROM_DATA),
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.MODE(MODE),
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.SNES_DATA_TO_MEM(SNES_DATA_TO_MEM),
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.MCU_DATA_TO_MEM(MCU_DATA_TO_MEM),
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.ROM_DATA_TO_SNES_MEM(ROM_DATA_TO_SNES_MEM),
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.ROM_DATA_TO_MCU_MEM(ROM_DATA_TO_MCU_MEM),
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.MCU_OVR(MCU_OVR),
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.MCU_IN_DATA(MCU_IN_DATA),
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.MCU_OUT_DATA(MCU_OUT_DATA),
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.ROM_ADDR0(ROM_ADDR0),
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.MSU_DATA_IN(MSU_SNES_DATA_IN),
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.MSU_DATA_OUT(MSU_SNES_DATA_OUT),
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.BSX_DATA_IN(BSX_SNES_DATA_IN),
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.BSX_DATA_OUT(BSX_SNES_DATA_OUT),
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.SRTC_DATA_IN(SRTC_SNES_DATA_IN),
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.SRTC_DATA_OUT(SRTC_SNES_DATA_OUT),
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.DSPX_DATA_IN(DSPX_SNES_DATA_IN),
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.DSPX_DATA_OUT(DSPX_SNES_DATA_OUT),
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.msu_enable(msu_enable),
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.bsx_data_ovr(bsx_data_ovr),
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.srtc_enable(srtc_enable),
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.dspx_enable(dspx_enable),
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.dspx_dp_enable(dspx_dp_enable)
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);
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parameter MODE_SNES = 1'b0;
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parameter MODE_MCU = 1'b1;
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parameter STATE_0 = 14'b00000000000001;
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parameter STATE_1 = 14'b00000000000010;
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parameter STATE_2 = 14'b00000000000100;
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parameter STATE_3 = 14'b00000000001000;
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parameter STATE_4 = 14'b00000000010000;
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parameter STATE_5 = 14'b00000000100000;
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parameter STATE_6 = 14'b00000001000000;
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parameter STATE_7 = 14'b00000010000000;
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parameter STATE_8 = 14'b00000100000000;
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parameter STATE_9 = 14'b00001000000000;
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parameter STATE_10 = 14'b00010000000000;
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parameter STATE_11 = 14'b00100000000000;
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parameter STATE_12 = 14'b01000000000000;
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parameter STATE_IDLE = 14'b10000000000000;
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reg [13:0] STATE;
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reg [3:0] STATEIDX;
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reg [1:0] CYCLE_RESET;
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reg ROM_WE_MASK;
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reg ROM_OE_MASK;
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|
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reg [13:0] ROM_WE_ARRAY [3:0];
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reg [13:0] ROM_OE_ARRAY [3:0];
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reg [13:0] SNES_DATA_TO_MEM_ARRAY[1:0];
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reg [13:0] MCU_DATA_TO_MEM_ARRAY[1:0];
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reg [13:0] ROM_DATA_TO_SNES_MEM_ARRAY[1:0];
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reg [13:0] ROM_DATA_TO_MCU_MEM_ARRAY[1:0];
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reg [13:0] MODE_ARRAY;
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|
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reg SNES_READ_CYCLE;
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reg SNES_WRITE_CYCLE;
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reg MCU_READ_CYCLE;
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reg MCU_WRITE_CYCLE;
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reg MCU_SPI_WRITEONCE;
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reg MCU_SPI_READONCE;
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reg MCU_SPI_WRITE;
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reg MCU_SPI_READ;
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reg MCU_SPI_ADDR_INCREMENT;
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reg [7:0] MCU_DATA_IN;
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reg [3:0] MAPPER_BUF;
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|
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reg SNES_DATABUS_OE_BUF;
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reg SNES_DATABUS_DIR_BUF;
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|
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assign MODE = !MCU_OVR ? MODE_MCU : MODE_ARRAY[STATEIDX];
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|
|
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initial begin
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CYCLE_RESET = 2'b0;
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STATE = STATE_IDLE;
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STATEIDX = 13;
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ROM_WE_MASK = 1'b1;
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ROM_OE_MASK = 1'b1;
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SNES_READ_CYCLE = 1'b1;
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SNES_WRITE_CYCLE = 1'b1;
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MCU_READ_CYCLE = 1'b1;
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MCU_WRITE_CYCLE = 1'b1;
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|
MODE_ARRAY = 14'b0_000000_1111111;
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|
|
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ROM_WE_ARRAY[2'b00] = 14'b1_000000_0000000;
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ROM_WE_ARRAY[2'b01] = 14'b1_000000_1111111;
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ROM_WE_ARRAY[2'b10] = 14'b1_111111_0000000;
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ROM_WE_ARRAY[2'b11] = 14'b1_111111_1111111;
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|
|
|
ROM_OE_ARRAY[2'b00] = 14'b1_111111_1111111;
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ROM_OE_ARRAY[2'b01] = 14'b1_111111_0000000;
|
|
ROM_OE_ARRAY[2'b10] = 14'b0_000000_1111111;
|
|
ROM_OE_ARRAY[2'b11] = 14'b0_000000_0000000;
|
|
|
|
SNES_DATA_TO_MEM_ARRAY[1'b0] = 14'b0_000100_0000000; // SNES write
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|
SNES_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // SNES read
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|
|
|
MCU_DATA_TO_MEM_ARRAY[1'b0] = 14'b1_111111_1111111; // MCU write
|
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MCU_DATA_TO_MEM_ARRAY[1'b1] = 14'b0_000000_0000000; // MCU read
|
|
|
|
ROM_DATA_TO_SNES_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // SNES write
|
|
ROM_DATA_TO_SNES_MEM_ARRAY[1'b1] = 14'b0_000010_0000000; // SNES read
|
|
|
|
ROM_DATA_TO_MCU_MEM_ARRAY[1'b0] = 14'b0_000000_0000000; // MCU write
|
|
ROM_DATA_TO_MCU_MEM_ARRAY[1'b1] = 14'b0_000000_0000001; // MCU read
|
|
|
|
end
|
|
|
|
// falling edge of SNES /RD or /WR marks the beginning of a new cycle
|
|
// SNES READ or WRITE always starts @posedge CLK !!
|
|
// CPU cycle can be 6, 8 or 12 CLKIN cycles so we must satisfy
|
|
// the minimum of 6 SNES cycles to get everything done.
|
|
// we have 24 internal cycles to work with. (CLKIN * 4)
|
|
|
|
always @(posedge CLK2) begin
|
|
CYCLE_RESET <= {CYCLE_RESET[0], SNES_cycle_start};
|
|
end
|
|
|
|
reg[7:0] STATECNT;
|
|
initial STATECNT = 0;
|
|
|
|
always @(posedge CLK2) begin
|
|
MCU_READ_CYCLE <= MCU_READ;
|
|
MCU_WRITE_CYCLE <= MCU_WRITE;
|
|
if (SNES_cycle_start) begin
|
|
SNES_READ_CYCLE <= SNES_READ;
|
|
SNES_WRITE_CYCLE <= SNES_WRITE;
|
|
STATE <= STATE_0;
|
|
STATEIDX <= 12;
|
|
STATECNT <= 0;
|
|
end else begin
|
|
STATECNT <= STATECNT + 1;
|
|
case (STATE)
|
|
STATE_0: begin
|
|
SNES_WRITE_CYCLE <= SNES_WRITE;
|
|
STATE <= STATE_1; STATEIDX <= 11;
|
|
end
|
|
STATE_1: begin
|
|
STATE <= STATE_2; STATEIDX <= 10;
|
|
end
|
|
STATE_2: begin
|
|
STATE <= STATE_3; STATEIDX <= 9;
|
|
end
|
|
STATE_3: begin
|
|
STATE <= STATE_4; STATEIDX <= 8;
|
|
end
|
|
STATE_4: begin
|
|
STATE <= STATE_5; STATEIDX <= 7;
|
|
end
|
|
STATE_5: begin
|
|
STATE <= STATE_6; STATEIDX <= 6;
|
|
end
|
|
STATE_6: begin
|
|
STATE <= STATE_7; STATEIDX <= 5;
|
|
end
|
|
STATE_7: begin
|
|
STATE <= STATE_8; STATEIDX <= 4;
|
|
end
|
|
STATE_8: begin
|
|
STATE <= STATE_9; STATEIDX <= 3;
|
|
end
|
|
STATE_9: begin
|
|
STATE <= STATE_10; STATEIDX <= 2;
|
|
end
|
|
STATE_10: begin
|
|
STATE <= STATE_11; STATEIDX <= 1;
|
|
end
|
|
STATE_11: begin
|
|
STATE <= STATE_12; STATEIDX <= 0;
|
|
end
|
|
STATE_12: begin
|
|
STATE <= STATE_IDLE; STATEIDX <= 13;
|
|
end
|
|
STATE_IDLE: begin
|
|
STATE <= STATE_IDLE; STATEIDX <= 13;
|
|
end
|
|
default: begin
|
|
STATE <= STATE_IDLE; STATEIDX <= 13;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// When in MCU mode, enable SRAM_WE according to MCU programming
|
|
// else enable SRAM_WE according to state&cycle
|
|
assign ROM_WE = !MCU_OVR
|
|
?MCU_WRITE
|
|
:((!IS_FLASHWR & !IS_WRITABLE & !MODE)
|
|
| ROM_WE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX]);
|
|
|
|
// When in MCU mode, enable SRAM_OE whenever not writing
|
|
// else enable SRAM_OE according to state&cycle
|
|
assign ROM_OE = !MCU_OVR
|
|
?MCU_READ
|
|
:ROM_OE_ARRAY[{SNES_WRITE_CYCLE, MCU_WRITE_CYCLE}][STATEIDX];
|
|
|
|
assign ROM_CE = 1'b0; // !MCU_OVR ? (MCU_READ & MCU_WRITE) : ROM_SEL;
|
|
|
|
assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
|
|
assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
|
|
|
|
//assign SRAM_BHE = SRAM_ADDR0;
|
|
//assign SRAM_BLE = ~SRAM_ADDR0;
|
|
|
|
// dumb version
|
|
//assign SRAM_OE = !MCU_ENA ? MCU_READ : SNES_READs;
|
|
//assign SRAM_WE = !MCU_ENA ? MCU_WRITE : 1'b1;
|
|
|
|
//assign SNES_DATABUS_OE = (!IS_SAVERAM & SNES_CS) | (SNES_READ & SNES_WRITE);
|
|
assign SNES_DATABUS_OE = (dspx_enable | dspx_dp_enable) ? 1'b0 :
|
|
msu_enable ? 1'b0 :
|
|
bsx_data_ovr ? (SNES_READ & SNES_WRITE) :
|
|
srtc_enable ? (SNES_READ & SNES_WRITE) :
|
|
((IS_ROM & SNES_CS)
|
|
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|
|
|(SNES_READ & SNES_WRITE)
|
|
);
|
|
|
|
assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
|
|
|
|
assign SNES_DATA_TO_MEM = SNES_DATA_TO_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
|
|
assign MCU_DATA_TO_MEM = MCU_DATA_TO_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
|
|
|
|
assign ROM_DATA_TO_SNES_MEM = ROM_DATA_TO_SNES_MEM_ARRAY[SNES_WRITE_CYCLE][STATEIDX];
|
|
assign ROM_DATA_TO_MCU_MEM = ROM_DATA_TO_MCU_MEM_ARRAY[MCU_WRITE_CYCLE][STATEIDX];
|
|
|
|
assign SNES_READ_CYCLEw = SNES_READ_CYCLE;
|
|
assign SNES_WRITE_CYCLEw = SNES_WRITE_CYCLE;
|
|
assign IRQ_DIR = 1'b0;
|
|
assign SNES_IRQ = 1'bZ;
|
|
|
|
endmodule
|