151 lines
2.5 KiB
Verilog
151 lines
2.5 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 09:28:48 05/31/2011
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// Design Name: upd77c25
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// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/updtest.tf
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// Project Name: sd2snes
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: upd77c25
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module updtest;
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// Inputs
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reg [7:0] DI;
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reg A0;
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reg nCS;
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reg nRD;
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reg nWR;
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reg RST;
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reg CLK;
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reg PGM_WR;
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reg [23:0] PGM_DI;
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reg [10:0] PGM_WR_ADDR;
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reg DAT_WR;
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reg [15:0] DAT_DI;
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reg [9:0] DAT_WR_ADDR;
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// debug
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wire [15:0] SR;
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wire [15:0] DR;
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wire [10:0] PC;
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wire [15:0] A;
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wire [15:0] B;
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wire [5:0] FL_A;
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wire [5:0] FL_B;
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// Outputs
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wire [7:0] DO;
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// variables
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integer i;
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// Instantiate the Unit Under Test (UUT)
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upd77c25 uut (
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.DI(DI),
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.DO(DO),
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.A0(A0),
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.nCS(nCS),
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.nRD(nRD),
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.nWR(nWR),
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.DP_nCS(1'b1),
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.RST(RST),
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.CLK(CLK),
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.PGM_WR(PGM_WR),
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.PGM_DI(PGM_DI),
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.PGM_WR_ADDR(PGM_WR_ADDR),
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.DAT_WR(DAT_WR),
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.DAT_DI(DAT_DI),
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.DAT_WR_ADDR(DAT_WR_ADDR),
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.SR(SR),
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.DR(DR),
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.PC(PC),
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.A(A),
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.B(B),
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.FL_A(FL_A),
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.FL_B(FL_B)
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);
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initial begin
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// Initialize Inputs
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DI = 0;
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A0 = 0;
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nCS = 0;
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nRD = 1;
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nWR = 1;
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RST = 1;
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CLK = 0;
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PGM_WR = 0;
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PGM_DI = 0;
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PGM_WR_ADDR = 0;
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DAT_WR = 0;
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DAT_DI = 0;
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DAT_WR_ADDR = 0;
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// Wait 100 ns for global reset to finish
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#1000;
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// Add stimulus here
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nRD = 0;
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#100 nRD = 1;
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for (i=0; i < 1; i = i + 1) begin
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#200 nRD = 0;
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#200 nRD = 1;
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end
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#1000 DI = 8'h02;
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nWR = 0;
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#200 nWR = 1;
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#3000 DI = 8'hc2;
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for (i=0; i < 6; i = i + 1) begin
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#400 nWR = 0;
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#400 nWR = 1;
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#400 nWR = 0;
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#400 nWR = 1;
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end
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#15000;
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#200 nWR = 0;
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#200 nWR = 1;
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#200 nWR = 0;
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#200 nWR = 1;
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#50000;
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for (i=0; i < 10; i = i + 1) begin
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#200 nRD = 0;
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#200 nRD = 1;
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end
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#200 DI = 8'h06;
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nWR = 0;
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#200 nWR = 1;
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#200 DI = 8'h7f;
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for (i=0; i < 3; i = i + 1) begin
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#400 nWR = 0;
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#400 nWR = 1;
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#400 nWR = 0;
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#400 nWR = 1;
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end
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#15000;
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for (i=0; i < 10; i = i + 1) begin
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#200 nRD = 0;
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#200 nRD = 1;
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end
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end
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always #6 CLK = ~CLK;
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endmodule
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