95 lines
2.3 KiB
Plaintext
95 lines
2.3 KiB
Plaintext
EESchema Schematic File Version 2 date Mon 02 Jan 2012 11:27:18 PM CET
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:snescart
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LIBS:misc-74
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LIBS:vreg
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LIBS:lpc1754
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LIBS:sd_card
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LIBS:cy62148ev30
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LIBS:mt45w8mw16
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LIBS:cs4344
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LIBS:double_sch_kcom
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LIBS:usb_minib
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LIBS:mic23250
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LIBS:sd2snes-cache
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EELAYER 25 0
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EELAYER END
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$Descr A4 11700 8267
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encoding utf-8
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Sheet 1 6
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Title "sd2snes Mark II"
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Date "2 jan 2012"
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Rev "E2"
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Comp "Maximilian Rehkopf"
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Notes Line
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3650 4200 6150 4200
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Text Notes 3300 3250 0 100 ~ 0
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Changes from Rev.A / TODO:\n [x] remove FPGA from JTAG chain\n [x] remove SNES IRQ_DIR+IRQ, replace with IRQ_OE. IRQ is unidirectional cart -> console\n (replace 1gate w/ transistor)\n [x] disconnect P2.10 from FPGA, using a different GPIO for IRQ / INIT_B\n [x] add pullup to P2.10\n [ ] add JTAG pullups\n [x] add series resistor for CPU_CLK\n [x] add a jumper in PIC MCLR line to MCU\n [x] change PIC to DIP8 type for easier preprogramming\n [x] change "P1" to "P401" in pin description in silk screen\n [x] filter CIC data lines\n [x] rearrange SD card interface/LEDs on MCU\n [x] RAs for SNES signals?\n [x] reroute/add decoupling capacitors\n [x] filter SNES control signals (RD, WR, PARD, PAWR, CPU_CLK, IRQ)\n [x] replace 4Mbit SRAM with much cheaper TSOP-II type\n [x] add inverse polarity protection\n [x] separate GND plane for DAC\n [ ] separate JTAG pads for FPGA\n [x] add USE_BATT jumper\n [x] move PROG_B to P1.15
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$Sheet
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S 1250 1250 1700 1250
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U 4B6E16F2
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F0 "SNES Slot" 60
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F1 "snesslot.sch" 60
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$EndSheet
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Text Notes 750 7700 0 500 ~ 100
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sd2snes Mark II
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$Sheet
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S 1250 3300 1600 1150
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U 4BAA6ABD
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F0 "Memory" 60
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F1 "memory.sch" 60
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$EndSheet
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$Sheet
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S 8050 1250 1600 1250
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U 4B6ED75B
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F0 "MCU" 60
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F1 "mcu.sch" 60
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$EndSheet
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$Sheet
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S 5900 1250 1600 1250
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U 4B6EC9C3
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F0 "Power Supply / Misc." 60
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F1 "pwr_misc.sch" 60
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$EndSheet
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$Sheet
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S 3650 1250 1650 1250
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U 4B6E18FC
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F0 "FPGA" 60
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F1 "fpga.sch" 60
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$EndSheet
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$EndSCHEMATC
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