98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
#ifndef _CONFIG_H
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#define _CONFIG_H
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// #define DEBUG_FS
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// #define DEBUG_SD
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// #define DEBUG_IRQ
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// #define DEBUG_MSU1
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#define VER "0.0.1(NSFW)"
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#define IN_AHBRAM __attribute__ ((section(".ahbram")))
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#define SD_DT_INT_SETUP() do {\
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BITBAND(LPC_GPIOINT->IO2IntEnR, SD_DT_BIT) = 1;\
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BITBAND(LPC_GPIOINT->IO2IntEnF, SD_DT_BIT) = 1;\
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} while(0)
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#define SD_CHANGE_DETECT (BITBAND(LPC_GPIOINT->IO2IntStatR, SD_DT_BIT)\
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|BITBAND(LPC_GPIOINT->IO2IntStatF, SD_DT_BIT))
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#define SD_CHANGE_CLR() do {LPC_GPIOINT->IO2IntClr = BV(SD_DT_BIT);} while(0)
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#define SD_DT_REG LPC_GPIO0
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#define SD_DT_BIT 8
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#define SD_WP_REG LPC_GPIO0
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#define SD_WP_BIT 6
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#define SDCARD_DETECT (!(BITBAND(SD_DT_REG->FIOPIN, SD_DT_BIT)))
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#define SDCARD_WP (BITBAND(SD_WP_REG->FIOPIN, SD_WP_BIT))
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#define SD_SUPPLY_VOLTAGE (1L<<21) /* 3.3V - 3.4V */
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#define CONFIG_SD_BLOCKTRANSFER 1
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#define CONFIG_SD_AUTO_RETRIES 10
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// #define SD_CHANGE_VECT
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// #define CONFIG_SD_DATACRC 1
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#define CONFIG_UART_NUM 3
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// #define CONFIG_CPU_FREQUENCY 90315789
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#define CONFIG_CPU_FREQUENCY 96000000
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//#define CONFIG_CPU_FREQUENCY 46000000
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#define CONFIG_UART_PCLKDIV 1
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#define CONFIG_UART_TX_BUF_SHIFT 8
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#define CONFIG_UART_BAUDRATE 921600
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#define CONFIG_UART_DEADLOCKABLE
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#define SSP_CLK_DIVISOR_FAST 2
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#define SSP_CLK_DIVISOR_SLOW 250
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#define SSP_CLK_DIVISOR_FPGA_FAST 6
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#define SSP_CLK_DIVISOR_FPGA_SLOW 20
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#define SNES_RESET_REG LPC_GPIO1
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#define SNES_RESET_BIT 26
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#define SNES_CIC_D0_REG LPC_GPIO0
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#define SNES_CIC_D0_BIT 1
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#define SNES_CIC_D1_REG LPC_GPIO0
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#define SNES_CIC_D1_BIT 0
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#define SNES_CIC_STATUS_REG LPC_GPIO1
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#define SNES_CIC_STATUS_BIT 29
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#define SNES_CIC_PAIR_REG LPC_GPIO1
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#define SNES_CIC_PAIR_BIT 25
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#define FPGA_MCU_RDY_REG LPC_GPIO2
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#define FPGA_MCU_RDY_BIT 9
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#define QSORT_MAXELEM 2048
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#define CLTBL_SIZE 100
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#define SSP_REGS LPC_SSP0
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#define SSP_PCLKREG PCLKSEL1
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// 1: PCLKSEL0
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#define SSP_PCLKBIT 10
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// 1: 20
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#define SSP_DMAID_TX 0
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// 1: 2
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#define SSP_DMAID_RX 1
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// 1: 3
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#define SSP_DMACH LPC_GPDMACH0
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#define SD_CLKREG LPC_GPIO0
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#define SD_CMDREG LPC_GPIO0
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#define SD_DAT0REG LPC_GPIO2
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#define SD_DAT1REG LPC_GPIO2
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#define SD_DAT2REG LPC_GPIO2
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#define SD_DAT3REG LPC_GPIO2
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#define SD_CLKPIN (7)
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#define SD_CMDPIN (9)
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#define SD_DAT0PIN (0)
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#define SD_DAT1PIN (1)
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#define SD_DAT2PIN (2)
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#define SD_DAT3PIN (3)
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#define SD_DAT (LPC_GPIO2->FIOPIN0)
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#endif
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