152 lines
2.9 KiB
Verilog
152 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 14:40:38 05/31/2011
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// Design Name: main
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// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/main_tf.v
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// Project Name: sd2snes
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: main
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module main_tf;
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// Inputs
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reg CLKIN;
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reg [23:0] SNES_ADDR;
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reg SNES_READ;
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reg SNES_WRITE;
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reg SNES_CS;
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reg SNES_CPU_CLK;
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reg SNES_REFRESH;
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reg SNES_SYSCLK;
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reg SPI_MOSI;
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reg SPI_SS;
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reg MCU_OVR;
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reg [3:0] SD_DAT;
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// Outputs
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wire SNES_DATABUS_OE;
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wire SNES_DATABUS_DIR;
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wire IRQ_DIR;
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wire [22:0] ROM_ADDR;
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wire ROM_CE;
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wire ROM_OE;
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wire ROM_WE;
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wire ROM_BHE;
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wire ROM_BLE;
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wire [18:0] RAM_ADDR;
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wire RAM_CE;
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wire RAM_OE;
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wire RAM_WE;
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wire DAC_MCLK;
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wire DAC_LRCK;
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wire DAC_SDOUT;
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// Bidirs
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wire [7:0] SNES_DATA;
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wire SNES_IRQ;
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wire [15:0] ROM_DATA;
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wire [7:0] RAM_DATA;
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wire SPI_MISO;
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wire SPI_SCK;
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wire SD_CMD;
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wire SD_CLK;
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// Instantiate the Unit Under Test (UUT)
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main uut (
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.CLKIN(CLKIN),
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.SNES_ADDR(SNES_ADDR),
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.SNES_READ(SNES_READ),
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.SNES_WRITE(SNES_WRITE),
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.SNES_CS(SNES_CS),
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.SNES_DATA(SNES_DATA),
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.SNES_CPU_CLK(SNES_CPU_CLK),
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.SNES_REFRESH(SNES_REFRESH),
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.SNES_IRQ(SNES_IRQ),
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.SNES_DATABUS_OE(SNES_DATABUS_OE),
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.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
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.IRQ_DIR(IRQ_DIR),
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.SNES_SYSCLK(SNES_SYSCLK),
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.ROM_DATA(ROM_DATA),
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.ROM_ADDR(ROM_ADDR),
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.ROM_CE(ROM_CE),
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.ROM_OE(ROM_OE),
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.ROM_WE(ROM_WE),
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.ROM_BHE(ROM_BHE),
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.ROM_BLE(ROM_BLE),
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.RAM_DATA(RAM_DATA),
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.RAM_ADDR(RAM_ADDR),
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.RAM_CE(RAM_CE),
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.RAM_OE(RAM_OE),
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.RAM_WE(RAM_WE),
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.SPI_MOSI(SPI_MOSI),
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.SPI_MISO(SPI_MISO),
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.SPI_SS(SPI_SS),
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.SPI_SCK(SPI_SCK),
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.MCU_OVR(MCU_OVR),
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.DAC_MCLK(DAC_MCLK),
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.DAC_LRCK(DAC_LRCK),
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.DAC_SDOUT(DAC_SDOUT),
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.SD_DAT(SD_DAT),
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.SD_CMD(SD_CMD),
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.SD_CLK(SD_CLK)
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);
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integer i;
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reg [7:0] SNES_DATA_OUT;
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reg [7:0] SNES_DATA_IN;
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assign SNES_DATA = (!SNES_READ) ? 8'bZ : SNES_DATA_IN;
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initial begin
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// Initialize Inputs
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CLKIN = 0;
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SNES_ADDR = 0;
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SNES_READ = 1;
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SNES_WRITE = 1;
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SNES_CS = 0;
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SNES_CPU_CLK = 0;
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SNES_REFRESH = 0;
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SNES_SYSCLK = 0;
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SPI_MOSI = 0;
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SPI_SS = 0;
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MCU_OVR = 1;
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SD_DAT = 0;
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// Wait 100 ns for global reset to finish
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#500;
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// Add stimulus here
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SNES_ADDR = 24'h208000;
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SNES_DATA_IN = 8'h1f;
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SNES_WRITE = 0;
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#100 SNES_WRITE = 1;
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#100;
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for (i = 0; i < 4096; i = i + 1) begin
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#140 SNES_READ = 0;
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SNES_CPU_CLK = 1;
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#140 SNES_READ = 1;
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SNES_CPU_CLK = 0;
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end
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end
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always #24 CLKIN = ~CLKIN;
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endmodule
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