406 lines
9.9 KiB
Verilog
406 lines
9.9 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: main
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Master Control FSM
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//
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// Dependencies: address
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module main(
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/* input clock */
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input CLKIN,
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/* SNES signals */
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input [23:0] SNES_ADDR,
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input SNES_READ,
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input SNES_WRITE,
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input SNES_CS,
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inout [7:0] SNES_DATA,
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input SNES_CPU_CLK,
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input SNES_REFRESH,
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output SNES_IRQ,
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output SNES_DATABUS_OE,
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output SNES_DATABUS_DIR,
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input SNES_SYSCLK,
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/* SRAM signals */
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/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
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inout [15:0] ROM_DATA,
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output [22:0] ROM_ADDR,
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output ROM_CE,
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output ROM_OE,
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output ROM_WE,
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output ROM_BHE,
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output ROM_BLE,
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/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
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inout [7:0] RAM_DATA,
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output [18:0] RAM_ADDR,
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output RAM_CE,
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output RAM_OE,
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output RAM_WE,
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/* MCU signals */
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input SPI_MOSI,
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inout SPI_MISO,
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input SPI_SS,
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inout SPI_SCK,
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input MCU_OVR,
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output MCU_RDY,
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output DAC_MCLK,
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output DAC_LRCK,
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output DAC_SDOUT,
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/* SD signals */
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input [3:0] SD_DAT,
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inout SD_CMD,
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inout SD_CLK,
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/* debug */
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output p113_out
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);
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assign DAC_MCLK = 1'b0;
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assign DAC_LRCK = 1'b0;
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assign DAC_SDOUT = 1'b0;
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assign SD_CMD = 1'bZ;
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assign SD_CLK = 1'bZ;
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wire [7:0] spi_cmd_data;
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wire [7:0] spi_param_data;
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wire [7:0] spi_input_data;
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wire [31:0] spi_byte_cnt;
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wire [2:0] spi_bit_cnt;
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wire [23:0] MCU_ADDR;
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wire [7:0] mcu_data_in;
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wire [7:0] mcu_data_out;
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wire [3:0] MAPPER;
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wire [23:0] SAVERAM_MASK;
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wire [23:0] ROM_MASK;
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wire [23:0] MAPPED_SNES_ADDR;
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wire ROM_ADDR0;
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spi snes_spi(
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.clk(CLK2),
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.MOSI(SPI_MOSI),
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.MISO(SPI_MISO),
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.SSEL(SPI_SS),
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.SCK(SPI_SCK),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.input_data(spi_input_data),
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.byte_cnt(spi_byte_cnt),
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.bit_cnt(spi_bit_cnt)
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);
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reg [7:0] MCU_DINr;
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wire [7:0] MCU_DOUT;
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mcu_cmd snes_mcu_cmd(
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.clk(CLK2),
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.cmd_ready(spi_cmd_ready),
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.param_ready(spi_param_ready),
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.cmd_data(spi_cmd_data),
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.param_data(spi_param_data),
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.mcu_sram_size(SRAM_SIZE),
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.mcu_write(MCU_WRITE),
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.mcu_data_in(MCU_DINr),
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.mcu_data_out(MCU_DOUT),
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.spi_byte_cnt(spi_byte_cnt),
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.spi_bit_cnt(spi_bit_cnt),
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.spi_data_out(spi_input_data),
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.addr_out(MCU_ADDR),
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.endmessage(spi_endmessage),
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.startmessage(spi_startmessage),
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.saveram_mask_out(SAVERAM_MASK),
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.rom_mask_out(ROM_MASK),
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.mcu_rrq(MCU_RRQ),
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.mcu_wrq(MCU_WRQ),
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.mcu_rq_rdy(MCU_RDY)
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);
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// dcm1: dfs 4x
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my_dcm snes_dcm(
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.CLKIN(CLKIN),
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.CLKFX(CLK2),
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.LOCKED(DCM_LOCKED),
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.RST(DCM_RST),
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.STATUS(DCM_STATUS)
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);
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assign DCM_RST=0;
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reg [5:0] SNES_READr;
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reg [5:0] SNES_WRITEr;
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reg [12:0] SNES_CPU_CLKr;
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reg [5:0] SNES_RWr;
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reg [23:0] SNES_ADDRr;
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wire SNES_RW = (SNES_READ & SNES_WRITE);
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wire SNES_RW_start = (SNES_RWr == 6'b111110); // falling edge marks beginning of cycle
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wire SNES_RD_start = (SNES_READr == 6'b111110);
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wire SNES_WR_start = (SNES_WRITEr == 6'b111110);
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wire SNES_cycle_start = (SNES_CPU_CLKr[5:0] == 6'b000001);
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wire SNES_cycle_end = (SNES_CPU_CLKr[5:0] == 6'b111110);
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always @(posedge CLK2) begin
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SNES_READr <= {SNES_READr[4:0], SNES_READ};
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SNES_WRITEr <= {SNES_WRITEr[4:0], SNES_WRITE};
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SNES_CPU_CLKr <= {SNES_CPU_CLKr[11:0], SNES_CPU_CLK};
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SNES_RWr <= {SNES_RWr[4:0], SNES_RW};
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end
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wire ROM_SEL;
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address snes_addr(
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.CLK(CLK2),
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.SNES_ADDR(SNES_ADDR), // requested address from SNES
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.SNES_CS(SNES_CS), // "CART" pin from SNES (active low)
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.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
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.ROM_SEL(ROM_SEL), // which SRAM unit to access
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.IS_SAVERAM(IS_SAVERAM),
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.IS_ROM(IS_ROM),
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.MCU_ADDR(MCU_ADDR),
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.SAVERAM_MASK(SAVERAM_MASK),
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.ROM_MASK(ROM_MASK)
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);
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wire SNES_READ_CYCLEw;
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wire SNES_WRITE_CYCLEw;
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wire MCU_READ_CYCLEw;
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wire MCU_WRITE_CYCLEw;
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parameter MODE_SNES = 1'b0;
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parameter MODE_MCU = 1'b1;
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parameter ST_IDLE = 18'b000000000000000001;
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parameter ST_SNES_RD_ADDR = 18'b000000000000000010;
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parameter ST_SNES_RD_WAIT = 18'b000000000000000100;
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parameter ST_SNES_RD_END = 18'b000000000000001000;
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parameter ST_SNES_WR_ADDR = 18'b000000000000010000;
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parameter ST_SNES_WR_WAIT1= 18'b000000000000100000;
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parameter ST_SNES_WR_DATA = 18'b000000000001000000;
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parameter ST_SNES_WR_WAIT2= 18'b000000000010000000;
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parameter ST_SNES_WR_END = 18'b000000000100000000;
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parameter ST_MCU_RD_ADDR = 18'b000000001000000000;
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parameter ST_MCU_RD_WAIT = 18'b000000010000000000;
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parameter ST_MCU_RD_WAIT2 = 18'b000000100000000000;
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parameter ST_MCU_RD_END = 18'b000001000000000000;
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parameter ST_MCU_WR_ADDR = 18'b000010000000000000;
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parameter ST_MCU_WR_WAIT = 18'b000100000000000000;
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parameter ST_MCU_WR_WAIT2 = 18'b001000000000000000;
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parameter ST_MCU_WR_END = 18'b010000000000000000;
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parameter ROM_RD_WAIT = 4'h4;
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parameter ROM_RD_WAIT_MCU = 4'h5;
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parameter ROM_WR_WAIT1 = 4'h2;
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parameter ROM_WR_WAIT2 = 4'h3;
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parameter ROM_WR_WAIT_MCU = 4'h6;
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reg [17:0] STATE;
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initial STATE = ST_IDLE;
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reg [1:0] CYCLE_RESET;
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reg ROM_WE_MASK;
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reg ROM_OE_MASK;
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reg [7:0] SNES_DINr;
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reg [7:0] ROM_DOUTr;
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assign SNES_DATA = (!SNES_READ) ? SNES_DINr : 8'bZ;
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reg [3:0] ST_MEM_DELAYr;
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reg MCU_RD_PENDr;
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reg MCU_WR_PENDr;
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reg [23:0] ROM_ADDRr;
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reg NEED_SNES_ADDRr;
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always @(posedge CLK2) begin
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if(SNES_cycle_end) NEED_SNES_ADDRr <= 1'b1;
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else if(STATE & (ST_SNES_RD_END | ST_SNES_WR_END)) NEED_SNES_ADDRr <= 1'b0;
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end
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wire ASSERT_SNES_ADDR = SNES_CPU_CLK & NEED_SNES_ADDRr;
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assign ROM_ADDR = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[23:1] : ROM_ADDRr[23:1];
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assign ROM_ADDR0 = (ASSERT_SNES_ADDR) ? MAPPED_SNES_ADDR[0] : ROM_ADDRr[0];
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reg ROM_WEr;
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initial ROM_WEr = 1'b1;
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reg RQ_MCU_RDYr;
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initial RQ_MCU_RDYr = 1'b1;
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assign MCU_RDY = RQ_MCU_RDYr;
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always @(posedge CLK2) begin
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if(MCU_RRQ) begin
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MCU_RD_PENDr <= 1'b1;
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RQ_MCU_RDYr <= 1'b0;
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end else if(MCU_WRQ) begin
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MCU_WR_PENDr <= 1'b1;
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RQ_MCU_RDYr <= 1'b0;
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end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
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MCU_RD_PENDr <= 1'b0;
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MCU_WR_PENDr <= 1'b0;
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RQ_MCU_RDYr <= 1'b1;
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end
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end
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reg snes_wr_cycle;
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always @(posedge CLK2) begin
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if(SNES_cycle_start) begin
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STATE <= ST_SNES_RD_ADDR;
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end else if(SNES_WR_start) begin
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STATE <= ST_SNES_WR_ADDR;
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end else begin
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case(STATE)
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ST_IDLE: begin
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ROM_ADDRr <= MAPPED_SNES_ADDR;
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if(MCU_RD_PENDr) STATE <= ST_MCU_RD_ADDR;
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else if(MCU_WR_PENDr) STATE <= ST_MCU_WR_ADDR;
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else STATE <= ST_IDLE;
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end
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ST_SNES_RD_ADDR: begin
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STATE <= ST_SNES_RD_WAIT;
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ST_MEM_DELAYr <= ROM_RD_WAIT;
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end
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ST_SNES_RD_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_RD_END;
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else STATE <= ST_SNES_RD_WAIT;
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if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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else SNES_DINr <= ROM_DATA[15:8];
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end
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ST_SNES_RD_END: begin
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STATE <= ST_IDLE;
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if(ROM_ADDR0) SNES_DINr <= ROM_DATA[7:0];
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else SNES_DINr <= ROM_DATA[15:8];
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end
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ST_SNES_WR_ADDR: begin
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ROM_WEr <= (!IS_SAVERAM);
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snes_wr_cycle <= 1'b1;
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STATE <= ST_SNES_WR_WAIT1;
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ST_MEM_DELAYr <= ROM_WR_WAIT1;
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end
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ST_SNES_WR_WAIT1: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_DATA;
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else STATE <= ST_SNES_WR_WAIT1;
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end
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ST_SNES_WR_DATA: begin
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ROM_DOUTr <= SNES_DATA;
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ST_MEM_DELAYr <= ROM_WR_WAIT2;
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STATE <= ST_SNES_WR_WAIT2;
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end
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ST_SNES_WR_WAIT2: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) STATE <= ST_SNES_WR_END;
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else STATE <= ST_SNES_WR_WAIT2;
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end
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ST_SNES_WR_END: begin
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STATE <= ST_IDLE;
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ROM_WEr <= 1'b1;
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snes_wr_cycle <= 1'b0;
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end
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ST_MCU_RD_ADDR: begin
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ROM_ADDRr <= MCU_ADDR;
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STATE <= ST_MCU_RD_WAIT;
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ST_MEM_DELAYr <= ROM_RD_WAIT_MCU;
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end
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ST_MCU_RD_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) begin
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STATE <= ST_MCU_RD_WAIT2;
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ST_MEM_DELAYr <= 4'h2;
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end
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else STATE <= ST_MCU_RD_WAIT;
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if(ROM_ADDR0) MCU_DINr <= ROM_DATA[7:0];
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else MCU_DINr <= ROM_DATA[15:8];
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end
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ST_MCU_RD_WAIT2: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) begin
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STATE <= ST_MCU_RD_END;
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end else STATE <= ST_MCU_RD_WAIT2;
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end
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ST_MCU_RD_END: begin
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STATE <= ST_IDLE;
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end
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ST_MCU_WR_ADDR: begin
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ROM_ADDRr <= MCU_ADDR;
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STATE <= ST_MCU_WR_WAIT;
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ST_MEM_DELAYr <= ROM_WR_WAIT_MCU;
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ROM_DOUTr <= MCU_DOUT;
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ROM_WEr <= 1'b0;
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end
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ST_MCU_WR_WAIT: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) begin
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ROM_WEr <= 1'b1;
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STATE <= ST_MCU_WR_WAIT2;
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ST_MEM_DELAYr <= 4'h2;
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end
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else STATE <= ST_MCU_WR_WAIT;
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end
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ST_MCU_WR_WAIT2: begin
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ST_MEM_DELAYr <= ST_MEM_DELAYr - 4'h1;
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if(ST_MEM_DELAYr == 4'h0) begin
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STATE <= ST_MCU_WR_END;
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end else STATE <= ST_MCU_WR_WAIT2;
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end
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ST_MCU_WR_END: begin
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STATE <= ST_IDLE;
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end
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endcase
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end
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end
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assign ROM_DATA[7:0] = ROM_ADDR0
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?(!ROM_WE ? ROM_DOUTr : 8'bZ)
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:8'bZ;
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assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
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:(!ROM_WE ? ROM_DOUTr : 8'bZ);
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assign ROM_WE = ROM_WEr | (ASSERT_SNES_ADDR & ~snes_wr_cycle);
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assign ROM_OE = 1'b0;
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assign ROM_CE = 1'b0;
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assign ROM_BHE = !ROM_WE ? ROM_ADDR0 : 1'b0;
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assign ROM_BLE = !ROM_WE ? !ROM_ADDR0 : 1'b0;
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assign SNES_DATABUS_OE = ((IS_ROM & SNES_CS)
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|(!IS_ROM & !IS_SAVERAM)
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|(SNES_READ & SNES_WRITE)
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);
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assign SNES_DATABUS_DIR = !SNES_READ ? 1'b1 : 1'b0;
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assign SNES_IRQ = 1'b0;
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assign p113_out = 1'b0;
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endmodule
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