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godzil
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sd2snes
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sd2snes
/
verilog
/
sd2sneslite
History
Maximilian Rehkopf
7df6909266
FPGA: rework shared memory access FSM
2012-07-09 02:12:59 +02:00
..
address.v
FPGA: adjust menu memory mapping to make more room for file database
2012-06-10 20:07:45 +02:00
data.v
FPGA: merge recent changes into sd2sneslite
2011-10-08 17:05:22 +02:00
dcm.v
FPGA: merge recent changes into sd2sneslite
2011-10-08 17:05:22 +02:00
main.ucf
FPGA: update clock speed to 88MHz
2012-07-09 01:54:05 +02:00
main.v
FPGA: rework shared memory access FSM
2012-07-09 02:12:59 +02:00
mcu_cmd.v
FPGA/sd2sneslite: add missing file mcu_cmd.v; remove avr_cmd.v
2012-07-09 01:55:02 +02:00
sd2sneslite.xise
FPGA: adjust menu memory mapping to make more room for file database
2012-06-10 20:07:45 +02:00
spi.v
FPGA: properly synchronize external signals
2012-07-09 01:48:43 +02:00