382 lines
9.4 KiB
Verilog
382 lines
9.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 23:32:12 01/08/2011
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// Design Name:
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// Module Name: rtc_srtc
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rtc (
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input clkin,
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input pgm_we,
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input [59:0] rtc_data_in,
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output [59:0] rtc_data
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);
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reg [59:0] rtc_data_r;
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reg [59:0] rtc_data_out_r;
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reg [1:0] pgm_we_sreg;
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always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
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wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
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reg [31:0] tick_cnt;
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always @(posedge clkin) begin
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tick_cnt <= tick_cnt + 1;
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if(tick_cnt == 23000000) tick_cnt <= 0;
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end
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assign rtc_data = rtc_data_out_r;
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reg [21:0] rtc_state;
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reg [21:0] next_state;
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reg carry;
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reg [3:0] dom1[11:0];
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reg [3:0] dom10[11:0];
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reg [3:0] month;
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reg [1:0] year;
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reg [4:0] dow_day;
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reg [3:0] dow_month;
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reg [13:0] dow_year;
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reg [6:0] dow_year1;
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reg [6:0] dow_year100;
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reg [15:0] dow_tmp;
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parameter [21:0]
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STATE_SEC1 = 22'b0000000000000000000001,
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STATE_SEC10 = 22'b0000000000000000000010,
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STATE_MIN1 = 22'b0000000000000000000100,
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STATE_MIN10 = 22'b0000000000000000001000,
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STATE_HOUR1 = 22'b0000000000000000010000,
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STATE_HOUR10 = 22'b0000000000000000100000,
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STATE_DAY1 = 22'b0000000000000001000000,
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STATE_DAY10 = 22'b0000000000000010000000,
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STATE_MON1 = 22'b0000000000000100000000,
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STATE_MON10 = 22'b0000000000001000000000,
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STATE_YEAR1 = 22'b0000000000010000000000,
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STATE_YEAR10 = 22'b0000000000100000000000,
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STATE_YEAR100 = 22'b0000000001000000000000,
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STATE_YEAR1000 = 22'b0000000010000000000000,
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STATE_DOW0 = 22'b0000000100000000000000,
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STATE_DOW1 = 22'b0000001000000000000000,
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STATE_DOW2 = 22'b0000010000000000000000,
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STATE_DOW3 = 22'b0000100000000000000000,
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STATE_DOW4 = 22'b0001000000000000000000,
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STATE_DOW5 = 22'b0010000000000000000000,
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STATE_LATCH = 22'b0100000000000000000000,
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STATE_IDLE = 22'b1000000000000000000000;
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initial begin
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rtc_state = STATE_IDLE;
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next_state = STATE_IDLE;
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dom1[0] <= 1; dom10[0] <= 3;
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dom1[1] <= 8; dom10[1] <= 2;
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dom1[2] <= 1; dom10[2] <= 3;
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dom1[3] <= 0; dom10[3] <= 3;
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dom1[4] <= 1; dom10[4] <= 3;
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dom1[5] <= 0; dom10[5] <= 3;
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dom1[6] <= 1; dom10[6] <= 3;
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dom1[7] <= 1; dom10[7] <= 3;
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dom1[8] <= 0; dom10[8] <= 3;
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dom1[9] <= 1; dom10[9] <= 3;
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dom1[10] <= 0; dom10[10] <= 3;
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dom1[11] <= 1; dom10[11] <= 3;
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month <= 0;
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rtc_data_r <= 60'h019900101000000;
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tick_cnt <= 0;
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end
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wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
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always @(posedge clkin) begin
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if(!tick_cnt) begin
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rtc_state <= STATE_SEC1;
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end else begin
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case (rtc_state)
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STATE_SEC1:
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rtc_state <= STATE_SEC10;
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STATE_SEC10:
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rtc_state <= STATE_MIN1;
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STATE_MIN1:
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rtc_state <= STATE_MIN10;
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STATE_MIN10:
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rtc_state <= STATE_HOUR1;
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STATE_HOUR1:
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rtc_state <= STATE_HOUR10;
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STATE_HOUR10:
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rtc_state <= STATE_DAY1;
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STATE_DAY1:
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rtc_state <= STATE_DAY10;
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STATE_DAY10:
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rtc_state <= STATE_MON1;
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STATE_MON1:
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rtc_state <= STATE_MON10;
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STATE_MON10:
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rtc_state <= STATE_YEAR1;
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STATE_YEAR1:
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rtc_state <= STATE_YEAR10;
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STATE_YEAR10:
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rtc_state <= STATE_YEAR100;
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STATE_YEAR100:
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rtc_state <= STATE_YEAR1000;
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STATE_YEAR1000:
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rtc_state <= STATE_DOW0;
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STATE_DOW0:
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rtc_state <= STATE_DOW1;
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STATE_DOW1:
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rtc_state <= STATE_DOW2;
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STATE_DOW2:
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rtc_state <= STATE_DOW3;
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STATE_DOW3:
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rtc_state <= STATE_DOW4;
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STATE_DOW4:
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if(dow_tmp > 13)
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rtc_state <= STATE_DOW4;
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else
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rtc_state <= STATE_DOW5;
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STATE_DOW5:
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rtc_state <= STATE_LATCH;
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STATE_LATCH:
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rtc_state <= STATE_IDLE;
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default:
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rtc_state <= STATE_IDLE;
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endcase
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end
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end
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always @(posedge clkin) begin
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if(pgm_we_rising) begin
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rtc_data_r <= rtc_data_in;
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end else begin
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case(rtc_state)
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STATE_SEC1: begin
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if(rtc_data_r[3:0] == 9) begin
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rtc_data_r[3:0] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
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carry <= 0;
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end
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end
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STATE_SEC10: begin
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if(carry) begin
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if(rtc_data_r[7:4] == 5) begin
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rtc_data_r[7:4] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
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carry <= 0;
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end
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end
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end
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STATE_MIN1: begin
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if(carry) begin
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if(rtc_data_r[11:8] == 9) begin
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rtc_data_r[11:8] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
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carry <= 0;
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end
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end
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end
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STATE_MIN10: begin
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if(carry) begin
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if(rtc_data_r[15:12] == 5) begin
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rtc_data_r[15:12] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
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carry <= 0;
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end
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end
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end
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STATE_HOUR1: begin
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if(carry) begin
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if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
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rtc_data_r[19:16] <= 0;
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carry <= 1;
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end else if (rtc_data_r[19:16] == 9) begin
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rtc_data_r[19:16] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
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carry <= 0;
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end
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end
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end
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STATE_HOUR10: begin
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if(carry) begin
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if(rtc_data_r[23:20] == 2) begin
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rtc_data_r[23:20] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
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carry <= 0;
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end
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end
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end
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STATE_DAY1: begin
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if(carry) begin
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if(rtc_data_r[31:28] == dom10[month] && rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
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rtc_data_r[27:24] <= 0;
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carry <= 1;
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end else if (rtc_data_r[27:24] == 9) begin
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rtc_data_r[27:24] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
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carry <= 0;
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end
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end
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end
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STATE_DAY10: begin
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if(carry) begin
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if(rtc_data_r[31:28] == dom10[month]) begin
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rtc_data_r[31:28] <= 0;
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rtc_data_r[27:24] <= 1;
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carry <= 1;
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end else begin
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rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
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carry <= 0;
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end
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end
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end
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STATE_MON1: begin
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if(carry) begin
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if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
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rtc_data_r[35:32] <= 1;
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carry <= 1;
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end else if (rtc_data_r[35:32] == 9) begin
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rtc_data_r[35:32] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
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carry <= 0;
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end
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end
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end
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STATE_MON10: begin
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if(carry) begin
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if(rtc_data_r[39:36] == 1) begin
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rtc_data_r[39:36] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
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carry <= 0;
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end
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end
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end
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STATE_YEAR1: begin
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month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
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if(carry) begin
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if(rtc_data_r[43:40] == 9) begin
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rtc_data_r[43:40] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
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carry <= 0;
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end
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end
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end
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STATE_YEAR10: begin
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if(carry) begin
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if(rtc_data_r[47:44] == 9) begin
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rtc_data_r[47:44] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
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carry <= 0;
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end
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end
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end
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STATE_YEAR100: begin
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if(carry) begin
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if(rtc_data_r[51:48] == 9) begin
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rtc_data_r[51:48] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
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carry <= 0;
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end
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end
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end
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STATE_YEAR1000: begin
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if(carry) begin
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if(rtc_data_r[55:52] == 9) begin
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rtc_data_r[55:52] <= 0;
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carry <= 1;
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end else begin
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rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
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carry <= 0;
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end
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end
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end
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STATE_DOW0: begin
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dow_year1 <= rtc_data_r[43:40]
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+(rtc_data_r[47:44] << 1) + (rtc_data_r[47:44] << 3);
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dow_year100 <= rtc_data_r[51:48]
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+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
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dow_month <= month + 1;
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dow_day <= rtc_data_r[27:24] + (rtc_data_r[31:28] << 1) + (rtc_data_r[31:28] << 3);
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end
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STATE_DOW1: begin
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year <= dow_year1[1:0];
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if(dow_month <= 2) begin
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dow_month <= dow_month + 10;
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dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6) - 1;
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if(dow_year1)
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dow_year1 <= dow_year1 - 1;
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else begin
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dow_year1 <= 99;
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dow_year100 <= dow_year100 - 1;
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end
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end else begin
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dow_month <= dow_month - 2;
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dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6);
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end
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end
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STATE_DOW2: begin
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dow_tmp <= (83 * dow_month);
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end
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STATE_DOW3: begin
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dow_tmp <= (dow_tmp >> 5)
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+ dow_day
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+ dow_year
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+ (dow_year >> 2)
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- (dow_year100)
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+ (dow_year100 >> 2);
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end
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STATE_DOW4: begin
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dow_tmp <= dow_tmp - 7;
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end
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STATE_DOW5: begin
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rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
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end
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STATE_LATCH: begin
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rtc_data_out_r <= rtc_data_r;
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end
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endcase
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end
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end
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endmodule
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