Logo
Explore More informations Help
Sign In
godzil/sd2snes
1
0
Fork 0
You've already forked sd2snes
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
sd2snes/verilog
History
ikari 8e7f77e49b FPGA/cx4: map ROM above bank 3F/BF
2012-02-27 22:14:19 +01:00
..
sd2snes
FPGA: pull-up SD clock
2012-02-27 22:12:35 +01:00
sd2snes_cx4
FPGA/cx4: map ROM above bank 3F/BF
2012-02-27 22:14:19 +01:00
sd2snes_test
FPGA: add test suite
2011-12-19 22:26:09 +01:00
sd2sneslite
FPGA: clean up (port size mismatches, unused regs/wires, ...)
2011-10-09 14:13:35 +02:00
Powered by Gitea Page: 55ms Template: 3ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API