73 lines
2.1 KiB
Verilog
73 lines
2.1 KiB
Verilog
`timescale 1 ns / 1 ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Rehkopf
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// Engineer: Rehkopf
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//
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// Create Date: 01:13:46 05/09/2009
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// Design Name:
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// Module Name: address
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description: Address logic w/ SaveRAM masking
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//
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// Dependencies:
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//
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// Revision:
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module address(
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input CLK,
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input [23:0] SNES_ADDR, // requested address from SNES
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output [23:0] ram0_addr,
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output [18:0] ram1_addr,
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output [7:0] PA_addr,
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output [12:0] bram_addr,
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input [7:0] ram0_bank,
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input ram0_linear,
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output ram0_enable,
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output ram1_enable,
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output PA_enable,
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output bram_enable,
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output irq_enable,
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output bank_enable,
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output linear_enable
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);
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wire [23:0] SRAM_SNES_ADDR;
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assign ram0bank0_enable = (SNES_ADDR[23:15] == 9'h001) | (SNES_ADDR[23:16] == 8'hC0);
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assign ram0bankx_enable = (SNES_ADDR[23:16] == 8'hC8);
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assign ram0linear_enable = ram0_linear & (SNES_ADDR[22] | SNES_ADDR[15]);
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assign ram0_enable = ram0linear_enable | ram0bank0_enable | ram0bankx_enable;
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assign ram1_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hD);
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assign PA_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hE);
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assign bram_enable = ~ram0_enable & (SNES_ADDR[23:20] == 4'hF);
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wire bank_enable_ = (SNES_ADDR == 24'h0055AA);
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wire irq_enable_ = (SNES_ADDR == 24'h002222);
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wire linear_enable_ = (SNES_ADDR == 24'h003333);
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reg [2:0] bank_enable_r;
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reg [2:0] irq_enable_r;
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reg [2:0] linear_enable_r;
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always @(posedge CLK) begin
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bank_enable_r <= {bank_enable_r[1:0], bank_enable_};
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irq_enable_r <= {irq_enable_r[1:0], irq_enable_};
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linear_enable_r <= {linear_enable_r[1:0], linear_enable_};
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end
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assign bank_enable = bank_enable_r[2];
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assign irq_enable = irq_enable_r[2];
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assign linear_enable = linear_enable_r[2];
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assign ram0_addr = ram0_linear ? SNES_ADDR
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: {2'b00,SNES_ADDR[21:0]};
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assign ram1_addr = SNES_ADDR[18:0];
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assign PA_addr = SNES_ADDR[7:0];
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assign bram_addr = SNES_ADDR[12:0];
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endmodule
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